1 /* 2 * Copyright (c) 1999, 2000 3 * Intel Corporation. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * 20 * This product includes software developed by Intel Corporation and 21 * its contributors. 22 * 23 * 4. Neither the name of Intel Corporation or its contributors may be 24 * used to endorse or promote products derived from this software 25 * without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY INTEL CORPORATION AND CONTRIBUTORS ``AS IS'' 28 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 30 * ARE DISCLAIMED. IN NO EVENT SHALL INTEL CORPORATION OR CONTRIBUTORS BE 31 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 37 * THE POSSIBILITY OF SUCH DAMAGE. 38 * 39 */ 40 41 42 #ifndef _EFICONTEXT_H_ 43 #define _EFICONTEXT_H_ 44 45 46 // 47 // IA-64 processor exception types 48 // 49 #define EXCPT_ALT_DTLB 4 50 #define EXCPT_DNESTED_TLB 5 51 #define EXCPT_BREAKPOINT 11 52 #define EXCPT_EXTERNAL_INTERRUPT 12 53 #define EXCPT_GEN_EXCEPT 24 54 #define EXCPT_NAT_CONSUMPTION 26 55 #define EXCPT_DEBUG_EXCEPT 29 56 #define EXCPT_UNALIGNED_ACCESS 30 57 #define EXCPT_FP_FAULT 32 58 #define EXCPT_FP_TRAP 33 59 #define EXCPT_TAKEN_BRANCH 35 60 #define EXCPT_SINGLE_STEP 36 61 62 // 63 // IA-64 processor context definition - must be 512 byte aligned!!! 64 // 65 typedef 66 struct { 67 UINT64 reserved; // necessary to preserve alignment for the correct bits in UNAT and to insure F2 is 16 byte aligned... 68 69 UINT64 r1; 70 UINT64 r2; 71 UINT64 r3; 72 UINT64 r4; 73 UINT64 r5; 74 UINT64 r6; 75 UINT64 r7; 76 UINT64 r8; 77 UINT64 r9; 78 UINT64 r10; 79 UINT64 r11; 80 UINT64 r12; 81 UINT64 r13; 82 UINT64 r14; 83 UINT64 r15; 84 UINT64 r16; 85 UINT64 r17; 86 UINT64 r18; 87 UINT64 r19; 88 UINT64 r20; 89 UINT64 r21; 90 UINT64 r22; 91 UINT64 r23; 92 UINT64 r24; 93 UINT64 r25; 94 UINT64 r26; 95 UINT64 r27; 96 UINT64 r28; 97 UINT64 r29; 98 UINT64 r30; 99 UINT64 r31; 100 101 UINT64 f2[2]; 102 UINT64 f3[2]; 103 UINT64 f4[2]; 104 UINT64 f5[2]; 105 UINT64 f6[2]; 106 UINT64 f7[2]; 107 UINT64 f8[2]; 108 UINT64 f9[2]; 109 UINT64 f10[2]; 110 UINT64 f11[2]; 111 UINT64 f12[2]; 112 UINT64 f13[2]; 113 UINT64 f14[2]; 114 UINT64 f15[2]; 115 UINT64 f16[2]; 116 UINT64 f17[2]; 117 UINT64 f18[2]; 118 UINT64 f19[2]; 119 UINT64 f20[2]; 120 UINT64 f21[2]; 121 UINT64 f22[2]; 122 UINT64 f23[2]; 123 UINT64 f24[2]; 124 UINT64 f25[2]; 125 UINT64 f26[2]; 126 UINT64 f27[2]; 127 UINT64 f28[2]; 128 UINT64 f29[2]; 129 UINT64 f30[2]; 130 UINT64 f31[2]; 131 132 UINT64 pr; 133 134 UINT64 b0; 135 UINT64 b1; 136 UINT64 b2; 137 UINT64 b3; 138 UINT64 b4; 139 UINT64 b5; 140 UINT64 b6; 141 UINT64 b7; 142 143 // application registers 144 UINT64 ar_rsc; 145 UINT64 ar_bsp; 146 UINT64 ar_bspstore; 147 UINT64 ar_rnat; 148 149 UINT64 ar_fcr; 150 151 UINT64 ar_eflag; 152 UINT64 ar_csd; 153 UINT64 ar_ssd; 154 UINT64 ar_cflg; 155 UINT64 ar_fsr; 156 UINT64 ar_fir; 157 UINT64 ar_fdr; 158 159 UINT64 ar_ccv; 160 161 UINT64 ar_unat; 162 163 UINT64 ar_fpsr; 164 165 UINT64 ar_pfs; 166 UINT64 ar_lc; 167 UINT64 ar_ec; 168 169 // control registers 170 UINT64 cr_dcr; 171 UINT64 cr_itm; 172 UINT64 cr_iva; 173 UINT64 cr_pta; 174 UINT64 cr_ipsr; 175 UINT64 cr_isr; 176 UINT64 cr_iip; 177 UINT64 cr_ifa; 178 UINT64 cr_itir; 179 UINT64 cr_iipa; 180 UINT64 cr_ifs; 181 UINT64 cr_iim; 182 UINT64 cr_iha; 183 184 // debug registers 185 UINT64 dbr0; 186 UINT64 dbr1; 187 UINT64 dbr2; 188 UINT64 dbr3; 189 UINT64 dbr4; 190 UINT64 dbr5; 191 UINT64 dbr6; 192 UINT64 dbr7; 193 194 UINT64 ibr0; 195 UINT64 ibr1; 196 UINT64 ibr2; 197 UINT64 ibr3; 198 UINT64 ibr4; 199 UINT64 ibr5; 200 UINT64 ibr6; 201 UINT64 ibr7; 202 203 // virtual registers 204 UINT64 int_nat; // nat bits for R1-R31 205 206 } SYSTEM_CONTEXT; 207 208 #endif /* _EFI_CONTEXT_H_ */ 209
