1 /* 2 * 3 * modified 4 * by Steve M. Gehlbach <steve (at) kesa.com> 5 * 6 * Originally from linux/drivers/video/vga16.c by 7 * Ben Pfaff <pfaffben (at) debian.org> and Petr Vandrovec <VANDROVE (at) vc.cvut.cz> 8 * Copyright 1999 Ben Pfaff <pfaffben (at) debian.org> and Petr Vandrovec <VANDROVE (at) vc.cvut.cz> 9 * Based on VGA info at http://www.goodnet.com/~tinara/FreeVGA/home.htm 10 * Based on VESA framebuffer (c) 1998 Gerd Knorr <kraxel (at) goldbach.in-berlin.de> 11 * 12 */ 13 14 #ifndef VGA_H_INCL 15 #define VGA_H_INCL 1 16 17 //#include <cpu/p5/io.h> 18 19 #define u8 unsigned char 20 #define u16 unsigned short 21 #define u32 unsigned int 22 #define __u32 u32 23 24 #define VERROR -1 25 #define CHAR_HEIGHT 16 26 #define LINES 25 27 #define COLS 80 28 29 // macros for writing to vga regs 30 #define write_crtc(data,addr) outb(addr,CRT_IC); outb(data,CRT_DC) 31 #define write_att(data,addr) inb(IS1_RC); inb(0x80); outb(addr,ATT_IW); inb(0x80); outb(data,ATT_IW); inb(0x80) 32 #define write_seq(data,addr) outb(addr,SEQ_I); outb(data,SEQ_D) 33 #define write_gra(data,addr) outb(addr,GRA_I); outb(data,GRA_D) 34 u8 read_seq_b(u16 addr); 35 u8 read_gra_b(u16 addr); 36 u8 read_crtc_b(u16 addr); 37 u8 read_att_b(u16 addr); 38 39 40 #ifdef VGA_HARDWARE_FIXUP 41 void vga_hardware_fixup(void); 42 #else 43 #define vga_hardware_fixup() do{} while(0) 44 #endif 45 46 #define SYNC_HOR_HIGH_ACT 1 /* horizontal sync high active */ 47 #define SYNC_VERT_HIGH_ACT 2 /* vertical sync high active */ 48 #define SYNC_EXT 4 /* external sync */ 49 #define SYNC_COMP_HIGH_ACT 8 /* composite sync high active */ 50 #define SYNC_BROADCAST 16 /* broadcast video timings */ 51 /* vtotal = 144d/288n/576i => PAL */ 52 /* vtotal = 121d/242n/484i => NTSC */ 53 54 #define SYNC_ON_GREEN 32 /* sync on green */ 55 56 #define VMODE_NONINTERLACED 0 /* non interlaced */ 57 #define VMODE_INTERLACED 1 /* interlaced */ 58 #define VMODE_DOUBLE 2 /* double scan */ 59 #define VMODE_MASK 255 60 61 #define VMODE_YWRAP 256 /* ywrap instead of panning */ 62 #define VMODE_SMOOTH_XPAN 512 /* smooth xpan possible (internally used) */ 63 #define VMODE_CONUPDATE 512 /* don't update x/yoffset */ 64 65 /* VGA data register ports */ 66 #define CRT_DC 0x3D5 /* CRT Controller Data Register - color emulation */ 67 #define CRT_DM 0x3B5 /* CRT Controller Data Register - mono emulation */ 68 #define ATT_R 0x3C1 /* Attribute Controller Data Read Register */ 69 #define GRA_D 0x3CF /* Graphics Controller Data Register */ 70 #define SEQ_D 0x3C5 /* Sequencer Data Register */ 71 72 #define MIS_R 0x3CC // Misc Output Read Register 73 #define MIS_W 0x3C2 // Misc Output Write Register 74 75 #define IS1_RC 0x3DA /* Input Status Register 1 - color emulation */ 76 #define IS1_RM 0x3BA /* Input Status Register 1 - mono emulation */ 77 #define PEL_D 0x3C9 /* PEL Data Register */ 78 #define PEL_MSK 0x3C6 /* PEL mask register */ 79 80 /* EGA-specific registers */ 81 #define GRA_E0 0x3CC /* Graphics enable processor 0 */ 82 #define GRA_E1 0x3CA /* Graphics enable processor 1 */ 83 84 85 /* VGA index register ports */ 86 #define CRT_IC 0x3D4 /* CRT Controller Index - color emulation */ 87 #define CRT_IM 0x3B4 /* CRT Controller Index - mono emulation */ 88 #define ATT_IW 0x3C0 /* Attribute Controller Index & Data Write Register */ 89 #define GRA_I 0x3CE /* Graphics Controller Index */ 90 #define SEQ_I 0x3C4 /* Sequencer Index */ 91 #define PEL_IW 0x3C8 /* PEL Write Index */ 92 #define PEL_IR 0x3C7 /* PEL Read Index */ 93 94 /* standard VGA indexes max counts */ 95 #define CRTC_C 25 /* 25 CRT Controller Registers sequentially set*/ 96 // the remainder are not in the par array 97 #define ATT_C 21 /* 21 Attribute Controller Registers */ 98 #define GRA_C 9 /* 9 Graphics Controller Registers */ 99 #define SEQ_C 5 /* 5 Sequencer Registers */ 100 #define MIS_C 1 /* 1 Misc Output Register */ 101 102 #define CRTC_H_TOTAL 0 103 #define CRTC_H_DISP 1 104 #define CRTC_H_BLANK_START 2 105 #define CRTC_H_BLANK_END 3 106 #define CRTC_H_SYNC_START 4 107 #define CRTC_H_SYNC_END 5 108 #define CRTC_V_TOTAL 6 109 #define CRTC_OVERFLOW 7 110 #define CRTC_PRESET_ROW 8 111 #define CRTC_MAX_SCAN 9 112 #define CRTC_CURSOR_START 0x0A 113 #define CRTC_CURSOR_END 0x0B 114 #define CRTC_START_HI 0x0C 115 #define CRTC_START_LO 0x0D 116 #define CRTC_CURSOR_HI 0x0E 117 #define CRTC_CURSOR_LO 0x0F 118 #define CRTC_V_SYNC_START 0x10 119 #define CRTC_V_SYNC_END 0x11 120 #define CRTC_V_DISP_END 0x12 121 #define CRTC_OFFSET 0x13 122 #define CRTC_UNDERLINE 0x14 123 #define CRTC_V_BLANK_START 0x15 124 #define CRTC_V_BLANK_END 0x16 125 #define CRTC_MODE 0x17 126 #define CRTC_LINE_COMPARE 0x18 127 128 #define ATC_MODE 0x10 129 #define ATC_OVERSCAN 0x11 130 #define ATC_PLANE_ENABLE 0x12 131 #define ATC_PEL 0x13 132 #define ATC_COLOR_PAGE 0x14 133 134 #define SEQ_CLOCK_MODE 0x01 135 #define SEQ_PLANE_WRITE 0x02 136 #define SEQ_CHARACTER_MAP 0x03 137 #define SEQ_MEMORY_MODE 0x04 138 139 #define GDC_SR_VALUE 0x00 140 #define GDC_SR_ENABLE 0x01 141 #define GDC_COMPARE_VALUE 0x02 142 #define GDC_DATA_ROTATE 0x03 143 #define GDC_PLANE_READ 0x04 144 #define GDC_MODE 0x05 145 #define GDC_MISC 0x06 146 #define GDC_COMPARE_MASK 0x07 147 #define GDC_BIT_MASK 0x08 148 149 // text attributes 150 #define VGA_ATTR_CLR_RED 0x4 151 #define VGA_ATTR_CLR_GRN 0x2 152 #define VGA_ATTR_CLR_BLU 0x1 153 #define VGA_ATTR_CLR_YEL (VGA_ATTR_CLR_RED | VGA_ATTR_CLR_GRN) 154 #define VGA_ATTR_CLR_CYN (VGA_ATTR_CLR_GRN | VGA_ATTR_CLR_BLU) 155 #define VGA_ATTR_CLR_MAG (VGA_ATTR_CLR_BLU | VGA_ATTR_CLR_RED) 156 #define VGA_ATTR_CLR_BLK 0 157 #define VGA_ATTR_CLR_WHT (VGA_ATTR_CLR_RED | VGA_ATTR_CLR_GRN | VGA_ATTR_CLR_BLU) 158 #define VGA_ATTR_BNK 0x80 159 #define VGA_ATTR_ITN 0x08 160 161 /* 162 * vga register parameters 163 * these are copied to the 164 * registers. 165 * 166 */ 167 struct vga_par { 168 u8 crtc[CRTC_C]; 169 u8 atc[ATT_C]; 170 u8 gdc[GRA_C]; 171 u8 seq[SEQ_C]; 172 u8 misc; // the misc register, MIS_W 173 u8 vss; 174 }; 175 176 177 /* Interpretation of offset for color fields: All offsets are from the right, 178 * inside a "pixel" value, which is exactly 'bits_per_pixel' wide (means: you 179 * can use the offset as right argument to <<). A pixel afterwards is a bit 180 * stream and is written to video memory as that unmodified. This implies 181 * big-endian byte order if bits_per_pixel is greater than 8. 182 */ 183 struct fb_bitfield { 184 __u32 offset; /* beginning of bitfield */ 185 __u32 length; /* length of bitfield */ 186 __u32 msb_right; /* != 0 : Most significant bit is */ 187 /* right */ 188 }; 189 190 struct screeninfo { 191 __u32 xres; /* visible resolution */ 192 __u32 yres; 193 __u32 xres_virtual; /* virtual resolution */ 194 __u32 yres_virtual; 195 __u32 xoffset; /* offset from virtual to visible */ 196 __u32 yoffset; /* resolution */ 197 198 __u32 bits_per_pixel; /* guess what */ 199 __u32 grayscale; /* != 0 Graylevels instead of colors */ 200 201 struct fb_bitfield red; /* bitfield in fb mem if true color, */ 202 struct fb_bitfield green; /* else only length is significant */ 203 struct fb_bitfield blue; 204 struct fb_bitfield transp; /* transparency */ 205 206 __u32 nonstd; /* != 0 Non standard pixel format */ 207 208 __u32 activate; /* see FB_ACTIVATE_* */ 209 210 __u32 height; /* height of picture in mm */ 211 __u32 width; /* width of picture in mm */ 212 213 __u32 accel_flags; /* acceleration flags (hints) */ 214 215 /* Timing: All values in pixclocks, except pixclock (of course) */ 216 __u32 pixclock; /* pixel clock in ps (pico seconds) */ 217 __u32 left_margin; /* time from sync to picture */ 218 __u32 right_margin; /* time from picture to sync */ 219 __u32 upper_margin; /* time from sync to picture */ 220 __u32 lower_margin; 221 __u32 hsync_len; /* length of horizontal sync */ 222 __u32 vsync_len; /* length of vertical sync */ 223 __u32 sync; /* sync polarity */ 224 __u32 vmode; /* interlaced etc */ 225 __u32 reserved[6]; /* Reserved for future compatibility */ 226 }; 227 228 #endif 229
