1 #ifdef ALLMULTI 2 #error multicast support is not yet implemented 3 #endif 4 /* 5 DAVICOM DM9009/DM9102/DM9102A Etherboot Driver V1.00 6 7 This driver was ported from Marty Connor's Tulip Etherboot driver. 8 Thanks Marty Connor (mdc (at) etherboot.org) 9 10 This davicom etherboot driver supports DM9009/DM9102/DM9102A/ 11 DM9102A+DM9801/DM9102A+DM9802 NICs. 12 13 This software may be used and distributed according to the terms 14 of the GNU Public License, incorporated herein by reference. 15 16 */ 17 18 FILE_LICENCE ( GPL_ANY ); 19 20 /*********************************************************************/ 21 /* Revision History */ 22 /*********************************************************************/ 23 24 /* 25 19 OCT 2000 Sten 1.00 26 Different half and full duplex mode 27 Do the different programming for DM9801/DM9802 28 29 12 OCT 2000 Sten 0.90 30 This driver was ported from tulip driver and it 31 has the following difference. 32 Changed symbol tulip/TULIP to davicom/DAVICOM 33 Deleted some code that did not use in this driver. 34 Used chain-strcture to replace ring structure 35 for both TX/RX descriptor. 36 Allocated two tx descriptor. 37 According current media mode to set operating 38 register(CR6) 39 */ 40 41 42 /*********************************************************************/ 44 /* Declarations */ 45 /*********************************************************************/ 46 47 #include "etherboot.h" 48 #include "nic.h" 49 #include <gpxe/pci.h> 50 #include <gpxe/ethernet.h> 51 52 #undef DAVICOM_DEBUG 53 #undef DAVICOM_DEBUG_WHERE 54 55 #define TX_TIME_OUT 2*TICKS_PER_SEC 56 57 /* Register offsets for davicom device */ 58 enum davicom_offsets { 59 CSR0=0, CSR1=0x08, CSR2=0x10, CSR3=0x18, CSR4=0x20, CSR5=0x28, 60 CSR6=0x30, CSR7=0x38, CSR8=0x40, CSR9=0x48, CSR10=0x50, CSR11=0x58, 61 CSR12=0x60, CSR13=0x68, CSR14=0x70, CSR15=0x78, CSR16=0x80, CSR20=0xA0 62 }; 63 64 /* EEPROM Address width definitions */ 65 #define EEPROM_ADDRLEN 6 66 #define EEPROM_SIZE 32 /* 1 << EEPROM_ADDRLEN */ 67 /* Used to be 128, but we only need to read enough to get the MAC 68 address at bytes 20..25 */ 69 70 /* Data Read from the EEPROM */ 71 static unsigned char ee_data[EEPROM_SIZE]; 72 73 /* The EEPROM commands include the alway-set leading bit. */ 74 #define EE_WRITE_CMD (5 << addr_len) 75 #define EE_READ_CMD (6 << addr_len) 76 #define EE_ERASE_CMD (7 << addr_len) 77 78 /* EEPROM_Ctrl bits. */ 79 #define EE_SHIFT_CLK 0x02 /* EEPROM shift clock. */ 80 #define EE_CS 0x01 /* EEPROM chip select. */ 81 #define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */ 82 #define EE_WRITE_0 0x01 83 #define EE_WRITE_1 0x05 84 #define EE_DATA_READ 0x08 /* EEPROM chip data out. */ 85 #define EE_ENB (0x4800 | EE_CS) 86 87 /* Sten 10/11 for phyxcer */ 88 #define PHY_DATA_0 0x0 89 #define PHY_DATA_1 0x20000 90 #define MDCLKH 0x10000 91 92 /* Delay between EEPROM clock transitions. Even at 33Mhz current PCI 93 implementations don't overrun the EEPROM clock. We add a bus 94 turn-around to insure that this remains true. */ 95 #define eeprom_delay() inl(ee_addr) 96 97 /* helpful macro if on a big_endian machine for changing byte order. 98 not strictly needed on Intel 99 Already defined in Etherboot includes 100 #define le16_to_cpu(val) (val) 101 */ 102 103 /* transmit and receive descriptor format */ 104 struct txdesc { 105 volatile unsigned long status; /* owner, status */ 106 unsigned long buf1sz:11, /* size of buffer 1 */ 107 buf2sz:11, /* size of buffer 2 */ 108 control:10; /* control bits */ 109 const unsigned char *buf1addr; /* buffer 1 address */ 110 const unsigned char *buf2addr; /* buffer 2 address */ 111 }; 112 113 struct rxdesc { 114 volatile unsigned long status; /* owner, status */ 115 unsigned long buf1sz:11, /* size of buffer 1 */ 116 buf2sz:11, /* size of buffer 2 */ 117 control:10; /* control bits */ 118 unsigned char *buf1addr; /* buffer 1 address */ 119 unsigned char *buf2addr; /* buffer 2 address */ 120 }; 121 122 /* Size of transmit and receive buffers */ 123 #define BUFLEN 1536 124 125 /*********************************************************************/ 126 /* Global Storage */ 127 /*********************************************************************/ 128 129 static struct nic_operations davicom_operations; 130 131 /* PCI Bus parameters */ 132 static unsigned short vendor, dev_id; 133 static unsigned long ioaddr; 134 135 /* Note: transmit and receive buffers must be longword aligned and 136 longword divisable */ 137 138 /* transmit descriptor and buffer */ 139 #define NTXD 2 140 #define NRXD 4 141 struct { 142 struct txdesc txd[NTXD] __attribute__ ((aligned(4))); 143 unsigned char txb[BUFLEN] __attribute__ ((aligned(4))); 144 struct rxdesc rxd[NRXD] __attribute__ ((aligned(4))); 145 unsigned char rxb[NRXD * BUFLEN] __attribute__ ((aligned(4))); 146 } davicom_bufs __shared; 147 #define txd davicom_bufs.txd 148 #define txb davicom_bufs.txb 149 #define rxd davicom_bufs.rxd 150 #define rxb davicom_bufs.rxb 151 static int rxd_tail; 152 static int TxPtr; 153 154 155 /*********************************************************************/ 157 /* Function Prototypes */ 158 /*********************************************************************/ 159 static void whereami(const char *str); 160 static int read_eeprom(unsigned long ioaddr, int location, int addr_len); 161 static int davicom_probe(struct nic *nic,struct pci_device *pci); 162 static void davicom_init_chain(struct nic *nic); /* Sten 10/9 */ 163 static void davicom_reset(struct nic *nic); 164 static void davicom_transmit(struct nic *nic, const char *d, unsigned int t, 165 unsigned int s, const char *p); 166 static int davicom_poll(struct nic *nic, int retrieve); 167 static void davicom_disable(struct nic *nic); 168 #ifdef DAVICOM_DEBUG 169 static void davicom_more(void); 170 #endif /* DAVICOM_DEBUG */ 171 static void davicom_wait(unsigned int nticks); 172 static int phy_read(int); 173 static void phy_write(int, u16); 174 static void phy_write_1bit(u32, u32); 175 static int phy_read_1bit(u32); 176 static void davicom_media_chk(struct nic *); 177 178 179 /*********************************************************************/ 181 /* Utility Routines */ 182 /*********************************************************************/ 183 static inline void whereami(const char *str) 184 { 185 printf("%s\n", str); 186 /* sleep(2); */ 187 } 188 189 #ifdef DAVICOM_DEBUG 190 static void davicom_more() 191 { 192 printf("\n\n-- more --"); 193 while (!iskey()) 194 /* wait */; 195 getchar(); 196 printf("\n\n"); 197 } 198 #endif /* DAVICOM_DEBUG */ 199 200 static void davicom_wait(unsigned int nticks) 201 { 202 unsigned int to = currticks() + nticks; 203 while (currticks() < to) 204 /* wait */ ; 205 } 206 207 208 /*********************************************************************/ 210 /* For DAVICOM phyxcer register by MII interface */ 211 /*********************************************************************/ 212 /* 213 Read a word data from phy register 214 */ 215 static int phy_read(int location) 216 { 217 int i, phy_addr=1; 218 u16 phy_data; 219 u32 io_dcr9; 220 221 whereami("phy_read\n"); 222 223 io_dcr9 = ioaddr + CSR9; 224 225 /* Send 33 synchronization clock to Phy controller */ 226 for (i=0; i<34; i++) 227 phy_write_1bit(io_dcr9, PHY_DATA_1); 228 229 /* Send start command(01) to Phy */ 230 phy_write_1bit(io_dcr9, PHY_DATA_0); 231 phy_write_1bit(io_dcr9, PHY_DATA_1); 232 233 /* Send read command(10) to Phy */ 234 phy_write_1bit(io_dcr9, PHY_DATA_1); 235 phy_write_1bit(io_dcr9, PHY_DATA_0); 236 237 /* Send Phy addres */ 238 for (i=0x10; i>0; i=i>>1) 239 phy_write_1bit(io_dcr9, phy_addr&i ? PHY_DATA_1: PHY_DATA_0); 240 241 /* Send register addres */ 242 for (i=0x10; i>0; i=i>>1) 243 phy_write_1bit(io_dcr9, location&i ? PHY_DATA_1: PHY_DATA_0); 244 245 /* Skip transition state */ 246 phy_read_1bit(io_dcr9); 247 248 /* read 16bit data */ 249 for (phy_data=0, i=0; i<16; i++) { 250 phy_data<<=1; 251 phy_data|=phy_read_1bit(io_dcr9); 252 } 253 254 return phy_data; 255 } 256 257 /* 258 Write a word to Phy register 259 */ 260 static void phy_write(int location, u16 phy_data) 261 { 262 u16 i, phy_addr=1; 263 u32 io_dcr9; 264 265 whereami("phy_write\n"); 266 267 io_dcr9 = ioaddr + CSR9; 268 269 /* Send 33 synchronization clock to Phy controller */ 270 for (i=0; i<34; i++) 271 phy_write_1bit(io_dcr9, PHY_DATA_1); 272 273 /* Send start command(01) to Phy */ 274 phy_write_1bit(io_dcr9, PHY_DATA_0); 275 phy_write_1bit(io_dcr9, PHY_DATA_1); 276 277 /* Send write command(01) to Phy */ 278 phy_write_1bit(io_dcr9, PHY_DATA_0); 279 phy_write_1bit(io_dcr9, PHY_DATA_1); 280 281 /* Send Phy addres */ 282 for (i=0x10; i>0; i=i>>1) 283 phy_write_1bit(io_dcr9, phy_addr&i ? PHY_DATA_1: PHY_DATA_0); 284 285 /* Send register addres */ 286 for (i=0x10; i>0; i=i>>1) 287 phy_write_1bit(io_dcr9, location&i ? PHY_DATA_1: PHY_DATA_0); 288 289 /* written trasnition */ 290 phy_write_1bit(io_dcr9, PHY_DATA_1); 291 phy_write_1bit(io_dcr9, PHY_DATA_0); 292 293 /* Write a word data to PHY controller */ 294 for (i=0x8000; i>0; i>>=1) 295 phy_write_1bit(io_dcr9, phy_data&i ? PHY_DATA_1: PHY_DATA_0); 296 } 297 298 /* 299 Write one bit data to Phy Controller 300 */ 301 static void phy_write_1bit(u32 ee_addr, u32 phy_data) 302 { 303 whereami("phy_write_1bit\n"); 304 outl(phy_data, ee_addr); /* MII Clock Low */ 305 eeprom_delay(); 306 outl(phy_data|MDCLKH, ee_addr); /* MII Clock High */ 307 eeprom_delay(); 308 outl(phy_data, ee_addr); /* MII Clock Low */ 309 eeprom_delay(); 310 } 311 312 /* 313 Read one bit phy data from PHY controller 314 */ 315 static int phy_read_1bit(u32 ee_addr) 316 { 317 int phy_data; 318 319 whereami("phy_read_1bit\n"); 320 321 outl(0x50000, ee_addr); 322 eeprom_delay(); 323 324 phy_data=(inl(ee_addr)>>19) & 0x1; 325 326 outl(0x40000, ee_addr); 327 eeprom_delay(); 328 329 return phy_data; 330 } 331 332 /* 333 DM9801/DM9802 present check and program 334 */ 335 static void HPNA_process(void) 336 { 337 338 if ( (phy_read(3) & 0xfff0) == 0xb900 ) { 339 if ( phy_read(31) == 0x4404 ) { 340 /* DM9801 present */ 341 if (phy_read(3) == 0xb901) 342 phy_write(16, 0x5); /* DM9801 E4 */ 343 else 344 phy_write(16, 0x1005); /* DM9801 E3 and others */ 345 phy_write(25, ((phy_read(24) + 3) & 0xff) | 0xf000); 346 } else { 347 /* DM9802 present */ 348 phy_write(16, 0x5); 349 phy_write(25, (phy_read(25) & 0xff00) + 2); 350 } 351 } 352 } 353 354 /* 355 Sense media mode and set CR6 356 */ 357 static void davicom_media_chk(struct nic * nic __unused) 358 { 359 unsigned long to, csr6; 360 361 csr6 = 0x00200000; /* SF */ 362 outl(csr6, ioaddr + CSR6); 363 364 #define PCI_DEVICE_ID_DM9009 0x9009 365 if (vendor == PCI_VENDOR_ID_DAVICOM && dev_id == PCI_DEVICE_ID_DM9009) { 366 /* Set to 10BaseT mode for DM9009 */ 367 phy_write(0, 0); 368 } else { 369 /* For DM9102/DM9102A */ 370 to = currticks() + 2 * TICKS_PER_SEC; 371 while ( ((phy_read(1) & 0x24)!=0x24) && (currticks() < to)) 372 /* wait */ ; 373 374 if ( (phy_read(1) & 0x24) == 0x24 ) { 375 if (phy_read(17) & 0xa000) 376 csr6 |= 0x00000200; /* Full Duplex mode */ 377 } else 378 csr6 |= 0x00040000; /* Select DM9801/DM9802 when Ethernet link failed */ 379 } 380 381 /* set the chip's operating mode */ 382 outl(csr6, ioaddr + CSR6); 383 384 /* DM9801/DM9802 present check & program */ 385 if (csr6 & 0x40000) 386 HPNA_process(); 387 } 388 389 390 /*********************************************************************/ 392 /* EEPROM Reading Code */ 393 /*********************************************************************/ 394 /* EEPROM routines adapted from the Linux Tulip Code */ 395 /* Reading a serial EEPROM is a "bit" grungy, but we work our way 396 through:->. 397 */ 398 static int read_eeprom(unsigned long ioaddr, int location, int addr_len) 399 { 400 int i; 401 unsigned short retval = 0; 402 long ee_addr = ioaddr + CSR9; 403 int read_cmd = location | EE_READ_CMD; 404 405 whereami("read_eeprom\n"); 406 407 outl(EE_ENB & ~EE_CS, ee_addr); 408 outl(EE_ENB, ee_addr); 409 410 /* Shift the read command bits out. */ 411 for (i = 4 + addr_len; i >= 0; i--) { 412 short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0; 413 outl(EE_ENB | dataval, ee_addr); 414 eeprom_delay(); 415 outl(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr); 416 eeprom_delay(); 417 } 418 outl(EE_ENB, ee_addr); 419 420 for (i = 16; i > 0; i--) { 421 outl(EE_ENB | EE_SHIFT_CLK, ee_addr); 422 eeprom_delay(); 423 retval = (retval << 1) | ((inl(ee_addr) & EE_DATA_READ) ? 1 : 0); 424 outl(EE_ENB, ee_addr); 425 eeprom_delay(); 426 } 427 428 /* Terminate the EEPROM access. */ 429 outl(EE_ENB & ~EE_CS, ee_addr); 430 return retval; 431 } 432 433 /*********************************************************************/ 435 /* davicom_init_chain - setup the tx and rx descriptors */ 436 /* Sten 10/9 */ 437 /*********************************************************************/ 438 static void davicom_init_chain(struct nic *nic) 439 { 440 int i; 441 442 /* setup the transmit descriptor */ 443 /* Sten: Set 2 TX descriptor but use one TX buffer because 444 it transmit a packet and wait complete every time. */ 445 for (i=0; i<NTXD; i++) { 446 txd[i].buf1addr = (void *)virt_to_bus(&txb[0]); /* Used same TX buffer */ 447 txd[i].buf2addr = (void *)virt_to_bus(&txd[i+1]); /* Point to Next TX desc */ 448 txd[i].buf1sz = 0; 449 txd[i].buf2sz = 0; 450 txd[i].control = 0x184; /* Begin/End/Chain */ 451 txd[i].status = 0x00000000; /* give ownership to Host */ 452 } 453 454 /* construct perfect filter frame with mac address as first match 455 and broadcast address for all others */ 456 for (i=0; i<192; i++) txb[i] = 0xFF; 457 txb[0] = nic->node_addr[0]; 458 txb[1] = nic->node_addr[1]; 459 txb[4] = nic->node_addr[2]; 460 txb[5] = nic->node_addr[3]; 461 txb[8] = nic->node_addr[4]; 462 txb[9] = nic->node_addr[5]; 463 464 /* setup receive descriptor */ 465 for (i=0; i<NRXD; i++) { 466 rxd[i].buf1addr = (void *)virt_to_bus(&rxb[i * BUFLEN]); 467 rxd[i].buf2addr = (void *)virt_to_bus(&rxd[i+1]); /* Point to Next RX desc */ 468 rxd[i].buf1sz = BUFLEN; 469 rxd[i].buf2sz = 0; /* not used */ 470 rxd[i].control = 0x4; /* Chain Structure */ 471 rxd[i].status = 0x80000000; /* give ownership to device */ 472 } 473 474 /* Chain the last descriptor to first */ 475 txd[NTXD - 1].buf2addr = (void *)virt_to_bus(&txd[0]); 476 rxd[NRXD - 1].buf2addr = (void *)virt_to_bus(&rxd[0]); 477 TxPtr = 0; 478 rxd_tail = 0; 479 } 480 481 482 /*********************************************************************/ 484 /* davicom_reset - Reset adapter */ 485 /*********************************************************************/ 486 static void davicom_reset(struct nic *nic) 487 { 488 unsigned long to; 489 490 whereami("davicom_reset\n"); 491 492 /* Stop Tx and RX */ 493 outl(inl(ioaddr + CSR6) & ~0x00002002, ioaddr + CSR6); 494 495 /* Reset the chip, holding bit 0 set at least 50 PCI cycles. */ 496 outl(0x00000001, ioaddr + CSR0); 497 498 davicom_wait(TICKS_PER_SEC); 499 500 /* TX/RX descriptor burst */ 501 outl(0x0C00000, ioaddr + CSR0); /* Sten 10/9 */ 502 503 /* set up transmit and receive descriptors */ 504 davicom_init_chain(nic); /* Sten 10/9 */ 505 506 /* Point to receive descriptor */ 507 outl(virt_to_bus(&rxd[0]), ioaddr + CSR3); 508 outl(virt_to_bus(&txd[0]), ioaddr + CSR4); /* Sten 10/9 */ 509 510 /* According phyxcer media mode to set CR6, 511 DM9102/A phyxcer can auto-detect media mode */ 512 davicom_media_chk(nic); 513 514 /* Prepare Setup Frame Sten 10/9 */ 515 txd[TxPtr].buf1sz = 192; 516 txd[TxPtr].control = 0x024; /* SF/CE */ 517 txd[TxPtr].status = 0x80000000; /* Give ownership to device */ 518 519 /* Start Tx */ 520 outl(inl(ioaddr + CSR6) | 0x00002000, ioaddr + CSR6); 521 /* immediate transmit demand */ 522 outl(0, ioaddr + CSR1); 523 524 to = currticks() + TX_TIME_OUT; 525 while ((txd[TxPtr].status & 0x80000000) && (currticks() < to)) /* Sten 10/9 */ 526 /* wait */ ; 527 528 if (currticks() >= to) { 529 printf ("TX Setup Timeout!\n"); 530 } 531 /* Point to next TX descriptor */ 532 TxPtr = (++TxPtr >= NTXD) ? 0:TxPtr; /* Sten 10/9 */ 533 534 #ifdef DAVICOM_DEBUG 535 printf("txd.status = %X\n", txd.status); 536 printf("ticks = %d\n", currticks() - (to - TX_TIME_OUT)); 537 davicom_more(); 538 #endif 539 540 /* enable RX */ 541 outl(inl(ioaddr + CSR6) | 0x00000002, ioaddr + CSR6); 542 /* immediate poll demand */ 543 outl(0, ioaddr + CSR2); 544 } 545 546 547 /*********************************************************************/ 549 /* eth_transmit - Transmit a frame */ 550 /*********************************************************************/ 551 static void davicom_transmit(struct nic *nic, const char *d, unsigned int t, 552 unsigned int s, const char *p) 553 { 554 unsigned long to; 555 556 whereami("davicom_transmit\n"); 557 558 /* Stop Tx */ 559 /* outl(inl(ioaddr + CSR6) & ~0x00002000, ioaddr + CSR6); */ 560 561 /* setup ethernet header */ 562 memcpy(&txb[0], d, ETH_ALEN); /* DA 6byte */ 563 memcpy(&txb[ETH_ALEN], nic->node_addr, ETH_ALEN); /* SA 6byte*/ 564 txb[ETH_ALEN*2] = (t >> 8) & 0xFF; /* Frame type: 2byte */ 565 txb[ETH_ALEN*2+1] = t & 0xFF; 566 memcpy(&txb[ETH_HLEN], p, s); /* Frame data */ 567 568 /* setup the transmit descriptor */ 569 txd[TxPtr].buf1sz = ETH_HLEN+s; 570 txd[TxPtr].control = 0x00000184; /* LS+FS+CE */ 571 txd[TxPtr].status = 0x80000000; /* give ownership to device */ 572 573 /* immediate transmit demand */ 574 outl(0, ioaddr + CSR1); 575 576 to = currticks() + TX_TIME_OUT; 577 while ((txd[TxPtr].status & 0x80000000) && (currticks() < to)) 578 /* wait */ ; 579 580 if (currticks() >= to) { 581 printf ("TX Timeout!\n"); 582 } 583 584 /* Point to next TX descriptor */ 585 TxPtr = (++TxPtr >= NTXD) ? 0:TxPtr; /* Sten 10/9 */ 586 587 } 588 589 /*********************************************************************/ 591 /* eth_poll - Wait for a frame */ 592 /*********************************************************************/ 593 static int davicom_poll(struct nic *nic, int retrieve) 594 { 595 whereami("davicom_poll\n"); 596 597 if (rxd[rxd_tail].status & 0x80000000) 598 return 0; 599 600 if ( ! retrieve ) return 1; 601 602 whereami("davicom_poll got one\n"); 603 604 nic->packetlen = (rxd[rxd_tail].status & 0x3FFF0000) >> 16; 605 606 if( rxd[rxd_tail].status & 0x00008000){ 607 rxd[rxd_tail].status = 0x80000000; 608 rxd_tail++; 609 if (rxd_tail == NRXD) rxd_tail = 0; 610 return 0; 611 } 612 613 /* copy packet to working buffer */ 614 /* XXX - this copy could be avoided with a little more work 615 but for now we are content with it because the optimised 616 memcpy is quite fast */ 617 618 memcpy(nic->packet, rxb + rxd_tail * BUFLEN, nic->packetlen); 619 620 /* return the descriptor and buffer to receive ring */ 621 rxd[rxd_tail].status = 0x80000000; 622 rxd_tail++; 623 if (rxd_tail == NRXD) rxd_tail = 0; 624 625 return 1; 626 } 627 628 /*********************************************************************/ 630 /* eth_disable - Disable the interface */ 631 /*********************************************************************/ 632 static void davicom_disable ( struct nic *nic ) { 633 634 whereami("davicom_disable\n"); 635 636 davicom_reset(nic); 637 638 /* disable interrupts */ 639 outl(0x00000000, ioaddr + CSR7); 640 641 /* Stop the chip's Tx and Rx processes. */ 642 outl(inl(ioaddr + CSR6) & ~0x00002002, ioaddr + CSR6); 643 644 /* Clear the missed-packet counter. */ 645 inl(ioaddr + CSR8); 646 } 647 648 649 /*********************************************************************/ 651 /* eth_irq - enable, disable and force interrupts */ 652 /*********************************************************************/ 653 static void davicom_irq(struct nic *nic __unused, irq_action_t action __unused) 654 { 655 switch ( action ) { 656 case DISABLE : 657 break; 658 case ENABLE : 659 break; 660 case FORCE : 661 break; 662 } 663 } 664 665 666 /*********************************************************************/ 668 /* eth_probe - Look for an adapter */ 669 /*********************************************************************/ 670 static int davicom_probe ( struct nic *nic, struct pci_device *pci ) { 671 672 unsigned int i; 673 674 whereami("davicom_probe\n"); 675 676 if (pci->ioaddr == 0) 677 return 0; 678 679 vendor = pci->vendor; 680 dev_id = pci->device; 681 ioaddr = pci->ioaddr; 682 683 nic->ioaddr = pci->ioaddr; 684 nic->irqno = 0; 685 686 /* wakeup chip */ 687 pci_write_config_dword(pci, 0x40, 0x00000000); 688 689 /* Stop the chip's Tx and Rx processes. */ 690 outl(inl(ioaddr + CSR6) & ~0x00002002, ioaddr + CSR6); 691 692 /* Clear the missed-packet counter. */ 693 inl(ioaddr + CSR8); 694 695 /* Get MAC Address */ 696 /* read EEPROM data */ 697 for (i = 0; i < sizeof(ee_data)/2; i++) 698 ((unsigned short *)ee_data)[i] = 699 le16_to_cpu(read_eeprom(ioaddr, i, EEPROM_ADDRLEN)); 700 701 /* extract MAC address from EEPROM buffer */ 702 for (i=0; i<ETH_ALEN; i++) 703 nic->node_addr[i] = ee_data[20+i]; 704 705 DBG ( "Davicom %s at IOADDR %4.4lx\n", eth_ntoa ( nic->node_addr ), ioaddr ); 706 707 /* initialize device */ 708 davicom_reset(nic); 709 nic->nic_op = &davicom_operations; 710 return 1; 711 } 712 713 static struct nic_operations davicom_operations = { 714 .connect = dummy_connect, 715 .poll = davicom_poll, 716 .transmit = davicom_transmit, 717 .irq = davicom_irq, 718 719 }; 720 721 static struct pci_device_id davicom_nics[] = { 722 PCI_ROM(0x1282, 0x9100, "davicom9100", "Davicom 9100", 0), 723 PCI_ROM(0x1282, 0x9102, "davicom9102", "Davicom 9102", 0), 724 PCI_ROM(0x1282, 0x9009, "davicom9009", "Davicom 9009", 0), 725 PCI_ROM(0x1282, 0x9132, "davicom9132", "Davicom 9132", 0), /* Needs probably some fixing */ 726 }; 727 728 PCI_DRIVER ( davicom_driver, davicom_nics, PCI_NO_CLASS ); 729 730 DRIVER ( "DAVICOM", nic_driver, pci_driver, davicom_driver, 731 davicom_probe, davicom_disable ); 732 733 /* 734 * Local variables: 735 * c-basic-offset: 8 736 * c-indent-level: 8 737 * tab-width: 8 738 * End: 739 */ 740
