1 /* Copyright 2015 The TensorFlow Authors. All Rights Reserved. 2 3 Licensed under the Apache License, Version 2.0 (the "License"); 4 you may not use this file except in compliance with the License. 5 You may obtain a copy of the License at 6 7 http://www.apache.org/licenses/LICENSE-2.0 8 9 Unless required by applicable law or agreed to in writing, software 10 distributed under the License is distributed on an "AS IS" BASIS, 11 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 See the License for the specific language governing permissions and 13 limitations under the License. 14 ==============================================================================*/ 15 16 #if GOOGLE_CUDA 17 18 #define EIGEN_USE_GPU 19 20 #include "tensorflow/core/framework/register_types.h" 21 #include "tensorflow/core/kernels/matrix_set_diag_op.h" 22 #include "tensorflow/core/util/cuda_kernel_helper.h" 23 24 namespace tensorflow { 25 namespace functor { 26 27 typedef Eigen::GpuDevice GPUDevice; 28 29 template <typename Scalar> 30 __global__ void MatrixSetDiagKernel(const int num_threads, const int m, 31 const int n, const int minsize, 32 const Scalar* diag_ptr, 33 Scalar* output_ptr) { 34 CUDA_1D_KERNEL_LOOP(index, num_threads) { 35 const int batch = index / minsize; 36 const int col = index - batch * minsize; 37 const int out_index = batch * m * n + (n + 1) * col; 38 output_ptr[out_index] = diag_ptr[index]; 39 } 40 } 41 42 template <typename Scalar> 43 __global__ void MatrixCopyInputAndSetDiagKernel( 44 const int num_threads, const int m, const int n, const int minsize, 45 const Scalar* input_ptr, const Scalar* diag_ptr, Scalar* output_ptr) { 46 CUDA_1D_KERNEL_LOOP(index, num_threads) { 47 const int global_row = index / n; 48 const int col = index - global_row * n; 49 const int batch = global_row / m; 50 const int row = global_row - batch * m; 51 if (col == row) { 52 // Because col = index % n, and row = (index / n) % m, 53 // we know that col==row => col < minsize, so the following is safe: 54 output_ptr[index] = diag_ptr[batch * minsize + col]; 55 } else { 56 output_ptr[index] = input_ptr[index]; 57 } 58 } 59 } 60 61 template <typename Scalar> 62 struct MatrixSetDiag<GPUDevice, Scalar> { 63 static void Compute(OpKernelContext* context, const GPUDevice& device, 64 typename TTypes<Scalar, 3>::ConstTensor input, 65 typename TTypes<Scalar, 2>::ConstTensor diag, 66 typename TTypes<Scalar, 3>::Tensor output) { 67 const int batch_size = input.dimension(0); 68 const int m = input.dimension(1); 69 const int n = input.dimension(2); 70 const int minsize = std::min(m, n); 71 CHECK_EQ(diag.dimension(1), minsize); 72 if (batch_size == 0 || minsize == 0) return; 73 if (input.data() == output.data()) { 74 CudaLaunchConfig config = 75 GetCudaLaunchConfig(batch_size * minsize, device); 76 MatrixSetDiagKernel<Scalar> 77 <<<config.block_count, config.thread_per_block, 0, device.stream()>>>( 78 config.virtual_thread_count, m, n, minsize, diag.data(), 79 output.data()); 80 } else { 81 CudaLaunchConfig config = GetCudaLaunchConfig(batch_size * m * n, device); 82 MatrixCopyInputAndSetDiagKernel<Scalar> 83 <<<config.block_count, config.thread_per_block, 0, device.stream()>>>( 84 config.virtual_thread_count, m, n, minsize, input.data(), 85 diag.data(), output.data()); 86 } 87 } 88 }; 89 90 #define DEFINE_GPU_SPEC(T) template struct MatrixSetDiag<GPUDevice, T>; 91 92 TF_CALL_GPU_NUMBER_TYPES(DEFINE_GPU_SPEC); 93 TF_CALL_bool(DEFINE_GPU_SPEC); 94 TF_CALL_complex64(DEFINE_GPU_SPEC); 95 TF_CALL_complex128(DEFINE_GPU_SPEC); 96 97 } // namespace functor 98 } // namespace tensorflow 99 100 #endif // GOOGLE_CUDA 101
