1 // Copyright 2016, VIXL authors 2 // All rights reserved. 3 // 4 // Redistribution and use in source and binary forms, with or without 5 // modification, are permitted provided that the following conditions are met: 6 // 7 // * Redistributions of source code must retain the above copyright notice, 8 // this list of conditions and the following disclaimer. 9 // * Redistributions in binary form must reproduce the above copyright notice, 10 // this list of conditions and the following disclaimer in the documentation 11 // and/or other materials provided with the distribution. 12 // * Neither the name of ARM Limited nor the names of its contributors may be 13 // used to endorse or promote products derived from this software without 14 // specific prior written permission. 15 // 16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 20 // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23 // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 27 { 28 "mnemonics": [ 29 "Vabd", // VABD{<c>}{<q>}.F32 {<Dd>}, <Dn>, <Dm> ; T1 30 // VABD{<c>}{<q>}.F32 {<Dd>}, <Dn>, <Dm> ; A1 31 "Vadd", // VADD{<c>}{<q>}.F32 {<Dd>}, <Dn>, <Dm> ; A1 32 // VADD{<c>}{<q>}.F64 {<Dd>}, <Dn>, <Dm> ; A2 33 // VADD{<c>}{<q>}.F32 {<Dd>}, <Dn>, <Dm> ; T1 34 // VADD{<c>}{<q>}.F64 {<Dd>}, <Dn>, <Dm> ; T2 35 "Vceq", // VCEQ{<c>}{<q>}.<dt> {<Dd>}, <Dn>, <Dm> ; A2 36 // VCEQ{<c>}{<q>}.<dt> {<Dd>}, <Dn>, <Dm> ; T2 37 "Vcge", // VCGE{<c>}{<q>}.F32 {<Dd>}, <Dn>, <Dm> ; A2 38 // VCGE{<c>}{<q>}.F32 {<Dd>}, <Dn>, <Dm> ; T2 39 "Vcgt", // VCGT{<c>}{<q>}.F32 {<Dd>}, <Dn>, <Dm> ; A2 40 // VCGT{<c>}{<q>}.F32 {<Dd>}, <Dn>, <Dm> ; T2 41 "Vcle", // VCLE{<c>}{<q>}.F32 {<Dd>}, <Dn>, <Dm> ; A2 42 // VCLE{<c>}{<q>}.F32 {<Dd>}, <Dn>, <Dm> ; T2 43 "Vclt", // VCLT{<c>}{<q>}.F32 {<Dd>}, <Dn>, <Dm> ; A2 44 // VCLT{<c>}{<q>}.F32 {<Dd>}, <Dn>, <Dm> ; T2 45 "Vmax", // VMAX{<c>}{<q>}.F32 {<Dd>}, <Dn>, <Dm> ; A1 46 // VMAX{<c>}{<q>}.F32 {<Dd>}, <Dn>, <Dm> ; T1 47 "Vmin", // VMIN{<c>}{<q>}.F32 {<Dd>}, <Dn>, <Dm> ; A1 48 // VMIN{<c>}{<q>}.F32 {<Dd>}, <Dn>, <Dm> ; T1 49 "Vpadd", // VPADD{<c>}{<q>}.F32 {<Dd>}, <Dn>, <Dm> ; A1 50 // VPADD{<c>}{<q>}.F32 {<Dd>}, <Dn>, <Dm> ; T1 51 "Vpmax", // VPMAX{<c>}{<q>}.F32 {<Dd>}, <Dn>, <Dm> ; A1 52 // VPMAX{<c>}{<q>}.F32 {<Dd>}, <Dn>, <Dm> ; T1 53 "Vpmin", // VPMIN{<c>}{<q>}.F32 {<Dd>}, <Dn>, <Dm> ; A1 54 // VPMIN{<c>}{<q>}.F32 {<Dd>}, <Dn>, <Dm> ; T1 55 "Vsub" // VSUB{<c>}{<q>}.F32 {<Dd>}, <Dn>, <Dm> ; A1 56 // VSUB{<c>}{<q>}.F64 {<Dd>}, <Dn>, <Dm> ; A2 57 // VSUB{<c>}{<q>}.F32 {<Dd>}, <Dn>, <Dm> ; T1 58 // VSUB{<c>}{<q>}.F64 {<Dd>}, <Dn>, <Dm> ; T2 59 ], 60 "description": { 61 "operands": [ 62 { 63 "name": "dt", 64 "type": "DataTypeFloat" 65 }, 66 { 67 "name": "rd", 68 "type": "DRegister" 69 }, 70 { 71 "name": "rn", 72 "type": "DRegister" 73 }, 74 { 75 "name": "rm", 76 "type": "DRegister" 77 } 78 ], 79 "inputs": [ 80 { 81 "name": "fpscr", 82 "type": "FPSCR" 83 }, 84 { 85 "name": "rd", 86 "type": "DRegisterF64" 87 }, 88 { 89 "name": "rn", 90 "type": "DRegisterF64" 91 }, 92 { 93 "name": "rm", 94 "type": "DRegisterF64" 95 } 96 ] 97 }, 98 "test-files": [ 99 { 100 "name": "not-f16", 101 "type": "assembler", 102 "mnemonics" : [ 103 "Vadd", 104 "Vsub" 105 ], 106 "test-cases": [ 107 { 108 "name": "Floats", 109 "operands": [ 110 "cond", "dt", "rd", "rn", "rm" 111 ], 112 "operand-filter": "dt in ['F32', 'F64']", 113 "operand-limit": 100 114 } 115 ] 116 }, 117 { 118 "name": "f32-only", 119 "type": "assembler", 120 "mnemonics" : [ 121 "Vceq", 122 "Vpadd", 123 "Vabd", 124 "Vcge", 125 "Vcgt", 126 "Vcle", 127 "Vclt", 128 "Vmax", 129 "Vmin", 130 "Vpmax", 131 "Vpmin" 132 ], 133 "test-cases": [ 134 { 135 "name": "Floats", 136 "operands": [ 137 "cond", "dt", "rd", "rn", "rm" 138 ], 139 "operand-filter": "dt == 'F32'", 140 "operand-limit": 100 141 } 142 ] 143 }, 144 // TODO: Add f32 test for VADD and VSUB. 145 { 146 "name": "f64", 147 "type": "simulator", 148 "mnemonics" : [ 149 "Vadd", 150 "Vsub" 151 ], 152 "test-cases": [ 153 { 154 "name": "Floats", 155 "operands": [ 156 "cond", "dt", "rd", "rn", "rm" 157 ], 158 "operand-filter": "dt == 'F64' and rn != rm", 159 "operand-limit": 100, 160 "inputs": [ 161 "rd", "rn", "rm" 162 ], 163 "input-limit": 100 164 }, 165 { 166 "name": "FloatsSameRegisters", 167 "operands": [ 168 "cond", "dt", "rd", "rn", "rm" 169 ], 170 "operand-filter": "dt == 'F64' and rn == rm", 171 "operand-limit": 100, 172 "inputs": [ 173 "rd", "rn", "rm" 174 ], 175 "input-filter": "rn == rm", 176 "input-limit": 100 177 } 178 ] 179 } 180 ] 181 } 182
