1 // Copyright 2016, VIXL authors 2 // All rights reserved. 3 // 4 // Redistribution and use in source and binary forms, with or without 5 // modification, are permitted provided that the following conditions are met: 6 // 7 // * Redistributions of source code must retain the above copyright notice, 8 // this list of conditions and the following disclaimer. 9 // * Redistributions in binary form must reproduce the above copyright notice, 10 // this list of conditions and the following disclaimer in the documentation 11 // and/or other materials provided with the distribution. 12 // * Neither the name of ARM Limited nor the names of its contributors may be 13 // used to endorse or promote products derived from this software without 14 // specific prior written permission. 15 // 16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 20 // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23 // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 27 { 28 "mnemonics": [ 29 "Ldr", 30 "Ldrb", 31 "Str", 32 "Strb" 33 ], 34 "description": { 35 "operands": [ 36 { 37 "name": "cond", 38 "type": "Condition" 39 }, 40 { 41 "name": "rd", 42 "type": "AllRegistersButPC" 43 }, 44 { 45 "name": "memop", 46 "wrapper": "MemOperand", 47 "operands": [ 48 { 49 "name": "rn", 50 "type": "AllRegistersButPC" 51 }, 52 { 53 "name": "sign", 54 "type": "Sign" 55 }, 56 { 57 "name": "rm", 58 "type": "AllRegistersButPC" 59 }, 60 { 61 "name": "shift", 62 "type": "Shift1To32" 63 }, 64 { 65 "name": "amount", 66 "type": "ShiftAmount1To32" 67 }, 68 { 69 "name": "addr_mode", 70 "type": "AddressingMode" 71 } 72 ] 73 } 74 ], 75 "inputs": [ 76 { 77 "name": "apsr", 78 "type": "NZCV" 79 }, 80 { 81 "name": "rd", 82 "type": "Register" 83 }, 84 { 85 "name": "rm", 86 "type": "RegisterOffsetLowerThan4096" 87 }, 88 { 89 "name": "memop", 90 "type": "MemOperand" 91 } 92 ] 93 }, 94 "test-files": [ 95 { 96 "type": "assembler", 97 "test-cases": [ 98 { 99 "name": "Registers", 100 "operands": [ 101 "cond", "rd", "rn", "rm" 102 ], 103 "operand-limit": 100 104 }, 105 { 106 "name": "MemOperandsOffset", 107 "operands": [ 108 "rn", "sign", "rm", "shift", "amount", "addr_mode" 109 ], 110 "operand-filter": "addr_mode == 'Offset'", 111 "operand-limit": 200 112 }, 113 { 114 "name": "MemOperandsWriteBack", 115 "operands": [ 116 "rd", "rn", "sign", "rm", "shift", "amount", "addr_mode" 117 ], 118 "operand-filter": "addr_mode != 'Offset' and rd != rn", 119 "operand-limit": 400 120 } 121 ] 122 }, 123 { 124 // TODO: The simulator tests do not support the case where `rd` == 125 // `rn`. See `data_types.MemOperand.Epilogue()` for details. 126 "type": "simulator", 127 "test-cases": [ 128 { 129 "name": "Condition", 130 "operands": [ 131 "cond", "rd", "rn", "rm" 132 ], 133 "operand-filter": "rd == 'r0' and rn == 'r1' and rm == 'r8'", 134 "inputs": [ 135 "apsr" 136 ] 137 }, 138 { 139 "name": "PositiveOffset", 140 "operands": [ 141 "rd", "rn", "sign", "rm", "shift", "amount", "addr_mode" 142 ], 143 "operand-filter": "sign == 'plus' and addr_mode == 'Offset' and rd != rm and rd != rn and rn != rm", 144 "operand-limit": 100, 145 "inputs": [ 146 "memop", "rm" 147 ], 148 "input-limit": 10 149 }, 150 { 151 "name": "NegativeOffset", 152 "operands": [ 153 "rd", "rn", "sign", "rm", "shift", "amount", "addr_mode" 154 ], 155 "operand-filter": "sign == 'minus' and addr_mode == 'Offset' and rd != rm and rd != rn and rn != rm", 156 "operand-limit": 100, 157 "inputs": [ 158 "memop", "rm" 159 ], 160 "input-limit": 10 161 }, 162 { 163 "name": "PositivePostIndex", 164 "operands": [ 165 "rd", "rn", "sign", "rm", "shift", "amount", "addr_mode" 166 ], 167 "operand-filter": "sign == 'plus' and addr_mode == 'PostIndex' and rd != rm and rd != rn and rn != rm", 168 "operand-limit": 100, 169 "inputs": [ 170 "memop", "rm" 171 ], 172 "input-limit": 10 173 }, 174 { 175 "name": "NegativePostIndex", 176 "operands": [ 177 "rd", "rn", "sign", "rm", "shift", "amount", "addr_mode" 178 ], 179 "operand-filter": "sign == 'minus' and addr_mode == 'PostIndex' and rd != rm and rd != rn and rn != rm", 180 "operand-limit": 100, 181 "inputs": [ 182 "memop", "rm" 183 ], 184 "input-limit": 10 185 }, 186 { 187 "name": "PositivePreIndex", 188 "operands": [ 189 "rd", "rn", "sign", "rm", "shift", "amount", "addr_mode" 190 ], 191 "operand-filter": "sign == 'plus' and addr_mode == 'PreIndex' and rd != rm and rd != rn and rn != rm", 192 "operand-limit": 100, 193 "inputs": [ 194 "memop", "rm" 195 ], 196 "input-limit": 10 197 }, 198 { 199 "name": "NegativePreIndex", 200 "operands": [ 201 "rd", "rn", "sign", "rm", "shift", "amount", "addr_mode" 202 ], 203 "operand-filter": "sign == 'minus' and addr_mode == 'PreIndex' and rd != rm and rd != rn and rn != rm", 204 "operand-limit": 100, 205 "inputs": [ 206 "memop", "rm" 207 ], 208 "input-limit": 10 209 } 210 ] 211 } 212 ] 213 } 214
