1 // Copyright 2016, VIXL authors 2 // All rights reserved. 3 // 4 // Redistribution and use in source and binary forms, with or without 5 // modification, are permitted provided that the following conditions are met: 6 // 7 // * Redistributions of source code must retain the above copyright notice, 8 // this list of conditions and the following disclaimer. 9 // * Redistributions in binary form must reproduce the above copyright notice, 10 // this list of conditions and the following disclaimer in the documentation 11 // and/or other materials provided with the distribution. 12 // * Neither the name of ARM Limited nor the names of its contributors may be 13 // used to endorse or promote products derived from this software without 14 // specific prior written permission. 15 // 16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 20 // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23 // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 27 // Test description for instructions of the following form: 28 // MNEMONIC{<c>}.W <Rn>, <Rm>, LSL|ROR #<amount> 29 30 { 31 "mnemonics" : [ 32 "Cmn", // CMN{<c>}{<q>} <Rn>, <Rm> {, <shift> #<amount> } ; T2 33 "Cmp", // CMP{<c>}{<q>} <Rn>, <Rm>, <shift> #<amount> ; T3 34 "Mov", // MOV<c>{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; T2 35 // MOV{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; T3 36 "Movs", // MOVS{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; T2 37 // MOVS{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; T3 38 "Mvn", // MVN{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; T2 39 "Mvns", // MVNS{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; T2 40 "Teq", // TEQ{<c>}{<q>} <Rn>, <Rm> {, <shift> #<amount> } ; T1 41 "Tst" // TST{<c>}{<q>} <Rn>, <Rm> {, <shift> #<amount> } ; T2 42 ], 43 "description" : { 44 "operands": [ 45 { 46 "name": "cond", 47 "type": "Condition" 48 }, 49 { 50 "name": "rd", 51 "type": "AllRegistersButPC" 52 }, 53 { 54 "name": "op", 55 "wrapper": "Operand", 56 "operands": [ 57 { 58 "name": "rn", 59 "type": "AllRegistersButPC" 60 }, 61 { 62 "name": "shift", 63 "type": "Shift1To31" 64 }, 65 { 66 "name": "amount", 67 "type": "ShiftAmount1To31" 68 } 69 ] 70 } 71 ], 72 "inputs": [ 73 { 74 "name": "apsr", 75 "type": "NZCV" 76 }, 77 { 78 "name": "rd", 79 "type": "Register" 80 }, 81 { 82 "name": "rn", 83 "type": "Register" 84 } 85 ] 86 }, 87 "test-files": [ 88 { 89 "type": "assembler", 90 "test-cases": [ 91 { 92 "name": "Unconditional", 93 "operands": [ 94 "cond", "rd", "rn", "shift", "amount" 95 ], 96 "operand-filter": "cond == 'al'", 97 "operand-limit": 1000 98 } 99 ] 100 }, 101 // Test instructions in an IT block with no restrictions on registers. 102 { 103 "name": "in-it-block", 104 "type": "assembler", 105 "mnemonics" : [ 106 "Mov" // MOV<c>{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; T2 107 ], 108 "test-cases": [ 109 { 110 "name": "InITBlock", 111 "operands": [ 112 "cond", "rd", "rn", "shift", "amount" 113 ], 114 // Generate an extra IT instruction. 115 "in-it-block": "{cond}", 116 "operand-filter": "cond != 'al' and register_is_low(rd) and register_is_low(rn) and shift != 'ROR'", 117 "operand-limit": 1000 118 } 119 ] 120 }, 121 { 122 "type": "simulator", 123 "test-cases": [ 124 { 125 "name": "Condition", 126 "operands": [ 127 "cond" 128 ], 129 "inputs": [ 130 "apsr" 131 ] 132 }, 133 // Test combinations of registers values with rd == rn. 134 { 135 "name": "RdIsRn", 136 "operands": [ 137 "rd", "rn" 138 ], 139 "inputs": [ 140 "rd", "rn" 141 ], 142 "operand-filter": "rd == rn", 143 "input-filter": "rd == rn" 144 }, 145 // Test combinations of registers values. 146 { 147 "name": "RdIsNotRn", 148 "operands": [ 149 "rd", "rn" 150 ], 151 "inputs": [ 152 "rd", "rn" 153 ], 154 "operand-filter": "rd != rn", 155 "operand-limit": 10, 156 "input-limit": 200 157 }, 158 // Test combinations of shift types and register values. 159 { 160 "name": "ShiftTypes", 161 "operands": [ 162 "rd", "rn", "shift", "amount" 163 ], 164 "inputs": [ 165 "rn" 166 ], 167 // Specify exactly what registers to use in this test to make sure 168 // that they are different. It makes the execution trace more 169 // understandable. 170 "operand-filter": "rd == 'r0' and rn == 'r1'" 171 } 172 ] 173 } 174 ] 175 } 176
