1 // Copyright 2016, VIXL authors 2 // All rights reserved. 3 // 4 // Redistribution and use in source and binary forms, with or without 5 // modification, are permitted provided that the following conditions are met: 6 // 7 // * Redistributions of source code must retain the above copyright notice, 8 // this list of conditions and the following disclaimer. 9 // * Redistributions in binary form must reproduce the above copyright notice, 10 // this list of conditions and the following disclaimer in the documentation 11 // and/or other materials provided with the distribution. 12 // * Neither the name of ARM Limited nor the names of its contributors may be 13 // used to endorse or promote products derived from this software without 14 // specific prior written permission. 15 // 16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 20 // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23 // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 27 // Test description for instructions of the following forms: 28 // MNEMONIC{<c>}.W <Rd>, <Rn>, #<const> 29 // MNEMONIC{<c>}.W <Rd>, SP, #<const> 30 // 31 // The instructions covered in this test do not write to the `Q` and `GE` flags, 32 // these are covered in other description files. 33 34 { 35 "mnemonics" : [ 36 "Adc", // ADC{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; T1 37 "Adcs", // ADCS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; T1 38 "Add", // ADD{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; T3 39 // ADD{<c>}{<q>} {<Rd>}, SP, #<const> ; T3 40 "Adds", // ADDS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; T3 41 // ADDS{<c>}{<q>} {<Rd>}, SP, #<const> ; T3 42 "And", // AND{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; T1 43 "Ands", // ANDS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; T1 44 "Bic", // BIC{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; T1 45 "Bics", // BICS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; T1 46 "Eor", // EOR{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; T1 47 "Eors", // EORS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; T1 48 "Orn", // ORN{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; T1 49 "Orns", // ORNS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; T1 50 "Orr", // ORR{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; T1 51 "Orrs", // ORRS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; T1 52 "Rsb", // RSB{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; T2 53 "Rsbs", // RSBS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; T2 54 "Sbc", // SBC{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; T1 55 "Sbcs", // SBCS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; T1 56 "Sub", // SUB{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; T3 57 // SUB{<c>}{<q>} {<Rd>}, SP, #<const> ; T2 58 "Subs" // SUBS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; T3 59 // SUBS{<c>}{<q>} {<Rd>}, SP, #<const> ; T2 60 ], 61 "description" : { 62 "operands": [ 63 { 64 "name": "cond", 65 "type": "Always" 66 }, 67 { 68 "name": "rd", 69 "type": "AllRegistersButPC" 70 }, 71 { 72 "name": "rn", 73 "type": "AllRegistersButPC" 74 }, 75 { 76 "name": "op", 77 "wrapper": "Operand", 78 "operands": [ 79 { 80 "name": "immediate", 81 "type": "T32ModifiedImmediate" 82 } 83 ] 84 } 85 ], 86 "inputs":[ 87 { 88 "name": "apsr", 89 "type": "NZCV" 90 }, 91 { 92 "name": "rd", 93 "type": "Register" 94 }, 95 { 96 "name": "rn", 97 "type": "Register" 98 } 99 ] 100 }, 101 "test-files": [ 102 { 103 "type": "assembler", 104 "test-cases": [ 105 { 106 "name": "Operands", 107 "operands": [ 108 "rd", "rn", "immediate" 109 ], 110 "operand-limit": 500 111 } 112 ] 113 }, 114 { 115 "type": "simulator", 116 "test-cases": [ 117 { 118 "name": "RdIsRn", 119 "operands": [ 120 "rd", "rn", "immediate" 121 ], 122 "inputs": [ 123 "rd", "rn" 124 ], 125 "operand-filter": "rd == rn", 126 "operand-limit": 10, 127 "input-filter": "rd == rn" 128 }, 129 { 130 "name": "RdIsNotRn", 131 "operands": [ 132 "rd", "rn", "immediate" 133 ], 134 "inputs": [ 135 "rd", "rn" 136 ], 137 "operand-filter": "rd != rn", 138 "operand-limit": 10 139 }, 140 { 141 "name": "ModifiedImmediate", 142 "operands": [ 143 "immediate" 144 ], 145 "inputs": [ 146 "rn" 147 ] 148 } 149 ] 150 } 151 ] 152 } 153
