1 // Copyright 2016, VIXL authors 2 // All rights reserved. 3 // 4 // Redistribution and use in source and binary forms, with or without 5 // modification, are permitted provided that the following conditions are met: 6 // 7 // * Redistributions of source code must retain the above copyright notice, 8 // this list of conditions and the following disclaimer. 9 // * Redistributions in binary form must reproduce the above copyright notice, 10 // this list of conditions and the following disclaimer in the documentation 11 // and/or other materials provided with the distribution. 12 // * Neither the name of ARM Limited nor the names of its contributors may be 13 // used to endorse or promote products derived from this software without 14 // specific prior written permission. 15 // 16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 20 // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23 // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 27 // Test description for instructions of the following form: 28 // MNEMONIC <Rd>, <Rn>, <Rm> 29 30 { 31 "mnemonics" : [ 32 "Crc32b", // CRC32B{<q>} <Rd>, <Rn>, <Rm> ; A1 33 // CRC32B{<q>} <Rd>, <Rn>, <Rm> ; T1 34 "Crc32cb", // CRC32CB{<q>} <Rd>, <Rn>, <Rm> ; A1 35 // CRC32CB{<q>} <Rd>, <Rn>, <Rm> ; T1 36 "Crc32ch", // CRC32CH{<q>} <Rd>, <Rn>, <Rm> ; A1 37 // CRC32CH{<q>} <Rd>, <Rn>, <Rm> ; T1 38 "Crc32cw", // CRC32CW{<q>} <Rd>, <Rn>, <Rm> ; A1 39 // CRC32CW{<q>} <Rd>, <Rn>, <Rm> ; T1 40 "Crc32h", // CRC32H{<q>} <Rd>, <Rn>, <Rm> ; A1 41 // CRC32H{<q>} <Rd>, <Rn>, <Rm> ; T1 42 "Crc32w" // CRC32W{<q>} <Rd>, <Rn>, <Rm> ; A1 43 // CRC32W{<q>} <Rd>, <Rn>, <Rm> ; T1 44 ], 45 "description" : { 46 "operands": [ 47 { 48 "name": "rd", 49 "type": "AllRegistersButPC" 50 }, 51 { 52 "name": "rn", 53 "type": "AllRegistersButPC" 54 }, 55 { 56 "name": "rm", 57 "type": "AllRegistersButPC" 58 } 59 ], 60 "inputs": [ 61 { 62 "name": "rd", 63 "type": "Register" 64 }, 65 { 66 "name": "rn", 67 "type": "Register" 68 }, 69 { 70 "name": "rm", 71 "type": "Register" 72 } 73 ] 74 }, 75 "test-files": [ 76 { 77 "type": "assembler", 78 "test-cases": [ 79 { 80 "name": "Registers", 81 "operands": [ 82 "rd", "rn", "rm" 83 ], 84 "operand-limit": 500 85 } 86 ] 87 }, 88 { 89 "type": "simulator", 90 "test-cases": [ 91 { 92 "name": "RnIsRm", 93 "operands": [ 94 "rd", "rn", "rm" 95 ], 96 "inputs": [ 97 "rd", "rn", "rm" 98 ], 99 "operand-filter": "rn == rm", 100 "operand-limit": 10, 101 "input-filter": "rn == rm", 102 "input-limit": 200 103 }, 104 { 105 "name": "RnIsNotRm", 106 "operands": [ 107 "rd", "rn", "rm" 108 ], 109 "inputs": [ 110 "rd", "rn", "rm" 111 ], 112 "operand-filter": "rn != rm", 113 "operand-limit": 10, 114 "input-filter": "rn != rm", 115 "input-limit": 200 116 } 117 ] 118 } 119 ] 120 } 121
