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      1 // Copyright 2015, VIXL authors
      2 // All rights reserved.
      3 //
      4 // Redistribution and use in source and binary forms, with or without
      5 // modification, are permitted provided that the following conditions are met:
      6 //
      7 //   * Redistributions of source code must retain the above copyright notice,
      8 //     this list of conditions and the following disclaimer.
      9 //   * Redistributions in binary form must reproduce the above copyright notice,
     10 //     this list of conditions and the following disclaimer in the documentation
     11 //     and/or other materials provided with the distribution.
     12 //   * Neither the name of ARM Limited nor the names of its contributors may be
     13 //     used to endorse or promote products derived from this software without
     14 //     specific prior written permission.
     15 //
     16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
     17 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
     18 // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
     19 // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
     20 // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     21 // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
     22 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
     23 // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     24 // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
     25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     26 
     27 
     28 // ---------------------------------------------------------------------
     29 // This file is auto generated using tools/generate_simulator_traces.py.
     30 //
     31 // PLEASE DO NOT EDIT.
     32 // ---------------------------------------------------------------------
     33 
     34 #ifndef VIXL_SIM_FCVTNU_WD_TRACE_AARCH64_H_
     35 #define VIXL_SIM_FCVTNU_WD_TRACE_AARCH64_H_
     36 
     37 const uint32_t kExpected_fcvtnu_wd[] = {
     38   0u,
     39   0u,
     40   0u,
     41   0u,
     42   1u,
     43   1u,
     44   1u,
     45   1u,
     46   2u,
     47   10u,
     48   4294967295u,
     49   4294967295u,
     50   0u,
     51   0u,
     52   0u,
     53   4294967295u,
     54   0u,
     55   0u,
     56   0u,
     57   0u,
     58   0u,
     59   0u,
     60   0u,
     61   0u,
     62   0u,
     63   0u,
     64   0u,
     65   0u,
     66   0u,
     67   0u,
     68   0u,
     69   0u,
     70   0u,
     71   0u,
     72   0u,
     73   0u,
     74   0u,
     75   0u,
     76   4294967295u,
     77   0u,
     78   1u,
     79   1u,
     80   1u,
     81   1u,
     82   1u,
     83   1u,
     84   1u,
     85   1u,
     86   1u,
     87   1u,
     88   1u,
     89   1u,
     90   1u,
     91   1u,
     92   4294967295u,
     93   4294967295u,
     94   4294967295u,
     95   0u,
     96   0u,
     97   0u,
     98   0u,
     99   0u,
    100   0u,
    101   0u,
    102   0u,
    103   0u,
    104   0u,
    105   0u,
    106   0u,
    107   0u,
    108   0u,
    109   0u,
    110   0u,
    111   0u,
    112   0u,
    113   0u,
    114   0u,
    115   0u,
    116   0u,
    117   0u,
    118   0u,
    119   0u,
    120   0u,
    121   0u,
    122   0u,
    123   0u,
    124   0u,
    125   0u,
    126   0u,
    127   0u,
    128   0u,
    129   0u,
    130   0u,
    131   0u,
    132   0u,
    133   0u,
    134   0u,
    135   0u,
    136   0u,
    137   0u,
    138   0u,
    139   0u,
    140   0u,
    141   0u,
    142   0u,
    143   0u,
    144   0u,
    145   0u,
    146   0u,
    147   0u,
    148   4294967295u,
    149   4294967295u,
    150   4294967295u,
    151   4294967295u,
    152   4294967295u,
    153   4294967295u,
    154   4294967295u,
    155   4294967295u,
    156   4294967295u,
    157   4294967295u,
    158   4294967295u,
    159   4294967295u,
    160   4294967295u,
    161   4294967295u,
    162   4294967295u,
    163   4294967295u,
    164   4294967295u,
    165   4294967295u,
    166   4294967295u,
    167   4294967295u,
    168   4294967295u,
    169   4294967295u,
    170   4294967295u,
    171   4294967295u,
    172   4294967295u,
    173   4294967295u,
    174   4294967295u,
    175   0u,
    176   0u,
    177   0u,
    178   0u,
    179   0u,
    180   0u,
    181   0u,
    182   0u,
    183   0u,
    184   0u,
    185   0u,
    186   0u,
    187   0u,
    188   0u,
    189   0u,
    190   0u,
    191   0u,
    192   0u,
    193   0u,
    194   0u,
    195   0u,
    196   0u,
    197   0u,
    198   0u,
    199   0u,
    200   0u,
    201   0u,
    202   0u,
    203   0u,
    204   0u,
    205   4294967295u,
    206   4294967295u,
    207   4294967295u,
    208   4294967295u,
    209   0u,
    210   0u,
    211   0u,
    212   0u,
    213   0u,
    214   0u,
    215   0u,
    216   0u,
    217   0u,
    218   0u,
    219   0u,
    220   0u,
    221   2147483646u,
    222   2147483646u,
    223   2147483646u,
    224   2147483646u,
    225   2147483646u,
    226   2147483647u,
    227   2147483647u,
    228   2147483647u,
    229   2147483647u,
    230   2147483647u,
    231   2147483648u,
    232   2147483648u,
    233   4294967294u,
    234   4294967294u,
    235   4294967294u,
    236   4294967294u,
    237   4294967294u,
    238   4294967295u,
    239   4294967295u,
    240   4294967295u,
    241   4294967295u,
    242   4294967295u,
    243   4294967295u,
    244   4294967295u,
    245 };
    246 const unsigned kExpectedCount_fcvtnu_wd = 207;
    247 
    248 #endif  // VIXL_SIM_FCVTNU_WD_TRACE_AARCH64_H_
    249