1 /* ------------------------------------------------------------------ 2 * Copyright (C) 1998-2009 PacketVideo 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either 13 * express or implied. 14 * See the License for the specific language governing permissions 15 * and limitations under the License. 16 * ------------------------------------------------------------------- 17 */ 18 /**************************************************************************************** 19 Portions of this file are derived from the following 3GPP standard: 20 21 3GPP TS 26.173 22 ANSI-C code for the Adaptive Multi-Rate - Wideband (AMR-WB) speech codec 23 Available from http://www.3gpp.org 24 25 (C) 2007, 3GPP Organizational Partners (ARIB, ATIS, CCSA, ETSI, TTA, TTC) 26 Permission to distribute, modify and use this file under the standard license 27 terms listed above has been obtained from the copyright holder. 28 ****************************************************************************************/ 29 /* 30 ------------------------------------------------------------------------------ 31 32 33 34 Pathname: ./src/pvamrwbdecoder_basic_op_armv5.h 35 36 Date: 05/07/2007 37 38 ------------------------------------------------------------------------------ 39 REVISION HISTORY 40 41 Description: 42 ------------------------------------------------------------------------------ 43 INCLUDE DESCRIPTION 44 45 ------------------------------------------------------------------------------ 46 */ 47 48 #ifndef PVAMRWBDECODER_BASIC_OP_ARMV5_H 49 #define PVAMRWBDECODER_BASIC_OP_ARMV5_H 50 51 #ifdef __cplusplus 52 extern "C" 53 { 54 #endif 55 56 57 58 59 60 #if defined(PV_ARM_V5) 61 62 __inline int16 add_int16(int16 var1, int16 var2) 63 { 64 int32 L_var_out; 65 int32 L_var_aux; 66 67 __asm 68 { 69 mov L_var_out, var1, lsl #16 70 mov L_var_aux, var2, lsl #16 71 qadd L_var_out, L_var_out, L_var_aux 72 mov L_var_out, L_var_out, asr #16 73 74 } 75 return L_var_out; 76 } 77 78 79 __inline int16 sub_int16(int16 var1, int16 var2) 80 { 81 int32 L_var_out; 82 int32 L_var_aux; 83 84 __asm 85 { 86 mov L_var_out, var1, lsl #16 87 mov L_var_aux, var2, lsl #16 88 qsub L_var_out, L_var_out, L_var_aux 89 mov L_var_out, L_var_out, asr #16 90 91 } 92 return L_var_out; 93 } 94 95 96 __inline int32 add_int32(int32 L_var1, int32 L_var2) 97 { 98 int32 L_var_out; 99 100 __asm 101 { 102 qadd L_var_out, L_var1, L_var2 103 } 104 return L_var_out; 105 } 106 107 108 __inline int32 mac_16by16_to_int32(int32 L_var3, int16 var1, int16 var2) 109 { 110 int32 L_var_out; 111 112 113 __asm 114 { 115 smulbb L_var_out, var1, var2 116 qdadd L_var_out, L_var3, L_var_out 117 } 118 return L_var_out; 119 } 120 121 __inline int32 sub_int32(int32 L_var1, int32 L_var2) 122 { 123 int32 L_var_out; 124 125 __asm 126 { 127 qsub L_var_out, L_var1, L_var2 128 } 129 return L_var_out; 130 } 131 132 __inline int32 msu_16by16_from_int32(int32 L_var3, int16 var1, int16 var2) 133 { 134 int32 L_var_out; 135 136 137 __asm 138 { 139 smulbb L_var_out, var1, var2 140 qdsub L_var_out, L_var3, L_var_out 141 } 142 return L_var_out; 143 } 144 145 __inline int32 mul_16by16_to_int32(int16 var1, int16 var2) 146 { 147 int32 L_var_out; 148 149 __asm 150 { 151 smulbb L_var_out, var1, var2 152 qadd L_var_out, L_var_out, L_var_out 153 } 154 return L_var_out; 155 } 156 157 __inline int16 mult_int16(int16 var1, int16 var2) 158 { 159 int32 L_var_out; 160 161 __asm 162 { 163 smulbb L_var_out, var1, var2 164 mov L_var_out, L_var_out, asr #15 165 } 166 return L_var_out; 167 } 168 169 170 __inline int16 amr_wb_round(int32 L_var1) 171 { 172 int32 L_var_out; 173 174 __asm 175 { 176 qadd L_var_out, L_var1, (int32) 0x00008000L 177 mov L_var_out, L_var_out, asr #16 178 } 179 return L_var_out; 180 } 181 182 183 184 __inline int16 amr_wb_shl1_round(int32 L_var1) 185 { 186 int32 L_var_out; 187 188 __asm 189 { 190 qadd L_var_out, L_var1, L_var1 191 qadd L_var_out, L_var_out, (int32) 0x00008000L 192 mov L_var_out, L_var_out, asr #16 193 } 194 return L_var_out; 195 } 196 197 __inline int32 mul_32by16(int16 hi, int16 lo, int16 n) 198 { 199 int32 H_32; 200 int32 L_32; 201 __asm 202 { 203 smulbb H_32, hi, n 204 smulbb L_32, lo, n 205 add H_32, H_32, L_32, asr #15 206 qadd H_32, H_32, H_32 207 } 208 209 return (H_32); 210 } 211 212 __inline int32 fxp_mac_16by16(const int16 var1, const int16 var2, int32 L_add) 213 { 214 __asm 215 { 216 smlabb L_add, var1, var2, L_add 217 } 218 return (L_add); 219 } 220 221 __inline int32 fxp_mul_16by16(int16 var1, const int16 var2) 222 { 223 int32 L_mult; 224 __asm 225 { 226 smulbb L_mult, var1, var2 227 } 228 return (L_mult); 229 } 230 231 __inline int32 fxp_mul32_by_16b(int32 L_var1, const int32 L_var2) 232 { 233 int32 L_mult; 234 __asm 235 { 236 smulwb L_mult, L_var1, L_var2 237 } 238 239 return L_mult; 240 } 241 242 243 #endif 244 245 #ifdef __cplusplus 246 } 247 #endif 248 249 250 251 252 #endif /* PVAMRWBDECODER_BASIC_OP_ARMV5_H */ 253 254
