1 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32-S64" 2 target triple = "armv7-none-linux-gnueabi" 3 4 declare i8* @rsOffset([1 x i32] %a.coerce, i32 %sizeOf, i32 %x, i32 %y, i32 %z) 5 declare i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) 6 7 ; The loads and stores in this file are annotated with RenderScript-specific 8 ; information for the type based alias analysis, such that the TBAA analysis 9 ; understands that loads and stores from two allocations with different types 10 ; can never access the same memory element. This is different from C, where 11 ; a char or uchar load/store is special as it can alias with about everything. 12 ; 13 ; The TBAA tree in this file has the the node "RenderScript Distinct TBAA" as 14 ; its root. 15 ; This means all loads/stores that share this common root can be proven to not 16 ; alias. However, the alias analysis still has to assume MayAlias between 17 ; memory accesses in this file and memory accesses annotated with the C/C++ 18 ; TBAA metadata. 19 ; A node named "RenderScript TBAA" wraps our distinct TBAA root node. 20 ; If we can ensure that all accesses to elements loaded from RenderScript 21 ; allocations are either annotated with the RenderScript TBAA information or 22 ; not annotated at all, but never annotated with the C/C++ metadata, we 23 ; can add the "RenderScript TBAA" tree under the C/C++ TBAA tree. This enables 24 ; TBAA to prove that an access to data from the RenderScript allocation 25 ; does not alias with a load/store accessing something not part of a RenderScript 26 ; allocation. 27 ; We do this by swapping the second operand of "RenderScript TBAA" with the node 28 ; for "Simple C/C++ TBAA", thus connecting these TBAA groups. The other root 29 ; node (with no children) can then safely be dropped from the analysis. 30 31 !13 = !{!"RenderScript Distinct TBAA"} 32 !14 = !{!"RenderScript TBAA", !13} 33 !15 = !{!"allocation", !14} 34 35 !21 = !{!"char", !15} 36 define void @rsSetElementAtImpl_char([1 x i32] %a.coerce, i8 signext %val, i32 %x, i32 %y, i32 %z) #1 { 37 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 1, i32 %x, i32 %y, i32 %z) #2 38 store i8 %val, i8* %1, align 1, !tbaa !21 39 ret void 40 } 41 42 define signext i8 @rsGetElementAtImpl_char([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 43 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 1, i32 %x, i32 %y, i32 %z) #2 44 %2 = load i8, i8* %1, align 1, !tbaa !21 45 ret i8 %2 46 } 47 48 !22 = !{!"char2", !15} 49 define void @rsSetElementAtImpl_char2([1 x i32] %a.coerce, <2 x i8> %val, i32 %x, i32 %y, i32 %z) #1 { 50 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 2, i32 %x, i32 %y, i32 %z) #2 51 %2 = bitcast i8* %1 to <2 x i8>* 52 store <2 x i8> %val, <2 x i8>* %2, align 2, !tbaa !22 53 ret void 54 } 55 56 define <2 x i8> @rsGetElementAtImpl_char2([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 57 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 2, i32 %x, i32 %y, i32 %z) #2 58 %2 = bitcast i8* %1 to <2 x i8>* 59 %3 = load <2 x i8>, <2 x i8>* %2, align 2, !tbaa !22 60 ret <2 x i8> %3 61 } 62 63 !23 = !{!"char3", !15} 64 define void @rsSetElementAtImpl_char3([1 x i32] %a.coerce, <3 x i8> %val, i32 %x, i32 %y, i32 %z) #1 { 65 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 4, i32 %x, i32 %y, i32 %z) #2 66 %2 = shufflevector <3 x i8> %val, <3 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef> 67 %3 = bitcast i8* %1 to <4 x i8>* 68 store <4 x i8> %2, <4 x i8>* %3, align 4, !tbaa !23 69 ret void 70 } 71 72 define <3 x i8> @rsGetElementAtImpl_char3([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 73 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 4, i32 %x, i32 %y, i32 %z) #2 74 %2 = bitcast i8* %1 to <4 x i8>* 75 %3 = load <4 x i8>, <4 x i8>* %2, align 4, !tbaa !23 76 %4 = shufflevector <4 x i8> %3, <4 x i8> undef, <3 x i32> <i32 0, i32 1, i32 2> 77 ret <3 x i8> %4 78 } 79 80 !24 = !{!"char4", !15} 81 define void @rsSetElementAtImpl_char4([1 x i32] %a.coerce, <4 x i8> %val, i32 %x, i32 %y, i32 %z) #1 { 82 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 4, i32 %x, i32 %y, i32 %z) #2 83 %2 = bitcast i8* %1 to <4 x i8>* 84 store <4 x i8> %val, <4 x i8>* %2, align 4, !tbaa !24 85 ret void 86 } 87 88 define <4 x i8> @rsGetElementAtImpl_char4([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 89 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 4, i32 %x, i32 %y, i32 %z) #2 90 %2 = bitcast i8* %1 to <4 x i8>* 91 %3 = load <4 x i8>, <4 x i8>* %2, align 4, !tbaa !24 92 ret <4 x i8> %3 93 } 94 95 !25 = !{!"uchar", !15} 96 define void @rsSetElementAtImpl_uchar([1 x i32] %a.coerce, i8 zeroext %val, i32 %x, i32 %y, i32 %z) #1 { 97 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 1, i32 %x, i32 %y, i32 %z) #2 98 store i8 %val, i8* %1, align 1, !tbaa !25 99 ret void 100 } 101 102 define zeroext i8 @rsGetElementAtImpl_uchar([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 103 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 1, i32 %x, i32 %y, i32 %z) #2 104 %2 = load i8, i8* %1, align 1, !tbaa !25 105 ret i8 %2 106 } 107 108 !26 = !{!"uchar2", !15} 109 define void @rsSetElementAtImpl_uchar2([1 x i32] %a.coerce, <2 x i8> %val, i32 %x, i32 %y, i32 %z) #1 { 110 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 2, i32 %x, i32 %y, i32 %z) #2 111 %2 = bitcast i8* %1 to <2 x i8>* 112 store <2 x i8> %val, <2 x i8>* %2, align 2, !tbaa !26 113 ret void 114 } 115 116 define <2 x i8> @rsGetElementAtImpl_uchar2([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 117 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 2, i32 %x, i32 %y, i32 %z) #2 118 %2 = bitcast i8* %1 to <2 x i8>* 119 %3 = load <2 x i8>, <2 x i8>* %2, align 2, !tbaa !26 120 ret <2 x i8> %3 121 } 122 123 !27 = !{!"uchar3", !15} 124 define void @rsSetElementAtImpl_uchar3([1 x i32] %a.coerce, <3 x i8> %val, i32 %x, i32 %y, i32 %z) #1 { 125 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 4, i32 %x, i32 %y, i32 %z) #2 126 %2 = shufflevector <3 x i8> %val, <3 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef> 127 %3 = bitcast i8* %1 to <4 x i8>* 128 store <4 x i8> %2, <4 x i8>* %3, align 4, !tbaa !27 129 ret void 130 } 131 132 define <3 x i8> @rsGetElementAtImpl_uchar3([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 133 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 4, i32 %x, i32 %y, i32 %z) #2 134 %2 = bitcast i8* %1 to <4 x i8>* 135 %3 = load <4 x i8>, <4 x i8>* %2, align 4, !tbaa !27 136 %4 = shufflevector <4 x i8> %3, <4 x i8> undef, <3 x i32> <i32 0, i32 1, i32 2> 137 ret <3 x i8> %4 138 } 139 140 !28 = !{!"uchar4", !15} 141 define void @rsSetElementAtImpl_uchar4([1 x i32] %a.coerce, <4 x i8> %val, i32 %x, i32 %y, i32 %z) #1 { 142 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 4, i32 %x, i32 %y, i32 %z) #2 143 %2 = bitcast i8* %1 to <4 x i8>* 144 store <4 x i8> %val, <4 x i8>* %2, align 4, !tbaa !28 145 ret void 146 } 147 148 define <4 x i8> @rsGetElementAtImpl_uchar4([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 149 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 4, i32 %x, i32 %y, i32 %z) #2 150 %2 = bitcast i8* %1 to <4 x i8>* 151 %3 = load <4 x i8>, <4 x i8>* %2, align 4, !tbaa !28 152 ret <4 x i8> %3 153 } 154 155 !29 = !{!"short", !15} 156 define void @rsSetElementAtImpl_short([1 x i32] %a.coerce, i16 signext %val, i32 %x, i32 %y, i32 %z) #1 { 157 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 2, i32 %x, i32 %y, i32 %z) #2 158 %2 = bitcast i8* %1 to i16* 159 store i16 %val, i16* %2, align 2, !tbaa !29 160 ret void 161 } 162 163 define signext i16 @rsGetElementAtImpl_short([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 164 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 2, i32 %x, i32 %y, i32 %z) #2 165 %2 = bitcast i8* %1 to i16* 166 %3 = load i16, i16* %2, align 2, !tbaa !29 167 ret i16 %3 168 } 169 170 !30 = !{!"short2", !15} 171 define void @rsSetElementAtImpl_short2([1 x i32] %a.coerce, <2 x i16> %val, i32 %x, i32 %y, i32 %z) #1 { 172 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 4, i32 %x, i32 %y, i32 %z) #2 173 %2 = bitcast i8* %1 to <2 x i16>* 174 store <2 x i16> %val, <2 x i16>* %2, align 4, !tbaa !30 175 ret void 176 } 177 178 define <2 x i16> @rsGetElementAtImpl_short2([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 179 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 4, i32 %x, i32 %y, i32 %z) #2 180 %2 = bitcast i8* %1 to <2 x i16>* 181 %3 = load <2 x i16>, <2 x i16>* %2, align 4, !tbaa !30 182 ret <2 x i16> %3 183 } 184 185 !31 = !{!"short3", !15} 186 define void @rsSetElementAtImpl_short3([1 x i32] %a.coerce, <3 x i16> %val, i32 %x, i32 %y, i32 %z) #1 { 187 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 8, i32 %x, i32 %y, i32 %z) #2 188 %2 = shufflevector <3 x i16> %val, <3 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef> 189 %3 = bitcast i8* %1 to <4 x i16>* 190 store <4 x i16> %2, <4 x i16>* %3, align 8, !tbaa !31 191 ret void 192 } 193 194 define <3 x i16> @rsGetElementAtImpl_short3([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 195 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 8, i32 %x, i32 %y, i32 %z) #2 196 %2 = bitcast i8* %1 to <4 x i16>* 197 %3 = load <4 x i16>, <4 x i16>* %2, align 8, !tbaa !31 198 %4 = shufflevector <4 x i16> %3, <4 x i16> undef, <3 x i32> <i32 0, i32 1, i32 2> 199 ret <3 x i16> %4 200 } 201 202 !32 = !{!"short4", !15} 203 define void @rsSetElementAtImpl_short4([1 x i32] %a.coerce, <4 x i16> %val, i32 %x, i32 %y, i32 %z) #1 { 204 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 8, i32 %x, i32 %y, i32 %z) #2 205 %2 = bitcast i8* %1 to <4 x i16>* 206 store <4 x i16> %val, <4 x i16>* %2, align 8, !tbaa !32 207 ret void 208 } 209 210 define <4 x i16> @rsGetElementAtImpl_short4([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 211 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 8, i32 %x, i32 %y, i32 %z) #2 212 %2 = bitcast i8* %1 to <4 x i16>* 213 %3 = load <4 x i16>, <4 x i16>* %2, align 8, !tbaa !32 214 ret <4 x i16> %3 215 } 216 217 !33 = !{!"ushort", !15} 218 define void @rsSetElementAtImpl_ushort([1 x i32] %a.coerce, i16 zeroext %val, i32 %x, i32 %y, i32 %z) #1 { 219 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 2, i32 %x, i32 %y, i32 %z) #2 220 %2 = bitcast i8* %1 to i16* 221 store i16 %val, i16* %2, align 2, !tbaa !33 222 ret void 223 } 224 225 define zeroext i16 @rsGetElementAtImpl_ushort([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 226 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 2, i32 %x, i32 %y, i32 %z) #2 227 %2 = bitcast i8* %1 to i16* 228 %3 = load i16, i16* %2, align 2, !tbaa !33 229 ret i16 %3 230 } 231 232 !34 = !{!"ushort2", !15} 233 define void @rsSetElementAtImpl_ushort2([1 x i32] %a.coerce, <2 x i16> %val, i32 %x, i32 %y, i32 %z) #1 { 234 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 4, i32 %x, i32 %y, i32 %z) #2 235 %2 = bitcast i8* %1 to <2 x i16>* 236 store <2 x i16> %val, <2 x i16>* %2, align 4, !tbaa !34 237 ret void 238 } 239 240 define <2 x i16> @rsGetElementAtImpl_ushort2([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 241 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 4, i32 %x, i32 %y, i32 %z) #2 242 %2 = bitcast i8* %1 to <2 x i16>* 243 %3 = load <2 x i16>, <2 x i16>* %2, align 4, !tbaa !34 244 ret <2 x i16> %3 245 } 246 247 !35 = !{!"ushort3", !15} 248 define void @rsSetElementAtImpl_ushort3([1 x i32] %a.coerce, <3 x i16> %val, i32 %x, i32 %y, i32 %z) #1 { 249 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 8, i32 %x, i32 %y, i32 %z) #2 250 %2 = shufflevector <3 x i16> %val, <3 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef> 251 %3 = bitcast i8* %1 to <4 x i16>* 252 store <4 x i16> %2, <4 x i16>* %3, align 8, !tbaa !35 253 ret void 254 } 255 256 define <3 x i16> @rsGetElementAtImpl_ushort3([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 257 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 8, i32 %x, i32 %y, i32 %z) #2 258 %2 = bitcast i8* %1 to <4 x i16>* 259 %3 = load <4 x i16>, <4 x i16>* %2, align 8, !tbaa !35 260 %4 = shufflevector <4 x i16> %3, <4 x i16> undef, <3 x i32> <i32 0, i32 1, i32 2> 261 ret <3 x i16> %4 262 } 263 264 !36 = !{!"ushort4", !15} 265 define void @rsSetElementAtImpl_ushort4([1 x i32] %a.coerce, <4 x i16> %val, i32 %x, i32 %y, i32 %z) #1 { 266 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 8, i32 %x, i32 %y, i32 %z) #2 267 %2 = bitcast i8* %1 to <4 x i16>* 268 store <4 x i16> %val, <4 x i16>* %2, align 8, !tbaa !36 269 ret void 270 } 271 272 define <4 x i16> @rsGetElementAtImpl_ushort4([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 273 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 8, i32 %x, i32 %y, i32 %z) #2 274 %2 = bitcast i8* %1 to <4 x i16>* 275 %3 = load <4 x i16>, <4 x i16>* %2, align 8, !tbaa !36 276 ret <4 x i16> %3 277 } 278 279 !37 = !{!"int", !15} 280 define void @rsSetElementAtImpl_int([1 x i32] %a.coerce, i32 %val, i32 %x, i32 %y, i32 %z) #1 { 281 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 4, i32 %x, i32 %y, i32 %z) #2 282 %2 = bitcast i8* %1 to i32* 283 store i32 %val, i32* %2, align 4, !tbaa !37 284 ret void 285 } 286 287 define i32 @rsGetElementAtImpl_int([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 288 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 4, i32 %x, i32 %y, i32 %z) #2 289 %2 = bitcast i8* %1 to i32* 290 %3 = load i32, i32* %2, align 4, !tbaa !37 291 ret i32 %3 292 } 293 294 !38 = !{!"int2", !15} 295 define void @rsSetElementAtImpl_int2([1 x i32] %a.coerce, <2 x i32> %val, i32 %x, i32 %y, i32 %z) #1 { 296 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 8, i32 %x, i32 %y, i32 %z) #2 297 %2 = bitcast i8* %1 to <2 x i32>* 298 store <2 x i32> %val, <2 x i32>* %2, align 8, !tbaa !38 299 ret void 300 } 301 302 define <2 x i32> @rsGetElementAtImpl_int2([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 303 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 8, i32 %x, i32 %y, i32 %z) #2 304 %2 = bitcast i8* %1 to <2 x i32>* 305 %3 = load <2 x i32>, <2 x i32>* %2, align 8, !tbaa !38 306 ret <2 x i32> %3 307 } 308 309 !39 = !{!"int3", !15} 310 define void @rsSetElementAtImpl_int3([1 x i32] %a.coerce, <3 x i32> %val, i32 %x, i32 %y, i32 %z) #1 { 311 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 16, i32 %x, i32 %y, i32 %z) #2 312 %2 = shufflevector <3 x i32> %val, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef> 313 %3 = bitcast i8* %1 to <4 x i32>* 314 store <4 x i32> %2, <4 x i32>* %3, align 16, !tbaa !39 315 ret void 316 } 317 318 define <3 x i32> @rsGetElementAtImpl_int3([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 319 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 16, i32 %x, i32 %y, i32 %z) #2 320 %2 = bitcast i8* %1 to <4 x i32>* 321 %3 = load <4 x i32>, <4 x i32>* %2, align 8, !tbaa !39 322 %4 = shufflevector <4 x i32> %3, <4 x i32> undef, <3 x i32> <i32 0, i32 1, i32 2> 323 ret <3 x i32> %4 324 } 325 326 !40 = !{!"int4", !15} 327 define void @rsSetElementAtImpl_int4([1 x i32] %a.coerce, <4 x i32> %val, i32 %x, i32 %y, i32 %z) #1 { 328 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 16, i32 %x, i32 %y, i32 %z) #2 329 %2 = bitcast i8* %1 to <4 x i32>* 330 store <4 x i32> %val, <4 x i32>* %2, align 16, !tbaa !40 331 ret void 332 } 333 334 define <4 x i32> @rsGetElementAtImpl_int4([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 335 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 16, i32 %x, i32 %y, i32 %z) #2 336 %2 = bitcast i8* %1 to <4 x i32>* 337 %3 = load <4 x i32>, <4 x i32>* %2, align 16, !tbaa !40 338 ret <4 x i32> %3 339 } 340 341 !41 = !{!"uint", !15} 342 define void @rsSetElementAtImpl_uint([1 x i32] %a.coerce, i32 %val, i32 %x, i32 %y, i32 %z) #1 { 343 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 4, i32 %x, i32 %y, i32 %z) #2 344 %2 = bitcast i8* %1 to i32* 345 store i32 %val, i32* %2, align 4, !tbaa !41 346 ret void 347 } 348 349 define i32 @rsGetElementAtImpl_uint([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 350 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 4, i32 %x, i32 %y, i32 %z) #2 351 %2 = bitcast i8* %1 to i32* 352 %3 = load i32, i32* %2, align 4, !tbaa !41 353 ret i32 %3 354 } 355 356 !42 = !{!"uint2", !15} 357 define void @rsSetElementAtImpl_uint2([1 x i32] %a.coerce, <2 x i32> %val, i32 %x, i32 %y, i32 %z) #1 { 358 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 8, i32 %x, i32 %y, i32 %z) #2 359 %2 = bitcast i8* %1 to <2 x i32>* 360 store <2 x i32> %val, <2 x i32>* %2, align 8, !tbaa !42 361 ret void 362 } 363 364 define <2 x i32> @rsGetElementAtImpl_uint2([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 365 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 8, i32 %x, i32 %y, i32 %z) #2 366 %2 = bitcast i8* %1 to <2 x i32>* 367 %3 = load <2 x i32>, <2 x i32>* %2, align 8, !tbaa !42 368 ret <2 x i32> %3 369 } 370 371 !43 = !{!"uint3", !15} 372 define void @rsSetElementAtImpl_uint3([1 x i32] %a.coerce, <3 x i32> %val, i32 %x, i32 %y, i32 %z) #1 { 373 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 16, i32 %x, i32 %y, i32 %z) #2 374 %2 = shufflevector <3 x i32> %val, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef> 375 %3 = bitcast i8* %1 to <4 x i32>* 376 store <4 x i32> %2, <4 x i32>* %3, align 16, !tbaa !43 377 ret void 378 } 379 380 define <3 x i32> @rsGetElementAtImpl_uint3([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 381 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 16, i32 %x, i32 %y, i32 %z) #2 382 %2 = bitcast i8* %1 to <4 x i32>* 383 %3 = load <4 x i32>, <4 x i32>* %2, align 8, !tbaa !43 384 %4 = shufflevector <4 x i32> %3, <4 x i32> undef, <3 x i32> <i32 0, i32 1, i32 2> 385 ret <3 x i32> %4 386 } 387 388 !44 = !{!"uint4", !15} 389 define void @rsSetElementAtImpl_uint4([1 x i32] %a.coerce, <4 x i32> %val, i32 %x, i32 %y, i32 %z) #1 { 390 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 16, i32 %x, i32 %y, i32 %z) #2 391 %2 = bitcast i8* %1 to <4 x i32>* 392 store <4 x i32> %val, <4 x i32>* %2, align 16, !tbaa !44 393 ret void 394 } 395 396 define <4 x i32> @rsGetElementAtImpl_uint4([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 397 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 16, i32 %x, i32 %y, i32 %z) #2 398 %2 = bitcast i8* %1 to <4 x i32>* 399 %3 = load <4 x i32>, <4 x i32>* %2, align 16, !tbaa !44 400 ret <4 x i32> %3 401 } 402 403 !45 = !{!"long", !15} 404 define void @rsSetElementAtImpl_long([1 x i32] %a.coerce, i64 %val, i32 %x, i32 %y, i32 %z) #1 { 405 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 8, i32 %x, i32 %y, i32 %z) #2 406 %2 = bitcast i8* %1 to i64* 407 store i64 %val, i64* %2, align 8, !tbaa !45 408 ret void 409 } 410 411 define i64 @rsGetElementAtImpl_long([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 412 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 8, i32 %x, i32 %y, i32 %z) #2 413 %2 = bitcast i8* %1 to i64* 414 %3 = load i64, i64* %2, align 8, !tbaa !45 415 ret i64 %3 416 } 417 418 !46 = !{!"long2", !15} 419 define void @rsSetElementAtImpl_long2([1 x i32] %a.coerce, <2 x i64> %val, i32 %x, i32 %y, i32 %z) #1 { 420 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 16, i32 %x, i32 %y, i32 %z) #2 421 %2 = bitcast i8* %1 to <2 x i64>* 422 store <2 x i64> %val, <2 x i64>* %2, align 16, !tbaa !46 423 ret void 424 } 425 426 define <2 x i64> @rsGetElementAtImpl_long2([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 427 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 16, i32 %x, i32 %y, i32 %z) #2 428 %2 = bitcast i8* %1 to <2 x i64>* 429 %3 = load <2 x i64>, <2 x i64>* %2, align 16, !tbaa !46 430 ret <2 x i64> %3 431 } 432 433 !47 = !{!"long3", !15} 434 define void @rsSetElementAtImpl_long3([1 x i32] %a.coerce, <3 x i64> %val, i32 %x, i32 %y, i32 %z) #1 { 435 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 32, i32 %x, i32 %y, i32 %z) #2 436 %2 = shufflevector <3 x i64> %val, <3 x i64> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef> 437 %3 = bitcast i8* %1 to <4 x i64>* 438 store <4 x i64> %2, <4 x i64>* %3, align 32, !tbaa !47 439 ret void 440 } 441 442 define void @rsGetElementAtImpl_long3(<3 x i64>* noalias nocapture sret %agg.result, [1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #1 { 443 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 32, i32 %x, i32 %y, i32 %z) #2 444 %2 = bitcast i8* %1 to <4 x i64>* 445 %3 = load <4 x i64>, <4 x i64>* %2, align 32 446 %4 = bitcast <3 x i64>* %agg.result to <4 x i64>* 447 store <4 x i64> %3, <4 x i64>* %4, align 32, !tbaa !47 448 ret void 449 } 450 451 !48 = !{!"long4", !15} 452 define void @rsSetElementAtImpl_long4([1 x i32] %a.coerce, <4 x i64> %val, i32 %x, i32 %y, i32 %z) #1 { 453 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 32, i32 %x, i32 %y, i32 %z) #2 454 %2 = bitcast i8* %1 to <4 x i64>* 455 store <4 x i64> %val, <4 x i64>* %2, align 32, !tbaa !48 456 ret void 457 } 458 459 define void @rsGetElementAtImpl_long4(<4 x i64>* noalias nocapture sret %agg.result, [1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #1 { 460 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 32, i32 %x, i32 %y, i32 %z) #2 461 %2 = bitcast i8* %1 to <4 x i64>* 462 %3 = load <4 x i64>, <4 x i64>* %2, align 32, !tbaa !15 463 store <4 x i64> %3, <4 x i64>* %agg.result, align 32, !tbaa !48 464 ret void 465 } 466 467 !49 = !{!"ulong", !15} 468 define void @rsSetElementAtImpl_ulong([1 x i32] %a.coerce, i64 %val, i32 %x, i32 %y, i32 %z) #1 { 469 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 8, i32 %x, i32 %y, i32 %z) #2 470 %2 = bitcast i8* %1 to i64* 471 store i64 %val, i64* %2, align 8, !tbaa !49 472 ret void 473 } 474 475 define i64 @rsGetElementAtImpl_ulong([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 476 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 8, i32 %x, i32 %y, i32 %z) #2 477 %2 = bitcast i8* %1 to i64* 478 %3 = load i64, i64* %2, align 8, !tbaa !49 479 ret i64 %3 480 } 481 482 !50 = !{!"ulong2", !15} 483 define void @rsSetElementAtImpl_ulong2([1 x i32] %a.coerce, <2 x i64> %val, i32 %x, i32 %y, i32 %z) #1 { 484 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 16, i32 %x, i32 %y, i32 %z) #2 485 %2 = bitcast i8* %1 to <2 x i64>* 486 store <2 x i64> %val, <2 x i64>* %2, align 16, !tbaa !50 487 ret void 488 } 489 490 define <2 x i64> @rsGetElementAtImpl_ulong2([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 491 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 16, i32 %x, i32 %y, i32 %z) #2 492 %2 = bitcast i8* %1 to <2 x i64>* 493 %3 = load <2 x i64>, <2 x i64>* %2, align 16, !tbaa !50 494 ret <2 x i64> %3 495 } 496 497 !51 = !{!"ulong3", !15} 498 define void @rsSetElementAtImpl_ulong3([1 x i32] %a.coerce, <3 x i64> %val, i32 %x, i32 %y, i32 %z) #1 { 499 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 32, i32 %x, i32 %y, i32 %z) #2 500 %2 = shufflevector <3 x i64> %val, <3 x i64> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef> 501 %3 = bitcast i8* %1 to <4 x i64>* 502 store <4 x i64> %2, <4 x i64>* %3, align 32, !tbaa !51 503 ret void 504 } 505 506 define void @rsGetElementAtImpl_ulong3(<3 x i64>* noalias nocapture sret %agg.result, [1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #1 { 507 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 32, i32 %x, i32 %y, i32 %z) #2 508 %2 = bitcast i8* %1 to <4 x i64>* 509 %3 = load <4 x i64>, <4 x i64>* %2, align 32 510 %4 = bitcast <3 x i64>* %agg.result to <4 x i64>* 511 store <4 x i64> %3, <4 x i64>* %4, align 32, !tbaa !51 512 ret void 513 } 514 515 !52 = !{!"ulong4", !15} 516 define void @rsSetElementAtImpl_ulong4([1 x i32] %a.coerce, <4 x i64> %val, i32 %x, i32 %y, i32 %z) #1 { 517 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 32, i32 %x, i32 %y, i32 %z) #2 518 %2 = bitcast i8* %1 to <4 x i64>* 519 store <4 x i64> %val, <4 x i64>* %2, align 32, !tbaa !52 520 ret void 521 } 522 523 define void @rsGetElementAtImpl_ulong4(<4 x i64>* noalias nocapture sret %agg.result, [1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #1 { 524 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 32, i32 %x, i32 %y, i32 %z) #2 525 %2 = bitcast i8* %1 to <4 x i64>* 526 %3 = load <4 x i64>, <4 x i64>* %2, align 32, !tbaa !15 527 store <4 x i64> %3, <4 x i64>* %agg.result, align 32, !tbaa !52 528 ret void 529 } 530 531 !53 = !{!"float", !15} 532 define void @rsSetElementAtImpl_float([1 x i32] %a.coerce, float %val, i32 %x, i32 %y, i32 %z) #1 { 533 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 4, i32 %x, i32 %y, i32 %z) #2 534 %2 = bitcast i8* %1 to float* 535 store float %val, float* %2, align 4, !tbaa !53 536 ret void 537 } 538 539 define float @rsGetElementAtImpl_float([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 540 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 4, i32 %x, i32 %y, i32 %z) #2 541 %2 = bitcast i8* %1 to float* 542 %3 = load float, float* %2, align 4, !tbaa !53 543 ret float %3 544 } 545 546 !54 = !{!"float2", !15} 547 define void @rsSetElementAtImpl_float2([1 x i32] %a.coerce, <2 x float> %val, i32 %x, i32 %y, i32 %z) #1 { 548 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 8, i32 %x, i32 %y, i32 %z) #2 549 %2 = bitcast i8* %1 to <2 x float>* 550 store <2 x float> %val, <2 x float>* %2, align 8, !tbaa !54 551 ret void 552 } 553 554 define <2 x float> @rsGetElementAtImpl_float2([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 555 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 8, i32 %x, i32 %y, i32 %z) #2 556 %2 = bitcast i8* %1 to <2 x float>* 557 %3 = load <2 x float>, <2 x float>* %2, align 8, !tbaa !54 558 ret <2 x float> %3 559 } 560 561 !55 = !{!"float3", !15} 562 define void @rsSetElementAtImpl_float3([1 x i32] %a.coerce, <3 x float> %val, i32 %x, i32 %y, i32 %z) #1 { 563 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 16, i32 %x, i32 %y, i32 %z) #2 564 %2 = shufflevector <3 x float> %val, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef> 565 %3 = bitcast i8* %1 to <4 x float>* 566 store <4 x float> %2, <4 x float>* %3, align 16, !tbaa !55 567 ret void 568 } 569 570 define <3 x float> @rsGetElementAtImpl_float3([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 571 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 16, i32 %x, i32 %y, i32 %z) #2 572 %2 = bitcast i8* %1 to <4 x float>* 573 %3 = load <4 x float>, <4 x float>* %2, align 8, !tbaa !55 574 %4 = shufflevector <4 x float> %3, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2> 575 ret <3 x float> %4 576 } 577 578 !56 = !{!"float4", !15} 579 define void @rsSetElementAtImpl_float4([1 x i32] %a.coerce, <4 x float> %val, i32 %x, i32 %y, i32 %z) #1 { 580 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 16, i32 %x, i32 %y, i32 %z) #2 581 %2 = bitcast i8* %1 to <4 x float>* 582 store <4 x float> %val, <4 x float>* %2, align 16, !tbaa !56 583 ret void 584 } 585 586 define <4 x float> @rsGetElementAtImpl_float4([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 587 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 16, i32 %x, i32 %y, i32 %z) #2 588 %2 = bitcast i8* %1 to <4 x float>* 589 %3 = load <4 x float>, <4 x float>* %2, align 16, !tbaa !56 590 ret <4 x float> %3 591 } 592 593 !57 = !{!"double", !15} 594 define void @rsSetElementAtImpl_double([1 x i32] %a.coerce, double %val, i32 %x, i32 %y, i32 %z) #1 { 595 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 8, i32 %x, i32 %y, i32 %z) #2 596 %2 = bitcast i8* %1 to double* 597 store double %val, double* %2, align 8, !tbaa !57 598 ret void 599 } 600 601 define double @rsGetElementAtImpl_double([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 602 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 8, i32 %x, i32 %y, i32 %z) #2 603 %2 = bitcast i8* %1 to double* 604 %3 = load double, double* %2, align 8, !tbaa !57 605 ret double %3 606 } 607 608 !58 = !{!"double2", !15} 609 define void @rsSetElementAtImpl_double2([1 x i32] %a.coerce, <2 x double> %val, i32 %x, i32 %y, i32 %z) #1 { 610 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 16, i32 %x, i32 %y, i32 %z) #2 611 %2 = bitcast i8* %1 to <2 x double>* 612 store <2 x double> %val, <2 x double>* %2, align 16, !tbaa !58 613 ret void 614 } 615 616 define <2 x double> @rsGetElementAtImpl_double2([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 617 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 16, i32 %x, i32 %y, i32 %z) #2 618 %2 = bitcast i8* %1 to <2 x double>* 619 %3 = load <2 x double>, <2 x double>* %2, align 16, !tbaa !58 620 ret <2 x double> %3 621 } 622 623 !59 = !{!"double3", !15} 624 define void @rsSetElementAtImpl_double3([1 x i32] %a.coerce, <3 x double> %val, i32 %x, i32 %y, i32 %z) #1 { 625 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 32, i32 %x, i32 %y, i32 %z) #2 626 %2 = shufflevector <3 x double> %val, <3 x double> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef> 627 %3 = bitcast i8* %1 to <4 x double>* 628 store <4 x double> %2, <4 x double>* %3, align 32, !tbaa !59 629 ret void 630 } 631 632 633 define void @rsGetElementAtImpl_double3(<3 x double>* noalias nocapture sret %agg.result, [1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #1 { 634 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 32, i32 %x, i32 %y, i32 %z) #2 635 %2 = bitcast i8* %1 to <4 x double>* 636 %3 = load <4 x double>, <4 x double>* %2, align 32 637 %4 = bitcast <3 x double>* %agg.result to <4 x double>* 638 store <4 x double> %3, <4 x double>* %4, align 32, !tbaa !59 639 ret void 640 } 641 642 !60 = !{!"double4", !15} 643 define void @rsSetElementAtImpl_double4([1 x i32] %a.coerce, <4 x double> %val, i32 %x, i32 %y, i32 %z) #1 { 644 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 32, i32 %x, i32 %y, i32 %z) #2 645 %2 = bitcast i8* %1 to <4 x double>* 646 store <4 x double> %val, <4 x double>* %2, align 32, !tbaa !60 647 ret void 648 } 649 define void @rsGetElementAtImpl_double4(<4 x double>* noalias nocapture sret %agg.result, [1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #1 { 650 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 32, i32 %x, i32 %y, i32 %z) #2 651 %2 = bitcast i8* %1 to <4 x double>* 652 %3 = load <4 x double>, <4 x double>* %2, align 32, !tbaa !15 653 store <4 x double> %3, <4 x double>* %agg.result, align 32, !tbaa !60 654 ret void 655 } 656 657 !61 = !{!"half", !15} 658 define void @rsSetElementAtImpl_half([1 x i32] %a.coerce, half %val, i32 %x, i32 %y, i32 %z) #1 { 659 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 2, i32 %x, i32 %y, i32 %z) #2 660 %2 = bitcast i8* %1 to half* 661 store half %val, half* %2, align 2, !tbaa !61 662 ret void 663 } 664 665 define half @rsGetElementAtImpl_half([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 666 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 2, i32 %x, i32 %y, i32 %z) #2 667 %2 = bitcast i8* %1 to half* 668 %3 = load half, half* %2, align 2, !tbaa !61 669 ret half %3 670 } 671 672 !62 = !{!"half2", !15} 673 define void @rsSetElementAtImpl_half2([1 x i32] %a.coerce, <2 x half> %val, i32 %x, i32 %y, i32 %z) #1 { 674 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 4, i32 %x, i32 %y, i32 %z) #2 675 %2 = bitcast i8* %1 to <2 x half>* 676 store <2 x half> %val, <2 x half>* %2, align 4, !tbaa !62 677 ret void 678 } 679 680 define <2 x half> @rsGetElementAtImpl_half2([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 681 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 4, i32 %x, i32 %y, i32 %z) #2 682 %2 = bitcast i8* %1 to <2 x half>* 683 %3 = load <2 x half>, <2 x half>* %2, align 4, !tbaa !62 684 ret <2 x half> %3 685 } 686 687 !63 = !{!"half3", !15} 688 define void @rsSetElementAtImpl_half3([1 x i32] %a.coerce, <3 x half> %val, i32 %x, i32 %y, i32 %z) #1 { 689 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 8, i32 %x, i32 %y, i32 %z) #2 690 %2 = shufflevector <3 x half> %val, <3 x half> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef> 691 %3 = bitcast i8* %1 to <4 x half>* 692 store <4 x half> %2, <4 x half>* %3, align 8, !tbaa !63 693 ret void 694 } 695 696 define <3 x half> @rsGetElementAtImpl_half3([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #1 { 697 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 8, i32 %x, i32 %y, i32 %z) #2 698 %2 = bitcast i8* %1 to <4 x half>* 699 %3 = load <4 x half>, <4 x half>* %2, align 8, !tbaa !63 700 %4 = shufflevector <4 x half> %3, <4 x half> undef, <3 x i32> <i32 0, i32 1, i32 2> 701 ret <3 x half> %4 702 } 703 704 !64 = !{!"half4", !15} 705 define void @rsSetElementAtImpl_half4([1 x i32] %a.coerce, <4 x half> %val, i32 %x, i32 %y, i32 %z) #1 { 706 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 8, i32 %x, i32 %y, i32 %z) #2 707 %2 = bitcast i8* %1 to <4 x half>* 708 store <4 x half> %val, <4 x half>* %2, align 8, !tbaa !64 709 ret void 710 } 711 712 define <4 x half> @rsGetElementAtImpl_half4([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 713 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 8, i32 %x, i32 %y, i32 %z) #2 714 %2 = bitcast i8* %1 to <4 x half>* 715 %3 = load <4 x half>, <4 x half>* %2, align 8, !tbaa !64 716 ret <4 x half> %3 717 } 718 719 define void @__rsAllocationVLoadXImpl_long4(<4 x i64>* noalias nocapture sret %agg.result, [1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #1 { 720 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 721 %2 = bitcast i8* %1 to <4 x i64>* 722 %3 = load <4 x i64>, <4 x i64>* %2, align 8 723 store <4 x i64> %3, <4 x i64>* %agg.result, align 32, !tbaa !52 724 ret void 725 } 726 define void @__rsAllocationVLoadXImpl_long3(<3 x i64>* noalias nocapture sret %agg.result, [1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #1 { 727 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 728 %2 = bitcast i8* %1 to <4 x i64>* 729 %3 = load <4 x i64>, <4 x i64>* %2, align 8 730 %4 = bitcast <3 x i64>* %agg.result to <4 x i64>* 731 store <4 x i64> %3, <4 x i64>* %4, align 32, !tbaa !47 732 ret void 733 } 734 define <2 x i64> @__rsAllocationVLoadXImpl_long2([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 735 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 736 %2 = bitcast i8* %1 to <2 x i64>* 737 %3 = load <2 x i64>, <2 x i64>* %2, align 8 738 ret <2 x i64> %3 739 } 740 741 define void @__rsAllocationVLoadXImpl_ulong4(<4 x i64>* noalias nocapture sret %agg.result, [1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #1 { 742 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 743 %2 = bitcast i8* %1 to <4 x i64>* 744 %3 = load <4 x i64>, <4 x i64>* %2, align 8 745 store <4 x i64> %3, <4 x i64>* %agg.result, align 32, !tbaa !48 746 ret void 747 } 748 define void @__rsAllocationVLoadXImpl_ulong3(<3 x i64>* noalias nocapture sret %agg.result, [1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #1 { 749 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 750 %2 = bitcast i8* %1 to <4 x i64>* 751 %3 = load <4 x i64>, <4 x i64>* %2, align 8 752 %4 = bitcast <3 x i64>* %agg.result to <4 x i64>* 753 store <4 x i64> %3, <4 x i64>* %4, align 32, !tbaa !51 754 ret void 755 } 756 define <2 x i64> @__rsAllocationVLoadXImpl_ulong2([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 757 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 758 %2 = bitcast i8* %1 to <2 x i64>* 759 %3 = load <2 x i64>, <2 x i64>* %2, align 8 760 ret <2 x i64> %3 761 } 762 763 define <4 x i32> @__rsAllocationVLoadXImpl_int4([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 764 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 765 %2 = bitcast i8* %1 to <4 x i32>* 766 %3 = load <4 x i32>, <4 x i32>* %2, align 4 767 ret <4 x i32> %3 768 } 769 define <3 x i32> @__rsAllocationVLoadXImpl_int3([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 770 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 771 %2 = bitcast i8* %1 to <3 x i32>* 772 %3 = load <3 x i32>, <3 x i32>* %2, align 4 773 ret <3 x i32> %3 774 } 775 define <2 x i32> @__rsAllocationVLoadXImpl_int2([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 776 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 777 %2 = bitcast i8* %1 to <2 x i32>* 778 %3 = load <2 x i32>, <2 x i32>* %2, align 4 779 ret <2 x i32> %3 780 } 781 782 define <4 x i32> @__rsAllocationVLoadXImpl_uint4([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 783 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 784 %2 = bitcast i8* %1 to <4 x i32>* 785 %3 = load <4 x i32>, <4 x i32>* %2, align 4 786 ret <4 x i32> %3 787 } 788 define <3 x i32> @__rsAllocationVLoadXImpl_uint3([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 789 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 790 %2 = bitcast i8* %1 to <3 x i32>* 791 %3 = load <3 x i32>, <3 x i32>* %2, align 4 792 ret <3 x i32> %3 793 } 794 define <2 x i32> @__rsAllocationVLoadXImpl_uint2([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 795 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 796 %2 = bitcast i8* %1 to <2 x i32>* 797 %3 = load <2 x i32>, <2 x i32>* %2, align 4 798 ret <2 x i32> %3 799 } 800 801 define <4 x i16> @__rsAllocationVLoadXImpl_short4([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 802 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 803 %2 = bitcast i8* %1 to <4 x i16>* 804 %3 = load <4 x i16>, <4 x i16>* %2, align 2 805 ret <4 x i16> %3 806 } 807 define <3 x i16> @__rsAllocationVLoadXImpl_short3([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 808 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 809 %2 = bitcast i8* %1 to <3 x i16>* 810 %3 = load <3 x i16>, <3 x i16>* %2, align 2 811 ret <3 x i16> %3 812 } 813 define <2 x i16> @__rsAllocationVLoadXImpl_short2([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 814 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 815 %2 = bitcast i8* %1 to <2 x i16>* 816 %3 = load <2 x i16>, <2 x i16>* %2, align 2 817 ret <2 x i16> %3 818 } 819 820 define <4 x i16> @__rsAllocationVLoadXImpl_ushort4([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 821 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 822 %2 = bitcast i8* %1 to <4 x i16>* 823 %3 = load <4 x i16>, <4 x i16>* %2, align 2 824 ret <4 x i16> %3 825 } 826 define <3 x i16> @__rsAllocationVLoadXImpl_ushort3([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 827 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 828 %2 = bitcast i8* %1 to <3 x i16>* 829 %3 = load <3 x i16>, <3 x i16>* %2, align 2 830 ret <3 x i16> %3 831 } 832 define <2 x i16> @__rsAllocationVLoadXImpl_ushort2([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 833 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 834 %2 = bitcast i8* %1 to <2 x i16>* 835 %3 = load <2 x i16>, <2 x i16>* %2, align 2 836 ret <2 x i16> %3 837 } 838 839 define <4 x i8> @__rsAllocationVLoadXImpl_char4([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 840 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 841 %2 = bitcast i8* %1 to <4 x i8>* 842 %3 = load <4 x i8>, <4 x i8>* %2, align 1 843 ret <4 x i8> %3 844 } 845 define <3 x i8> @__rsAllocationVLoadXImpl_char3([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 846 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 847 %2 = bitcast i8* %1 to <3 x i8>* 848 %3 = load <3 x i8>, <3 x i8>* %2, align 1 849 ret <3 x i8> %3 850 } 851 define <2 x i8> @__rsAllocationVLoadXImpl_char2([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 852 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 853 %2 = bitcast i8* %1 to <2 x i8>* 854 %3 = load <2 x i8>, <2 x i8>* %2, align 1 855 ret <2 x i8> %3 856 } 857 858 define <4 x i8> @__rsAllocationVLoadXImpl_uchar4([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 859 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 860 %2 = bitcast i8* %1 to <4 x i8>* 861 %3 = load <4 x i8>, <4 x i8>* %2, align 1 862 ret <4 x i8> %3 863 } 864 define <3 x i8> @__rsAllocationVLoadXImpl_uchar3([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 865 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 866 %2 = bitcast i8* %1 to <3 x i8>* 867 %3 = load <3 x i8>, <3 x i8>* %2, align 1 868 ret <3 x i8> %3 869 } 870 define <2 x i8> @__rsAllocationVLoadXImpl_uchar2([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 871 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 872 %2 = bitcast i8* %1 to <2 x i8>* 873 %3 = load <2 x i8>, <2 x i8>* %2, align 1 874 ret <2 x i8> %3 875 } 876 877 define <4 x float> @__rsAllocationVLoadXImpl_float4([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 878 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 879 %2 = bitcast i8* %1 to <4 x float>* 880 %3 = load <4 x float>, <4 x float>* %2, align 4 881 ret <4 x float> %3 882 } 883 define <3 x float> @__rsAllocationVLoadXImpl_float3([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 884 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 885 %2 = bitcast i8* %1 to <3 x float>* 886 %3 = load <3 x float>, <3 x float>* %2, align 4 887 ret <3 x float> %3 888 } 889 define <2 x float> @__rsAllocationVLoadXImpl_float2([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 890 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 891 %2 = bitcast i8* %1 to <2 x float>* 892 %3 = load <2 x float>, <2 x float>* %2, align 4 893 ret <2 x float> %3 894 } 895 896 define void @__rsAllocationVLoadXImpl_double4(<4 x double>* noalias nocapture sret %agg.result, [1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #1 { 897 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 898 %2 = bitcast i8* %1 to <4 x double>* 899 %3 = load <4 x double>, <4 x double>* %2, align 8 900 store <4 x double> %3, <4 x double>* %agg.result, align 32, !tbaa !60 901 ret void 902 } 903 define void @__rsAllocationVLoadXImpl_double3(<3 x double>* noalias nocapture sret %agg.result, [1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #1 { 904 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 905 %2 = bitcast i8* %1 to <4 x double>* 906 %3 = load <4 x double>, <4 x double>* %2, align 8 907 %4 = bitcast <3 x double>* %agg.result to <4 x double>* 908 store <4 x double> %3, <4 x double>* %4, align 32, !tbaa !59 909 ret void 910 } 911 define <2 x double> @__rsAllocationVLoadXImpl_double2([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 912 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 913 %2 = bitcast i8* %1 to <2 x double>* 914 %3 = load <2 x double>, <2 x double>* %2, align 8 915 ret <2 x double> %3 916 } 917 918 919 define void @__rsAllocationVStoreXImpl_long4([1 x i32] %a.coerce, <4 x i64> %val, i32 %x, i32 %y, i32 %z) #1 { 920 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 921 %2 = bitcast i8* %1 to <4 x i64>* 922 store <4 x i64> %val, <4 x i64>* %2, align 8 923 ret void 924 } 925 define void @__rsAllocationVStoreXImpl_long3([1 x i32] %a.coerce, <3 x i64> %val, i32 %x, i32 %y, i32 %z) #1 { 926 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 927 %2 = bitcast i8* %1 to <3 x i64>* 928 store <3 x i64> %val, <3 x i64>* %2, align 8 929 ret void 930 } 931 define void @__rsAllocationVStoreXImpl_long2([1 x i32] %a.coerce, <2 x i64> %val, i32 %x, i32 %y, i32 %z) #1 { 932 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 933 %2 = bitcast i8* %1 to <2 x i64>* 934 store <2 x i64> %val, <2 x i64>* %2, align 8 935 ret void 936 } 937 938 define void @__rsAllocationVStoreXImpl_ulong4([1 x i32] %a.coerce, <4 x i64> %val, i32 %x, i32 %y, i32 %z) #1 { 939 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 940 %2 = bitcast i8* %1 to <4 x i64>* 941 store <4 x i64> %val, <4 x i64>* %2, align 8 942 ret void 943 } 944 define void @__rsAllocationVStoreXImpl_ulong3([1 x i32] %a.coerce, <3 x i64> %val, i32 %x, i32 %y, i32 %z) #1 { 945 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 946 %2 = bitcast i8* %1 to <3 x i64>* 947 store <3 x i64> %val, <3 x i64>* %2, align 8 948 ret void 949 } 950 define void @__rsAllocationVStoreXImpl_ulong2([1 x i32] %a.coerce, <2 x i64> %val, i32 %x, i32 %y, i32 %z) #1 { 951 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 952 %2 = bitcast i8* %1 to <2 x i64>* 953 store <2 x i64> %val, <2 x i64>* %2, align 8 954 ret void 955 } 956 957 define void @__rsAllocationVStoreXImpl_int4([1 x i32] %a.coerce, <4 x i32> %val, i32 %x, i32 %y, i32 %z) #1 { 958 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 959 %2 = bitcast i8* %1 to <4 x i32>* 960 store <4 x i32> %val, <4 x i32>* %2, align 4 961 ret void 962 } 963 define void @__rsAllocationVStoreXImpl_int3([1 x i32] %a.coerce, <3 x i32> %val, i32 %x, i32 %y, i32 %z) #1 { 964 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 965 %2 = bitcast i8* %1 to <3 x i32>* 966 store <3 x i32> %val, <3 x i32>* %2, align 4 967 ret void 968 } 969 define void @__rsAllocationVStoreXImpl_int2([1 x i32] %a.coerce, <2 x i32> %val, i32 %x, i32 %y, i32 %z) #1 { 970 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 971 %2 = bitcast i8* %1 to <2 x i32>* 972 store <2 x i32> %val, <2 x i32>* %2, align 4 973 ret void 974 } 975 976 define void @__rsAllocationVStoreXImpl_uint4([1 x i32] %a.coerce, <4 x i32> %val, i32 %x, i32 %y, i32 %z) #1 { 977 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 978 %2 = bitcast i8* %1 to <4 x i32>* 979 store <4 x i32> %val, <4 x i32>* %2, align 4 980 ret void 981 } 982 define void @__rsAllocationVStoreXImpl_uint3([1 x i32] %a.coerce, <3 x i32> %val, i32 %x, i32 %y, i32 %z) #1 { 983 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 984 %2 = bitcast i8* %1 to <3 x i32>* 985 store <3 x i32> %val, <3 x i32>* %2, align 4 986 ret void 987 } 988 define void @__rsAllocationVStoreXImpl_uint2([1 x i32] %a.coerce, <2 x i32> %val, i32 %x, i32 %y, i32 %z) #1 { 989 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 990 %2 = bitcast i8* %1 to <2 x i32>* 991 store <2 x i32> %val, <2 x i32>* %2, align 4 992 ret void 993 } 994 995 define void @__rsAllocationVStoreXImpl_short4([1 x i32] %a.coerce, <4 x i16> %val, i32 %x, i32 %y, i32 %z) #1 { 996 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 997 %2 = bitcast i8* %1 to <4 x i16>* 998 store <4 x i16> %val, <4 x i16>* %2, align 2 999 ret void 1000 } 1001 define void @__rsAllocationVStoreXImpl_short3([1 x i32] %a.coerce, <3 x i16> %val, i32 %x, i32 %y, i32 %z) #1 { 1002 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 1003 %2 = bitcast i8* %1 to <3 x i16>* 1004 store <3 x i16> %val, <3 x i16>* %2, align 2 1005 ret void 1006 } 1007 define void @__rsAllocationVStoreXImpl_short2([1 x i32] %a.coerce, <2 x i16> %val, i32 %x, i32 %y, i32 %z) #1 { 1008 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 1009 %2 = bitcast i8* %1 to <2 x i16>* 1010 store <2 x i16> %val, <2 x i16>* %2, align 2 1011 ret void 1012 } 1013 1014 define void @__rsAllocationVStoreXImpl_ushort4([1 x i32] %a.coerce, <4 x i16> %val, i32 %x, i32 %y, i32 %z) #1 { 1015 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 1016 %2 = bitcast i8* %1 to <4 x i16>* 1017 store <4 x i16> %val, <4 x i16>* %2, align 2 1018 ret void 1019 } 1020 define void @__rsAllocationVStoreXImpl_ushort3([1 x i32] %a.coerce, <3 x i16> %val, i32 %x, i32 %y, i32 %z) #1 { 1021 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 1022 %2 = bitcast i8* %1 to <3 x i16>* 1023 store <3 x i16> %val, <3 x i16>* %2, align 2 1024 ret void 1025 } 1026 define void @__rsAllocationVStoreXImpl_ushort2([1 x i32] %a.coerce, <2 x i16> %val, i32 %x, i32 %y, i32 %z) #1 { 1027 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 1028 %2 = bitcast i8* %1 to <2 x i16>* 1029 store <2 x i16> %val, <2 x i16>* %2, align 2 1030 ret void 1031 } 1032 1033 define void @__rsAllocationVStoreXImpl_char4([1 x i32] %a.coerce, <4 x i8> %val, i32 %x, i32 %y, i32 %z) #1 { 1034 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 1035 %2 = bitcast i8* %1 to <4 x i8>* 1036 store <4 x i8> %val, <4 x i8>* %2, align 1 1037 ret void 1038 } 1039 define void @__rsAllocationVStoreXImpl_char3([1 x i32] %a.coerce, <3 x i8> %val, i32 %x, i32 %y, i32 %z) #1 { 1040 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 1041 %2 = bitcast i8* %1 to <3 x i8>* 1042 store <3 x i8> %val, <3 x i8>* %2, align 1 1043 ret void 1044 } 1045 define void @__rsAllocationVStoreXImpl_char2([1 x i32] %a.coerce, <2 x i8> %val, i32 %x, i32 %y, i32 %z) #1 { 1046 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 1047 %2 = bitcast i8* %1 to <2 x i8>* 1048 store <2 x i8> %val, <2 x i8>* %2, align 1 1049 ret void 1050 } 1051 1052 define void @__rsAllocationVStoreXImpl_uchar4([1 x i32] %a.coerce, <4 x i8> %val, i32 %x, i32 %y, i32 %z) #1 { 1053 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 1054 %2 = bitcast i8* %1 to <4 x i8>* 1055 store <4 x i8> %val, <4 x i8>* %2, align 1 1056 ret void 1057 } 1058 define void @__rsAllocationVStoreXImpl_uchar3([1 x i32] %a.coerce, <3 x i8> %val, i32 %x, i32 %y, i32 %z) #1 { 1059 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 1060 %2 = bitcast i8* %1 to <3 x i8>* 1061 store <3 x i8> %val, <3 x i8>* %2, align 1 1062 ret void 1063 } 1064 define void @__rsAllocationVStoreXImpl_uchar2([1 x i32] %a.coerce, <2 x i8> %val, i32 %x, i32 %y, i32 %z) #1 { 1065 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 1066 %2 = bitcast i8* %1 to <2 x i8>* 1067 store <2 x i8> %val, <2 x i8>* %2, align 1 1068 ret void 1069 } 1070 1071 define void @__rsAllocationVStoreXImpl_float4([1 x i32] %a.coerce, <4 x float> %val, i32 %x, i32 %y, i32 %z) #1 { 1072 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 1073 %2 = bitcast i8* %1 to <4 x float>* 1074 store <4 x float> %val, <4 x float>* %2, align 4 1075 ret void 1076 } 1077 define void @__rsAllocationVStoreXImpl_float3([1 x i32] %a.coerce, <3 x float> %val, i32 %x, i32 %y, i32 %z) #1 { 1078 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 1079 %2 = bitcast i8* %1 to <3 x float>* 1080 store <3 x float> %val, <3 x float>* %2, align 4 1081 ret void 1082 } 1083 define void @__rsAllocationVStoreXImpl_float2([1 x i32] %a.coerce, <2 x float> %val, i32 %x, i32 %y, i32 %z) #1 { 1084 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 1085 %2 = bitcast i8* %1 to <2 x float>* 1086 store <2 x float> %val, <2 x float>* %2, align 4 1087 ret void 1088 } 1089 1090 define void @__rsAllocationVStoreXImpl_double4([1 x i32] %a.coerce, <4 x double> %val, i32 %x, i32 %y, i32 %z) #1 { 1091 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 1092 %2 = bitcast i8* %1 to <4 x double>* 1093 store <4 x double> %val, <4 x double>* %2, align 8 1094 ret void 1095 } 1096 define void @__rsAllocationVStoreXImpl_double3([1 x i32] %a.coerce, <3 x double> %val, i32 %x, i32 %y, i32 %z) #1 { 1097 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 1098 %2 = bitcast i8* %1 to <3 x double>* 1099 store <3 x double> %val, <3 x double>* %2, align 8 1100 ret void 1101 } 1102 define void @__rsAllocationVStoreXImpl_double2([1 x i32] %a.coerce, <2 x double> %val, i32 %x, i32 %y, i32 %z) #1 { 1103 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 1104 %2 = bitcast i8* %1 to <2 x double>* 1105 store <2 x double> %val, <2 x double>* %2, align 8 1106 ret void 1107 } 1108 1109 1110 attributes #0 = { nounwind readonly "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } 1111 attributes #1 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } 1112 attributes #2 = { nobuiltin } 1113 1114
