1 /* 2 * Copyright (C) 2010-2014 NXP Semiconductors 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 #ifndef _PHNXPNCIHAL_H_ 17 #define _PHNXPNCIHAL_H_ 18 19 #include <hardware/nfc.h> 20 #include <phNxpNciHal_utils.h> 21 #include "NxpNfcCapability.h" 22 23 /********************* Definitions and structures *****************************/ 24 #define MAX_RETRY_COUNT 5 25 #define NCI_MAX_DATA_LEN 300 26 #define NCI_POLL_DURATION 500 27 #define HAL_NFC_ENABLE_I2C_FRAGMENTATION_EVT 0x07 28 #undef P2P_PRIO_LOGIC_HAL_IMP 29 #define NCI_VERSION_2_0 0x20 30 #define NCI_VERSION_1_1 0x11 31 #define NCI_VERSION_1_0 0x10 32 #define NCI_VERSION_UNKNOWN 0x00 33 typedef void(phNxpNciHal_control_granted_callback_t)(); 34 35 /*ROM CODE VERSION FW*/ 36 #define FW_MOBILE_ROM_VERSION_PN551 0x10 37 #define FW_MOBILE_ROM_VERSION_PN553 0x11 38 #define FW_MOBILE_ROM_VERSION_PN557 0x12 39 /* NCI Data */ 40 41 #define NCI_MT_CMD 0x20 42 #define NCI_MT_RSP 0x40 43 #define NCI_MT_NTF 0x60 44 45 #define CORE_RESET_TRIGGER_TYPE_CORE_RESET_CMD_RECEIVED 0x02 46 #define CORE_RESET_TRIGGER_TYPE_POWERED_ON 0x01 47 #define NCI_MSG_CORE_RESET 0x00 48 #define NCI_MSG_CORE_INIT 0x01 49 #define NCI_MT_MASK 0xE0 50 #define NCI_OID_MASK 0x3F 51 52 #define NXP_MAX_CONFIG_STRING_LEN 260 53 54 typedef struct nci_data { 55 uint16_t len; 56 uint8_t p_data[NCI_MAX_DATA_LEN]; 57 } nci_data_t; 58 59 typedef enum { 60 HAL_STATUS_CLOSE = 0, 61 HAL_STATUS_OPEN, 62 HAL_STATUS_MIN_OPEN 63 } phNxpNci_HalStatus; 64 65 typedef enum { 66 GPIO_UNKNOWN = 0x00, 67 GPIO_STORE = 0x01, 68 GPIO_STORE_DONE = 0x02, 69 GPIO_RESTORE = 0x10, 70 GPIO_RESTORE_DONE = 0x20, 71 GPIO_CLEAR = 0xFF 72 } phNxpNciHal_GpioInfoState; 73 74 typedef struct phNxpNciGpioInfo { 75 phNxpNciHal_GpioInfoState state; 76 uint8_t values[2]; 77 } phNxpNciGpioInfo_t; 78 79 /* Macros to enable and disable extensions */ 80 #define HAL_ENABLE_EXT() (nxpncihal_ctrl.hal_ext_enabled = 1) 81 #define HAL_DISABLE_EXT() (nxpncihal_ctrl.hal_ext_enabled = 0) 82 typedef struct phNxpNciInfo { 83 uint8_t nci_version; 84 bool_t wait_for_ntf; 85 } phNxpNciInfo_t; 86 /* NCI Control structure */ 87 typedef struct phNxpNciHal_Control { 88 phNxpNci_HalStatus halStatus; /* Indicate if hal is open or closed */ 89 pthread_t client_thread; /* Integration thread handle */ 90 uint8_t thread_running; /* Thread running if set to 1, else set to 0 */ 91 phLibNfc_sConfig_t gDrvCfg; /* Driver config data */ 92 93 /* Rx data */ 94 uint8_t* p_rx_data; 95 uint16_t rx_data_len; 96 97 /* Rx data */ 98 uint8_t* p_rx_ese_data; 99 uint16_t rx_ese_data_len; 100 101 /* libnfc-nci callbacks */ 102 nfc_stack_callback_t* p_nfc_stack_cback; 103 nfc_stack_data_callback_t* p_nfc_stack_data_cback; 104 105 /* control granted callback */ 106 phNxpNciHal_control_granted_callback_t* p_control_granted_cback; 107 108 /* HAL open status */ 109 bool_t hal_open_status; 110 111 /* HAL extensions */ 112 uint8_t hal_ext_enabled; 113 114 /* Waiting semaphore */ 115 phNxpNciHal_Sem_t ext_cb_data; 116 sem_t syncSpiNfc; 117 118 uint16_t cmd_len; 119 uint8_t p_cmd_data[NCI_MAX_DATA_LEN]; 120 uint16_t rsp_len; 121 uint8_t p_rsp_data[NCI_MAX_DATA_LEN]; 122 123 /* retry count used to force download */ 124 uint16_t retry_cnt; 125 uint8_t read_retry_cnt; 126 phNxpNciInfo_t nci_info; 127 128 /* to store and restore gpio values */ 129 phNxpNciGpioInfo_t phNxpNciGpioInfo; 130 bool bIsForceFwDwnld; 131 } phNxpNciHal_Control_t; 132 133 typedef struct phNxpNciClock { 134 bool_t isClockSet; 135 uint8_t p_rx_data[20]; 136 bool_t issetConfig; 137 } phNxpNciClock_t; 138 139 typedef struct phNxpNciRfSetting { 140 bool_t isGetRfSetting; 141 uint8_t p_rx_data[20]; 142 } phNxpNciRfSetting_t; 143 144 typedef struct phNxpNciMwEepromArea { 145 bool_t isGetEepromArea; 146 uint8_t p_rx_data[32]; 147 } phNxpNciMwEepromArea_t; 148 149 typedef enum { 150 NFC_FORUM_PROFILE, 151 EMV_CO_PROFILE, 152 INVALID_PROFILe 153 } phNxpNciProfile_t; 154 /* NXP Poll Profile control structure */ 155 typedef struct phNxpNciProfile_Control { 156 phNxpNciProfile_t profile_type; 157 uint8_t bClkSrcVal; /* Holds the System clock source read from config file */ 158 uint8_t 159 bClkFreqVal; /* Holds the System clock frequency read from config file */ 160 uint8_t bTimeout; /* Holds the Timeout Value */ 161 } phNxpNciProfile_Control_t; 162 163 /* Internal messages to handle callbacks */ 164 #define NCI_HAL_OPEN_CPLT_MSG 0x411 165 #define NCI_HAL_CLOSE_CPLT_MSG 0x412 166 #define NCI_HAL_POST_INIT_CPLT_MSG 0x413 167 #define NCI_HAL_PRE_DISCOVER_CPLT_MSG 0x414 168 #define NCI_HAL_ERROR_MSG 0x415 169 #define NCI_HAL_HCI_NETWORK_RESET_MSG 0x416 170 #define NCI_HAL_RX_MSG 0xF01 171 172 #define NCIHAL_CMD_CODE_LEN_BYTE_OFFSET (2U) 173 #define NCIHAL_CMD_CODE_BYTE_LEN (3U) 174 175 /******************** NCI HAL exposed functions *******************************/ 176 int phNxpNciHal_check_ncicmd_write_window(uint16_t cmd_len, uint8_t* p_cmd); 177 void phNxpNciHal_request_control(void); 178 void phNxpNciHal_release_control(void); 179 int phNxpNciHal_write_unlocked(uint16_t data_len, const uint8_t* p_data); 180 /******************************************************************************* 181 ** 182 ** Function phNxpNciHal_configFeatureList 183 ** 184 ** Description Configures the featureList based on chip type 185 186 ** Returns none 187 *******************************************************************************/ 188 void phNxpNciHal_configFeatureList(uint8_t* init_rsp, uint16_t rsp_len); 189 #endif /* _PHNXPNCIHAL_H_ */ 190
