1 /* 2 * Copyright 2012 The Android Open Source Project 3 * Copyright (c) 2013, The Linux Foundation. All rights reserved. 4 * Not a Contribution. 5 * 6 * Licensed under the Apache License, Version 2.0 (the "License"); 7 * you may not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * http://www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an "AS IS" BASIS, 14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 */ 18 #ifndef HW_AR3K_H 19 #define HW_AR3K_H 20 21 #include <sys/socket.h> 22 23 /****************************************************************************** 24 ** Constants & Macros 25 ******************************************************************************/ 26 #define MAX_CNT_RETRY 100 27 28 #define HCI_MAX_CMD_SIZE 260 29 #define HCI_MAX_EVENT_SIZE 260 30 #define HCI_CHG_BAUD_CMD_OCF 0x0C 31 #define HCI_VENDOR_CMD_OGF 0x3F 32 #define WRITE_BDADDR_CMD_LEN 14 33 #define WRITE_BAUD_CMD_LEN 6 34 #define MAX_CMD_LEN WRITE_BDADDR_CMD_LEN 35 #define GET_VERSION_OCF 0x1E 36 /* Byte order conversions */ 37 #if __BYTE_ORDER == __LITTLE_ENDIAN 38 #define htobs(d) (d) 39 #define htobl(d) (d) 40 #define btohs(d) (d) 41 #define btohl(d) (d) 42 #elif __BYTE_ORDER == __BIG_ENDIAN 43 #define htobs(d) bswap_16(d) 44 #define htobl(d) bswap_32(d) 45 #define btohs(d) bswap_16(d) 46 #define btohl(d) bswap_32(d) 47 #else 48 #error "Unknown byte order" 49 #endif 50 51 #define FW_PATH "/system/etc/firmware/ar3k/" 52 53 #define STREAM_TO_UINT16(u16, p) \ 54 {u16 = ((uint16_t)(*(p)) + (((uint16_t)(*((p) + 1))) << 8)); (p) += 2;} 55 #define UINT16_TO_STREAM(p, u16) \ 56 {*(p)++ = (uint8_t)(u16); *(p)++ = (uint8_t)((u16) >> 8);} 57 #define UINT32_TO_STREAM(p, u32) \ 58 {*(p)++ = (uint8_t)(u32); *(p)++ = (uint8_t)((u32) >> 8);\ 59 *(p)++ = (uint8_t)((u32) >> 16); *(p)++ = (uint8_t)((u32) >> 24);} 60 61 #define MAX_TAGS 50 62 #define PS_HDR_LEN 4 63 #define HCI_VENDOR_CMD_OGF 0x3F 64 #define HCI_PS_CMD_OCF 0x0B 65 66 #define VERIFY_CRC 9 67 #define PS_REGION 1 68 #define PATCH_REGION 2 69 #define BDADDR_FILE "ar3kbdaddr.pst" 70 71 72 #define MAX_PATCH_CMD 244 73 struct patch_entry { 74 int16_t len; 75 uint8_t data[MAX_PATCH_CMD]; 76 }; 77 #define HCI_UART_RAW_DEVICE 0 78 #define HCI_COMMAND_HDR_SIZE 3 79 #define PS_WRITE 1 80 #define PS_RESET 2 81 #define WRITE_PATCH 8 82 #define ENABLE_PATCH 11 83 84 #define HCI_PS_CMD_HDR_LEN 7 85 #define HCI_CMD_MAX_LEN 258 86 #define PS_RESET_PARAM_LEN 6 87 #define PS_RESET_CMD_LEN (HCI_PS_CMD_HDR_LEN + PS_RESET_PARAM_LEN) 88 89 #define PS_ID_MASK 0xFF 90 91 92 #define LOCAL_NAME_BUFFER_LEN 32 93 #define DEV_REGISTER 0x4FFC 94 #define GET_DEV_TYPE_OCF 0x05 95 96 #define HCIDEVUP _IOW('H', 201, int) 97 #define OGF_VENDOR_CMD 0x3f 98 #define EVT_CMD_COMPLETE_SIZE 3 99 #define EVT_CMD_STATUS 0x0F 100 #define EVT_CMD_STATUS_SIZE 4 101 #define HCI_COMMAND_HDR_SIZE 3 102 #define HCI_EVENT_HDR_SIZE 2 103 #define HCI_EV_SUCCESS 0x00 104 /* HCI Socket options */ 105 #define HCI_DATA_DIR 1 106 #define HCI_FILTER 2 107 #define HCI_TIME_STAMP 3 108 109 /* HCI CMSG flags */ 110 #define HCI_CMSG_DIR 0x0001 111 #define HCI_CMSG_TSTAMP 0x0002 112 113 #ifndef VENDOR_LPM_PROC_NODE 114 #define VENDOR_LPM_PROC_NODE "/sys/module/hci_uart/parameters/ath_lpm" 115 #endif 116 117 /* proc fs node for notifying write request */ 118 #ifndef VENDOR_BTWRITE_PROC_NODE 119 #define VENDOR_BTWRITE_PROC_NODE "/sys/module/hci_uart/parameters/ath_btwrite" 120 #endif 121 122 /****************************************************************************** 123 ** Local type definitions 124 ******************************************************************************/ 125 typedef struct { 126 uint8_t b[6]; 127 } __attribute__((packed)) bdaddr_t; 128 129 struct sockaddr_hci { 130 sa_family_t hci_family; 131 unsigned short hci_dev; 132 unsigned short hci_channel; 133 }; 134 135 struct tag_info { 136 unsigned section; 137 unsigned line_count; 138 unsigned char_cnt; 139 unsigned byte_count; 140 }; 141 142 struct ps_cfg_entry { 143 uint32_t id; 144 uint32_t len; 145 uint8_t *data; 146 }; 147 148 struct ps_entry_type { 149 unsigned char type; 150 unsigned char array; 151 }; 152 153 struct uart_t { 154 char *type; 155 int m_id; 156 int p_id; 157 int proto; 158 int init_speed; 159 int speed; 160 int flags; 161 int pm; 162 char *bdaddr; 163 int (*init) (int fd, struct uart_t *u, struct termios *ti); 164 int (*post) (int fd, struct uart_t *u, struct termios *ti); 165 }; 166 #endif /* HW_AR3K_H */ 167
