1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef _UAPI_MSM_MDP_H_ 20 #define _UAPI_MSM_MDP_H_ 21 #include <linux/types.h> 22 #include <linux/fb.h> 23 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 24 #define MSMFB_IOCTL_MAGIC 'm' 25 #define MSMFB_GRP_DISP _IOW(MSMFB_IOCTL_MAGIC, 1, unsigned int) 26 #define MSMFB_BLIT _IOW(MSMFB_IOCTL_MAGIC, 2, unsigned int) 27 #define MSMFB_SUSPEND_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 128, unsigned int) 28 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 29 #define MSMFB_RESUME_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 129, unsigned int) 30 #define MSMFB_CURSOR _IOW(MSMFB_IOCTL_MAGIC, 130, struct fb_cursor) 31 #define MSMFB_SET_LUT _IOW(MSMFB_IOCTL_MAGIC, 131, struct fb_cmap) 32 #define MSMFB_HISTOGRAM _IOWR(MSMFB_IOCTL_MAGIC, 132, struct mdp_histogram_data) 33 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 34 #define MSMFB_GET_CCS_MATRIX _IOWR(MSMFB_IOCTL_MAGIC, 133, struct mdp_ccs) 35 #define MSMFB_SET_CCS_MATRIX _IOW(MSMFB_IOCTL_MAGIC, 134, struct mdp_ccs) 36 #define MSMFB_OVERLAY_SET _IOWR(MSMFB_IOCTL_MAGIC, 135, struct mdp_overlay) 37 #define MSMFB_OVERLAY_UNSET _IOW(MSMFB_IOCTL_MAGIC, 136, unsigned int) 38 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 39 #define MSMFB_OVERLAY_PLAY _IOW(MSMFB_IOCTL_MAGIC, 137, struct msmfb_overlay_data) 40 #define MSMFB_OVERLAY_QUEUE MSMFB_OVERLAY_PLAY 41 #define MSMFB_GET_PAGE_PROTECTION _IOR(MSMFB_IOCTL_MAGIC, 138, struct mdp_page_protection) 42 #define MSMFB_SET_PAGE_PROTECTION _IOW(MSMFB_IOCTL_MAGIC, 139, struct mdp_page_protection) 43 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 44 #define MSMFB_OVERLAY_GET _IOR(MSMFB_IOCTL_MAGIC, 140, struct mdp_overlay) 45 #define MSMFB_OVERLAY_PLAY_ENABLE _IOW(MSMFB_IOCTL_MAGIC, 141, unsigned int) 46 #define MSMFB_OVERLAY_BLT _IOWR(MSMFB_IOCTL_MAGIC, 142, struct msmfb_overlay_blt) 47 #define MSMFB_OVERLAY_BLT_OFFSET _IOW(MSMFB_IOCTL_MAGIC, 143, unsigned int) 48 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 49 #define MSMFB_HISTOGRAM_START _IOR(MSMFB_IOCTL_MAGIC, 144, struct mdp_histogram_start_req) 50 #define MSMFB_HISTOGRAM_STOP _IOR(MSMFB_IOCTL_MAGIC, 145, unsigned int) 51 #define MSMFB_NOTIFY_UPDATE _IOWR(MSMFB_IOCTL_MAGIC, 146, unsigned int) 52 #define MSMFB_OVERLAY_3D _IOWR(MSMFB_IOCTL_MAGIC, 147, struct msmfb_overlay_3d) 53 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 54 #define MSMFB_MIXER_INFO _IOWR(MSMFB_IOCTL_MAGIC, 148, struct msmfb_mixer_info_req) 55 #define MSMFB_OVERLAY_PLAY_WAIT _IOWR(MSMFB_IOCTL_MAGIC, 149, struct msmfb_overlay_data) 56 #define MSMFB_WRITEBACK_INIT _IO(MSMFB_IOCTL_MAGIC, 150) 57 #define MSMFB_WRITEBACK_START _IO(MSMFB_IOCTL_MAGIC, 151) 58 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 59 #define MSMFB_WRITEBACK_STOP _IO(MSMFB_IOCTL_MAGIC, 152) 60 #define MSMFB_WRITEBACK_QUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 153, struct msmfb_data) 61 #define MSMFB_WRITEBACK_DEQUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 154, struct msmfb_data) 62 #define MSMFB_WRITEBACK_TERMINATE _IO(MSMFB_IOCTL_MAGIC, 155) 63 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 64 #define MSMFB_MDP_PP _IOWR(MSMFB_IOCTL_MAGIC, 156, struct msmfb_mdp_pp) 65 #define MSMFB_OVERLAY_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 160, unsigned int) 66 #define MSMFB_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 161, unsigned int) 67 #define MSMFB_BUFFER_SYNC _IOW(MSMFB_IOCTL_MAGIC, 162, struct mdp_buf_sync) 68 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 69 #define MSMFB_OVERLAY_COMMIT _IO(MSMFB_IOCTL_MAGIC, 163) 70 #define MSMFB_DISPLAY_COMMIT _IOW(MSMFB_IOCTL_MAGIC, 164, struct mdp_display_commit) 71 #define MSMFB_METADATA_SET _IOW(MSMFB_IOCTL_MAGIC, 165, struct msmfb_metadata) 72 #define MSMFB_METADATA_GET _IOW(MSMFB_IOCTL_MAGIC, 166, struct msmfb_metadata) 73 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 74 #define MSMFB_WRITEBACK_SET_MIRRORING_HINT _IOW(MSMFB_IOCTL_MAGIC, 167, unsigned int) 75 #define MSMFB_ASYNC_BLIT _IOW(MSMFB_IOCTL_MAGIC, 168, unsigned int) 76 #define MSMFB_OVERLAY_PREPARE _IOWR(MSMFB_IOCTL_MAGIC, 169, struct mdp_overlay_list) 77 #define MSMFB_LPM_ENABLE _IOWR(MSMFB_IOCTL_MAGIC, 170, unsigned int) 78 #define MSMFB_SET_PERSISTENCE_MODE _IOWR(MSMFB_IOCTL_MAGIC, 171, unsigned int) 79 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 80 #define FB_TYPE_3D_PANEL 0x10101010 81 #define MDP_IMGTYPE2_START 0x10000 82 #define MSMFB_DRIVER_VERSION 0xF9E8D701 83 #define MDSS_GET_MAJOR(rev) ((rev) >> 28) 84 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 85 #define MDSS_GET_MINOR(rev) (((rev) >> 16) & 0xFFF) 86 #define MDSS_GET_STEP(rev) ((rev) & 0xFFFF) 87 #define MDSS_GET_MAJOR_MINOR(rev) ((rev) >> 16) 88 #define IS_MDSS_MAJOR_MINOR_SAME(rev1,rev2) (MDSS_GET_MAJOR_MINOR((rev1)) == MDSS_GET_MAJOR_MINOR((rev2))) 89 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 90 #define MDSS_MDP_REV(major,minor,step) ((((major) & 0x000F) << 28) | (((minor) & 0x0FFF) << 16) | ((step) & 0xFFFF)) 91 #define MDSS_MDP_HW_REV_100 MDSS_MDP_REV(1, 0, 0) 92 #define MDSS_MDP_HW_REV_101 MDSS_MDP_REV(1, 1, 0) 93 #define MDSS_MDP_HW_REV_101_1 MDSS_MDP_REV(1, 1, 1) 94 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 95 #define MDSS_MDP_HW_REV_101_2 MDSS_MDP_REV(1, 1, 2) 96 #define MDSS_MDP_HW_REV_102 MDSS_MDP_REV(1, 2, 0) 97 #define MDSS_MDP_HW_REV_102_1 MDSS_MDP_REV(1, 2, 1) 98 #define MDSS_MDP_HW_REV_103 MDSS_MDP_REV(1, 3, 0) 99 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 100 #define MDSS_MDP_HW_REV_103_1 MDSS_MDP_REV(1, 3, 1) 101 #define MDSS_MDP_HW_REV_105 MDSS_MDP_REV(1, 5, 0) 102 #define MDSS_MDP_HW_REV_106 MDSS_MDP_REV(1, 6, 0) 103 #define MDSS_MDP_HW_REV_107 MDSS_MDP_REV(1, 7, 0) 104 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 105 #define MDSS_MDP_HW_REV_108 MDSS_MDP_REV(1, 8, 0) 106 #define MDSS_MDP_HW_REV_109 MDSS_MDP_REV(1, 9, 0) 107 #define MDSS_MDP_HW_REV_110 MDSS_MDP_REV(1, 10, 0) 108 #define MDSS_MDP_HW_REV_200 MDSS_MDP_REV(2, 0, 0) 109 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 110 enum { 111 NOTIFY_UPDATE_INIT, 112 NOTIFY_UPDATE_DEINIT, 113 NOTIFY_UPDATE_START, 114 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 115 NOTIFY_UPDATE_STOP, 116 NOTIFY_UPDATE_POWER_OFF, 117 }; 118 enum { 119 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 120 NOTIFY_TYPE_NO_UPDATE, 121 NOTIFY_TYPE_SUSPEND, 122 NOTIFY_TYPE_UPDATE, 123 NOTIFY_TYPE_BL_UPDATE, 124 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 125 NOTIFY_TYPE_BL_AD_ATTEN_UPDATE, 126 }; 127 enum { 128 MDP_RGB_565, 129 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 130 MDP_XRGB_8888, 131 MDP_Y_CBCR_H2V2, 132 MDP_Y_CBCR_H2V2_ADRENO, 133 MDP_ARGB_8888, 134 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 135 MDP_RGB_888, 136 MDP_Y_CRCB_H2V2, 137 MDP_YCRYCB_H2V1, 138 MDP_CBYCRY_H2V1, 139 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 140 MDP_Y_CRCB_H2V1, 141 MDP_Y_CBCR_H2V1, 142 MDP_Y_CRCB_H1V2, 143 MDP_Y_CBCR_H1V2, 144 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 145 MDP_RGBA_8888, 146 MDP_BGRA_8888, 147 MDP_RGBX_8888, 148 MDP_Y_CRCB_H2V2_TILE, 149 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 150 MDP_Y_CBCR_H2V2_TILE, 151 MDP_Y_CR_CB_H2V2, 152 MDP_Y_CR_CB_GH2V2, 153 MDP_Y_CB_CR_H2V2, 154 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 155 MDP_Y_CRCB_H1V1, 156 MDP_Y_CBCR_H1V1, 157 MDP_YCRCB_H1V1, 158 MDP_YCBCR_H1V1, 159 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 160 MDP_BGR_565, 161 MDP_BGR_888, 162 MDP_Y_CBCR_H2V2_VENUS, 163 MDP_BGRX_8888, 164 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 165 MDP_RGBA_8888_TILE, 166 MDP_ARGB_8888_TILE, 167 MDP_ABGR_8888_TILE, 168 MDP_BGRA_8888_TILE, 169 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 170 MDP_RGBX_8888_TILE, 171 MDP_XRGB_8888_TILE, 172 MDP_XBGR_8888_TILE, 173 MDP_BGRX_8888_TILE, 174 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 175 MDP_YCBYCR_H2V1, 176 MDP_RGB_565_TILE, 177 MDP_BGR_565_TILE, 178 MDP_ARGB_1555, 179 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 180 MDP_RGBA_5551, 181 MDP_ARGB_4444, 182 MDP_RGBA_4444, 183 MDP_RGB_565_UBWC, 184 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 185 MDP_RGBA_8888_UBWC, 186 MDP_Y_CBCR_H2V2_UBWC, 187 MDP_IMGTYPE_LIMIT, 188 MDP_RGB_BORDERFILL, 189 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 190 MDP_FB_FORMAT = MDP_IMGTYPE2_START, 191 MDP_IMGTYPE_LIMIT2 192 }; 193 enum { 194 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 195 PMEM_IMG, 196 FB_IMG, 197 }; 198 enum { 199 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 200 HSIC_HUE = 0, 201 HSIC_SAT, 202 HSIC_INT, 203 HSIC_CON, 204 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 205 NUM_HSIC_PARAM, 206 }; 207 #define MDSS_MDP_ROT_ONLY 0x80 208 #define MDSS_MDP_RIGHT_MIXER 0x100 209 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 210 #define MDSS_MDP_DUAL_PIPE 0x200 211 #define MDP_ROT_NOP 0 212 #define MDP_FLIP_LR 0x1 213 #define MDP_FLIP_UD 0x2 214 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 215 #define MDP_ROT_90 0x4 216 #define MDP_ROT_180 (MDP_FLIP_UD | MDP_FLIP_LR) 217 #define MDP_ROT_270 (MDP_ROT_90 | MDP_FLIP_UD | MDP_FLIP_LR) 218 #define MDP_DITHER 0x8 219 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 220 #define MDP_BLUR 0x10 221 #define MDP_BLEND_FG_PREMULT 0x20000 222 #define MDP_IS_FG 0x40000 223 #define MDP_SOLID_FILL 0x00000020 224 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 225 #define MDP_VPU_PIPE 0x00000040 226 #define MDP_DEINTERLACE 0x80000000 227 #define MDP_SHARPENING 0x40000000 228 #define MDP_NO_DMA_BARRIER_START 0x20000000 229 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 230 #define MDP_NO_DMA_BARRIER_END 0x10000000 231 #define MDP_NO_BLIT 0x08000000 232 #define MDP_BLIT_WITH_DMA_BARRIERS 0x000 233 #define MDP_BLIT_WITH_NO_DMA_BARRIERS (MDP_NO_DMA_BARRIER_START | MDP_NO_DMA_BARRIER_END) 234 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 235 #define MDP_BLIT_SRC_GEM 0x04000000 236 #define MDP_BLIT_DST_GEM 0x02000000 237 #define MDP_BLIT_NON_CACHED 0x01000000 238 #define MDP_OV_PIPE_SHARE 0x00800000 239 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 240 #define MDP_DEINTERLACE_ODD 0x00400000 241 #define MDP_OV_PLAY_NOWAIT 0x00200000 242 #define MDP_SOURCE_ROTATED_90 0x00100000 243 #define MDP_OVERLAY_PP_CFG_EN 0x00080000 244 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 245 #define MDP_BACKEND_COMPOSITION 0x00040000 246 #define MDP_BORDERFILL_SUPPORTED 0x00010000 247 #define MDP_SECURE_OVERLAY_SESSION 0x00008000 248 #define MDP_SECURE_DISPLAY_OVERLAY_SESSION 0x00002000 249 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 250 #define MDP_OV_PIPE_FORCE_DMA 0x00004000 251 #define MDP_MEMORY_ID_TYPE_FB 0x00001000 252 #define MDP_BWC_EN 0x00000400 253 #define MDP_DECIMATION_EN 0x00000800 254 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 255 #define MDP_SMP_FORCE_ALLOC 0x00200000 256 #define MDP_TRANSP_NOP 0xffffffff 257 #define MDP_ALPHA_NOP 0xff 258 #define MDP_SMART_BLIT 0xC0000000 259 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 260 #define MDP_FB_PAGE_PROTECTION_NONCACHED (0) 261 #define MDP_FB_PAGE_PROTECTION_WRITECOMBINE (1) 262 #define MDP_FB_PAGE_PROTECTION_WRITETHROUGHCACHE (2) 263 #define MDP_FB_PAGE_PROTECTION_WRITEBACKCACHE (3) 264 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 265 #define MDP_FB_PAGE_PROTECTION_WRITEBACKWACACHE (4) 266 #define MDP_FB_PAGE_PROTECTION_INVALID (5) 267 #define MDP_NUM_FB_PAGE_PROTECTION_VALUES (5) 268 struct mdp_rect { 269 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 270 uint32_t x; 271 uint32_t y; 272 uint32_t w; 273 uint32_t h; 274 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 275 }; 276 struct mdp_img { 277 uint32_t width; 278 uint32_t height; 279 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 280 uint32_t format; 281 uint32_t offset; 282 int memory_id; 283 uint32_t priv; 284 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 285 }; 286 #define MDP_CCS_RGB2YUV 0 287 #define MDP_CCS_YUV2RGB 1 288 #define MDP_CCS_SIZE 9 289 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 290 #define MDP_BV_SIZE 3 291 struct mdp_ccs { 292 int direction; 293 uint16_t ccs[MDP_CCS_SIZE]; 294 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 295 uint16_t bv[MDP_BV_SIZE]; 296 }; 297 struct mdp_csc { 298 int id; 299 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 300 uint32_t csc_mv[9]; 301 uint32_t csc_pre_bv[3]; 302 uint32_t csc_post_bv[3]; 303 uint32_t csc_pre_lv[6]; 304 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 305 uint32_t csc_post_lv[6]; 306 }; 307 #define MDP_BLIT_REQ_VERSION 2 308 struct color { 309 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 310 uint32_t r; 311 uint32_t g; 312 uint32_t b; 313 uint32_t alpha; 314 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 315 }; 316 struct mdp_blit_req { 317 struct mdp_img src; 318 struct mdp_img dst; 319 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 320 struct mdp_rect src_rect; 321 struct mdp_rect dst_rect; 322 struct color const_color; 323 uint32_t alpha; 324 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 325 uint32_t transp_mask; 326 uint32_t flags; 327 int sharpening_strength; 328 uint8_t color_space; 329 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 330 uint32_t fps; 331 }; 332 struct mdp_blit_req_list { 333 uint32_t count; 334 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 335 struct mdp_blit_req req[]; 336 }; 337 #define MSMFB_DATA_VERSION 2 338 struct msmfb_data { 339 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 340 uint32_t offset; 341 int memory_id; 342 int id; 343 uint32_t flags; 344 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 345 uint32_t priv; 346 uint32_t iova; 347 }; 348 #define MSMFB_NEW_REQUEST - 1 349 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 350 struct msmfb_overlay_data { 351 uint32_t id; 352 struct msmfb_data data; 353 uint32_t version_key; 354 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 355 struct msmfb_data plane1_data; 356 struct msmfb_data plane2_data; 357 struct msmfb_data dst_data; 358 }; 359 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 360 struct msmfb_img { 361 uint32_t width; 362 uint32_t height; 363 uint32_t format; 364 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 365 }; 366 #define MSMFB_WRITEBACK_DEQUEUE_BLOCKING 0x1 367 struct msmfb_writeback_data { 368 struct msmfb_data buf_info; 369 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 370 struct msmfb_img img; 371 }; 372 #define MDP_PP_OPS_ENABLE 0x1 373 #define MDP_PP_OPS_READ 0x2 374 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 375 #define MDP_PP_OPS_WRITE 0x4 376 #define MDP_PP_OPS_DISABLE 0x8 377 #define MDP_PP_IGC_FLAG_ROM0 0x10 378 #define MDP_PP_IGC_FLAG_ROM1 0x20 379 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 380 #define MDP_PP_PA_HUE_ENABLE 0x10 381 #define MDP_PP_PA_SAT_ENABLE 0x20 382 #define MDP_PP_PA_VAL_ENABLE 0x40 383 #define MDP_PP_PA_CONT_ENABLE 0x80 384 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 385 #define MDP_PP_PA_SIX_ZONE_ENABLE 0x100 386 #define MDP_PP_PA_SKIN_ENABLE 0x200 387 #define MDP_PP_PA_SKY_ENABLE 0x400 388 #define MDP_PP_PA_FOL_ENABLE 0x800 389 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 390 #define MDP_PP_PA_HUE_MASK 0x1000 391 #define MDP_PP_PA_SAT_MASK 0x2000 392 #define MDP_PP_PA_VAL_MASK 0x4000 393 #define MDP_PP_PA_CONT_MASK 0x8000 394 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 395 #define MDP_PP_PA_SIX_ZONE_HUE_MASK 0x10000 396 #define MDP_PP_PA_SIX_ZONE_SAT_MASK 0x20000 397 #define MDP_PP_PA_SIX_ZONE_VAL_MASK 0x40000 398 #define MDP_PP_PA_MEM_COL_SKIN_MASK 0x80000 399 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 400 #define MDP_PP_PA_MEM_COL_SKY_MASK 0x100000 401 #define MDP_PP_PA_MEM_COL_FOL_MASK 0x200000 402 #define MDP_PP_PA_MEM_PROTECT_EN 0x400000 403 #define MDP_PP_PA_SAT_ZERO_EXP_EN 0x800000 404 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 405 #define MDSS_PP_DSPP_CFG 0x000 406 #define MDSS_PP_SSPP_CFG 0x100 407 #define MDSS_PP_LM_CFG 0x200 408 #define MDSS_PP_WB_CFG 0x300 409 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 410 #define MDSS_PP_ARG_MASK 0x3C00 411 #define MDSS_PP_ARG_NUM 4 412 #define MDSS_PP_ARG_SHIFT 10 413 #define MDSS_PP_LOCATION_MASK 0x0300 414 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 415 #define MDSS_PP_LOGICAL_MASK 0x00FF 416 #define MDSS_PP_ADD_ARG(var,arg) ((var) | (0x1 << (MDSS_PP_ARG_SHIFT + (arg)))) 417 #define PP_ARG(x,var) ((var) & (0x1 << (MDSS_PP_ARG_SHIFT + (x)))) 418 #define PP_LOCAT(var) ((var) & MDSS_PP_LOCATION_MASK) 419 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 420 #define PP_BLOCK(var) ((var) & MDSS_PP_LOGICAL_MASK) 421 struct mdp_qseed_cfg { 422 uint32_t table_num; 423 uint32_t ops; 424 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 425 uint32_t len; 426 uint32_t * data; 427 }; 428 struct mdp_sharp_cfg { 429 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 430 uint32_t flags; 431 uint32_t strength; 432 uint32_t edge_thr; 433 uint32_t smooth_thr; 434 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 435 uint32_t noise_thr; 436 }; 437 struct mdp_qseed_cfg_data { 438 uint32_t block; 439 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 440 struct mdp_qseed_cfg qseed_data; 441 }; 442 #define MDP_OVERLAY_PP_CSC_CFG 0x1 443 #define MDP_OVERLAY_PP_QSEED_CFG 0x2 444 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 445 #define MDP_OVERLAY_PP_PA_CFG 0x4 446 #define MDP_OVERLAY_PP_IGC_CFG 0x8 447 #define MDP_OVERLAY_PP_SHARP_CFG 0x10 448 #define MDP_OVERLAY_PP_HIST_CFG 0x20 449 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 450 #define MDP_OVERLAY_PP_HIST_LUT_CFG 0x40 451 #define MDP_OVERLAY_PP_PA_V2_CFG 0x80 452 #define MDP_CSC_FLAG_ENABLE 0x1 453 #define MDP_CSC_FLAG_YUV_IN 0x2 454 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 455 #define MDP_CSC_FLAG_YUV_OUT 0x4 456 struct mdp_csc_cfg { 457 uint32_t flags; 458 uint32_t csc_mv[9]; 459 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 460 uint32_t csc_pre_bv[3]; 461 uint32_t csc_post_bv[3]; 462 uint32_t csc_pre_lv[6]; 463 uint32_t csc_post_lv[6]; 464 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 465 }; 466 struct mdp_csc_cfg_data { 467 uint32_t block; 468 struct mdp_csc_cfg csc_data; 469 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 470 }; 471 struct mdp_pa_cfg { 472 uint32_t flags; 473 uint32_t hue_adj; 474 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 475 uint32_t sat_adj; 476 uint32_t val_adj; 477 uint32_t cont_adj; 478 }; 479 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 480 struct mdp_pa_mem_col_cfg { 481 uint32_t color_adjust_p0; 482 uint32_t color_adjust_p1; 483 uint32_t hue_region; 484 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 485 uint32_t sat_region; 486 uint32_t val_region; 487 }; 488 #define MDP_SIX_ZONE_LUT_SIZE 384 489 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 490 struct mdp_pa_v2_data { 491 uint32_t flags; 492 uint32_t global_hue_adj; 493 uint32_t global_sat_adj; 494 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 495 uint32_t global_val_adj; 496 uint32_t global_cont_adj; 497 struct mdp_pa_mem_col_cfg skin_cfg; 498 struct mdp_pa_mem_col_cfg sky_cfg; 499 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 500 struct mdp_pa_mem_col_cfg fol_cfg; 501 uint32_t six_zone_len; 502 uint32_t six_zone_thresh; 503 uint32_t * six_zone_curve_p0; 504 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 505 uint32_t * six_zone_curve_p1; 506 }; 507 struct mdp_igc_lut_data { 508 uint32_t block; 509 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 510 uint32_t len, ops; 511 uint32_t * c0_c1_data; 512 uint32_t * c2_data; 513 }; 514 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 515 struct mdp_histogram_cfg { 516 uint32_t ops; 517 uint32_t block; 518 uint8_t frame_cnt; 519 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 520 uint8_t bit_mask; 521 uint16_t num_bins; 522 }; 523 struct mdp_hist_lut_data { 524 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 525 uint32_t block; 526 uint32_t ops; 527 uint32_t len; 528 uint32_t * data; 529 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 530 }; 531 struct mdp_overlay_pp_params { 532 uint32_t config_ops; 533 struct mdp_csc_cfg csc_cfg; 534 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 535 struct mdp_qseed_cfg qseed_cfg[2]; 536 struct mdp_pa_cfg pa_cfg; 537 struct mdp_pa_v2_data pa_v2_cfg; 538 struct mdp_igc_lut_data igc_cfg; 539 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 540 struct mdp_sharp_cfg sharp_cfg; 541 struct mdp_histogram_cfg hist_cfg; 542 struct mdp_hist_lut_data hist_lut_cfg; 543 }; 544 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 545 enum mdss_mdp_blend_op { 546 BLEND_OP_NOT_DEFINED = 0, 547 BLEND_OP_OPAQUE, 548 BLEND_OP_PREMULTIPLIED, 549 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 550 BLEND_OP_COVERAGE, 551 BLEND_OP_MAX, 552 }; 553 #define DECIMATED_DIMENSION(dim,deci) (((dim) + ((1 << (deci)) - 1)) >> (deci)) 554 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 555 #define MAX_PLANES 4 556 struct mdp_scale_data { 557 uint8_t enable_pxl_ext; 558 int init_phase_x[MAX_PLANES]; 559 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 560 int phase_step_x[MAX_PLANES]; 561 int init_phase_y[MAX_PLANES]; 562 int phase_step_y[MAX_PLANES]; 563 int num_ext_pxls_left[MAX_PLANES]; 564 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 565 int num_ext_pxls_right[MAX_PLANES]; 566 int num_ext_pxls_top[MAX_PLANES]; 567 int num_ext_pxls_btm[MAX_PLANES]; 568 int left_ftch[MAX_PLANES]; 569 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 570 int left_rpt[MAX_PLANES]; 571 int right_ftch[MAX_PLANES]; 572 int right_rpt[MAX_PLANES]; 573 int top_rpt[MAX_PLANES]; 574 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 575 int btm_rpt[MAX_PLANES]; 576 int top_ftch[MAX_PLANES]; 577 int btm_ftch[MAX_PLANES]; 578 uint32_t roi_w[MAX_PLANES]; 579 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 580 }; 581 enum mdp_overlay_pipe_type { 582 PIPE_TYPE_AUTO = 0, 583 PIPE_TYPE_VIG, 584 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 585 PIPE_TYPE_RGB, 586 PIPE_TYPE_DMA, 587 PIPE_TYPE_CURSOR, 588 PIPE_TYPE_MAX, 589 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 590 }; 591 struct mdp_overlay { 592 struct msmfb_img src; 593 struct mdp_rect src_rect; 594 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 595 struct mdp_rect dst_rect; 596 uint32_t z_order; 597 uint32_t is_fg; 598 uint32_t alpha; 599 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 600 uint32_t blend_op; 601 uint32_t transp_mask; 602 uint32_t flags; 603 uint32_t pipe_type; 604 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 605 uint32_t id; 606 uint8_t priority; 607 uint32_t user_data[6]; 608 uint32_t bg_color; 609 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 610 uint8_t horz_deci; 611 uint8_t vert_deci; 612 struct mdp_overlay_pp_params overlay_pp_cfg; 613 struct mdp_scale_data scale; 614 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 615 uint8_t color_space; 616 }; 617 struct msmfb_overlay_3d { 618 uint32_t is_3d; 619 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 620 uint32_t width; 621 uint32_t height; 622 }; 623 struct msmfb_overlay_blt { 624 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 625 uint32_t enable; 626 uint32_t offset; 627 uint32_t width; 628 uint32_t height; 629 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 630 uint32_t bpp; 631 }; 632 struct mdp_histogram { 633 uint32_t frame_cnt; 634 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 635 uint32_t bin_cnt; 636 uint32_t * r; 637 uint32_t * g; 638 uint32_t * b; 639 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 640 }; 641 #define MISR_CRC_BATCH_SIZE 32 642 enum { 643 DISPLAY_MISR_EDP, 644 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 645 DISPLAY_MISR_DSI0, 646 DISPLAY_MISR_DSI1, 647 DISPLAY_MISR_HDMI, 648 DISPLAY_MISR_LCDC, 649 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 650 DISPLAY_MISR_MDP, 651 DISPLAY_MISR_ATV, 652 DISPLAY_MISR_DSI_CMD, 653 DISPLAY_MISR_MAX 654 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 655 }; 656 enum { 657 MISR_OP_NONE, 658 MISR_OP_SFM, 659 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 660 MISR_OP_MFM, 661 MISR_OP_BM, 662 MISR_OP_MAX 663 }; 664 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 665 struct mdp_misr { 666 uint32_t block_id; 667 uint32_t frame_count; 668 uint32_t crc_op_mode; 669 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 670 uint32_t crc_value[MISR_CRC_BATCH_SIZE]; 671 }; 672 enum { 673 MDP_BLOCK_RESERVED = 0, 674 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 675 MDP_BLOCK_OVERLAY_0, 676 MDP_BLOCK_OVERLAY_1, 677 MDP_BLOCK_VG_1, 678 MDP_BLOCK_VG_2, 679 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 680 MDP_BLOCK_RGB_1, 681 MDP_BLOCK_RGB_2, 682 MDP_BLOCK_DMA_P, 683 MDP_BLOCK_DMA_S, 684 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 685 MDP_BLOCK_DMA_E, 686 MDP_BLOCK_OVERLAY_2, 687 MDP_LOGICAL_BLOCK_DISP_0 = 0x10, 688 MDP_LOGICAL_BLOCK_DISP_1, 689 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 690 MDP_LOGICAL_BLOCK_DISP_2, 691 MDP_BLOCK_MAX, 692 }; 693 struct mdp_histogram_start_req { 694 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 695 uint32_t block; 696 uint8_t frame_cnt; 697 uint8_t bit_mask; 698 uint16_t num_bins; 699 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 700 }; 701 struct mdp_histogram_data { 702 uint32_t block; 703 uint32_t bin_cnt; 704 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 705 uint32_t * c0; 706 uint32_t * c1; 707 uint32_t * c2; 708 uint32_t * extra_info; 709 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 710 }; 711 struct mdp_pcc_coeff { 712 uint32_t c, r, g, b, rr, gg, bb, rg, gb, rb, rgb_0, rgb_1; 713 }; 714 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 715 struct mdp_pcc_cfg_data { 716 uint32_t block; 717 uint32_t ops; 718 struct mdp_pcc_coeff r, g, b; 719 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 720 }; 721 #define MDP_GAMUT_TABLE_NUM 8 722 enum { 723 mdp_lut_igc, 724 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 725 mdp_lut_pgc, 726 mdp_lut_hist, 727 mdp_lut_rgb, 728 mdp_lut_max, 729 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 730 }; 731 struct mdp_ar_gc_lut_data { 732 uint32_t x_start; 733 uint32_t slope; 734 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 735 uint32_t offset; 736 }; 737 struct mdp_pgc_lut_data { 738 uint32_t block; 739 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 740 uint32_t flags; 741 uint8_t num_r_stages; 742 uint8_t num_g_stages; 743 uint8_t num_b_stages; 744 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 745 struct mdp_ar_gc_lut_data * r_data; 746 struct mdp_ar_gc_lut_data * g_data; 747 struct mdp_ar_gc_lut_data * b_data; 748 }; 749 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 750 struct mdp_rgb_lut_data { 751 uint32_t flags; 752 uint32_t lut_type; 753 struct fb_cmap cmap; 754 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 755 }; 756 enum { 757 mdp_rgb_lut_gc, 758 mdp_rgb_lut_hist, 759 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 760 }; 761 struct mdp_lut_cfg_data { 762 uint32_t lut_type; 763 union { 764 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 765 struct mdp_igc_lut_data igc_lut_data; 766 struct mdp_pgc_lut_data pgc_lut_data; 767 struct mdp_hist_lut_data hist_lut_data; 768 struct mdp_rgb_lut_data rgb_lut_data; 769 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 770 } data; 771 }; 772 struct mdp_bl_scale_data { 773 uint32_t min_lvl; 774 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 775 uint32_t scale; 776 }; 777 struct mdp_pa_cfg_data { 778 uint32_t block; 779 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 780 struct mdp_pa_cfg pa_data; 781 }; 782 struct mdp_pa_v2_cfg_data { 783 uint32_t block; 784 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 785 struct mdp_pa_v2_data pa_v2_data; 786 }; 787 struct mdp_dither_cfg_data { 788 uint32_t block; 789 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 790 uint32_t flags; 791 uint32_t g_y_depth; 792 uint32_t r_cr_depth; 793 uint32_t b_cb_depth; 794 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 795 }; 796 struct mdp_gamut_cfg_data { 797 uint32_t block; 798 uint32_t flags; 799 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 800 uint32_t gamut_first; 801 uint32_t tbl_size[MDP_GAMUT_TABLE_NUM]; 802 uint16_t * r_tbl[MDP_GAMUT_TABLE_NUM]; 803 uint16_t * g_tbl[MDP_GAMUT_TABLE_NUM]; 804 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 805 uint16_t * b_tbl[MDP_GAMUT_TABLE_NUM]; 806 }; 807 struct mdp_calib_config_data { 808 uint32_t ops; 809 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 810 uint32_t addr; 811 uint32_t data; 812 }; 813 struct mdp_calib_config_buffer { 814 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 815 uint32_t ops; 816 uint32_t size; 817 uint32_t * buffer; 818 }; 819 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 820 struct mdp_calib_dcm_state { 821 uint32_t ops; 822 uint32_t dcm_state; 823 }; 824 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 825 struct mdp_pp_init_data { 826 uint32_t init_request; 827 }; 828 enum { 829 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 830 MDP_PP_DISABLE, 831 MDP_PP_ENABLE, 832 }; 833 enum { 834 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 835 DCM_UNINIT, 836 DCM_UNBLANK, 837 DCM_ENTER, 838 DCM_EXIT, 839 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 840 DCM_BLANK, 841 DTM_ENTER, 842 DTM_EXIT, 843 }; 844 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 845 #define MDSS_PP_SPLIT_LEFT_ONLY 0x10000000 846 #define MDSS_PP_SPLIT_RIGHT_ONLY 0x20000000 847 #define MDSS_PP_SPLIT_MASK 0x30000000 848 #define MDSS_MAX_BL_BRIGHTNESS 255 849 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 850 #define AD_BL_LIN_LEN 256 851 #define AD_BL_ATT_LUT_LEN 33 852 #define MDSS_AD_MODE_AUTO_BL 0x0 853 #define MDSS_AD_MODE_AUTO_STR 0x1 854 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 855 #define MDSS_AD_MODE_TARG_STR 0x3 856 #define MDSS_AD_MODE_MAN_STR 0x7 857 #define MDSS_AD_MODE_CALIB 0xF 858 #define MDP_PP_AD_INIT 0x10 859 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 860 #define MDP_PP_AD_CFG 0x20 861 struct mdss_ad_init { 862 uint32_t asym_lut[33]; 863 uint32_t color_corr_lut[33]; 864 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 865 uint8_t i_control[2]; 866 uint16_t black_lvl; 867 uint16_t white_lvl; 868 uint8_t var; 869 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 870 uint8_t limit_ampl; 871 uint8_t i_dither; 872 uint8_t slope_max; 873 uint8_t slope_min; 874 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 875 uint8_t dither_ctl; 876 uint8_t format; 877 uint8_t auto_size; 878 uint16_t frame_w; 879 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 880 uint16_t frame_h; 881 uint8_t logo_v; 882 uint8_t logo_h; 883 uint32_t alpha; 884 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 885 uint32_t alpha_base; 886 uint32_t bl_lin_len; 887 uint32_t bl_att_len; 888 uint32_t * bl_lin; 889 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 890 uint32_t * bl_lin_inv; 891 uint32_t * bl_att_lut; 892 }; 893 #define MDSS_AD_BL_CTRL_MODE_EN 1 894 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 895 #define MDSS_AD_BL_CTRL_MODE_DIS 0 896 struct mdss_ad_cfg { 897 uint32_t mode; 898 uint32_t al_calib_lut[33]; 899 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 900 uint16_t backlight_min; 901 uint16_t backlight_max; 902 uint16_t backlight_scale; 903 uint16_t amb_light_min; 904 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 905 uint16_t filter[2]; 906 uint16_t calib[4]; 907 uint8_t strength_limit; 908 uint8_t t_filter_recursion; 909 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 910 uint16_t stab_itr; 911 uint32_t bl_ctrl_mode; 912 }; 913 struct mdss_ad_init_cfg { 914 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 915 uint32_t ops; 916 union { 917 struct mdss_ad_init init; 918 struct mdss_ad_cfg cfg; 919 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 920 } params; 921 }; 922 struct mdss_ad_input { 923 uint32_t mode; 924 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 925 union { 926 uint32_t amb_light; 927 uint32_t strength; 928 uint32_t calib_bl; 929 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 930 } in; 931 uint32_t output; 932 }; 933 #define MDSS_CALIB_MODE_BL 0x1 934 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 935 struct mdss_calib_cfg { 936 uint32_t ops; 937 uint32_t calib_mask; 938 }; 939 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 940 enum { 941 mdp_op_pcc_cfg, 942 mdp_op_csc_cfg, 943 mdp_op_lut_cfg, 944 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 945 mdp_op_qseed_cfg, 946 mdp_bl_scale_cfg, 947 mdp_op_pa_cfg, 948 mdp_op_pa_v2_cfg, 949 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 950 mdp_op_dither_cfg, 951 mdp_op_gamut_cfg, 952 mdp_op_calib_cfg, 953 mdp_op_ad_cfg, 954 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 955 mdp_op_ad_input, 956 mdp_op_calib_mode, 957 mdp_op_calib_buffer, 958 mdp_op_calib_dcm_state, 959 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 960 mdp_op_max, 961 mdp_op_pp_init_cfg, 962 }; 963 enum { 964 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 965 WB_FORMAT_NV12, 966 WB_FORMAT_RGB_565, 967 WB_FORMAT_RGB_888, 968 WB_FORMAT_xRGB_8888, 969 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 970 WB_FORMAT_ARGB_8888, 971 WB_FORMAT_BGRA_8888, 972 WB_FORMAT_BGRX_8888, 973 WB_FORMAT_ARGB_8888_INPUT_ALPHA 974 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 975 }; 976 struct msmfb_mdp_pp { 977 uint32_t op; 978 union { 979 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 980 struct mdp_pcc_cfg_data pcc_cfg_data; 981 struct mdp_csc_cfg_data csc_cfg_data; 982 struct mdp_lut_cfg_data lut_cfg_data; 983 struct mdp_qseed_cfg_data qseed_cfg_data; 984 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 985 struct mdp_bl_scale_data bl_scale_data; 986 struct mdp_pa_cfg_data pa_cfg_data; 987 struct mdp_pa_v2_cfg_data pa_v2_cfg_data; 988 struct mdp_dither_cfg_data dither_cfg_data; 989 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 990 struct mdp_gamut_cfg_data gamut_cfg_data; 991 struct mdp_calib_config_data calib_cfg; 992 struct mdss_ad_init_cfg ad_init_cfg; 993 struct mdss_calib_cfg mdss_calib_cfg; 994 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 995 struct mdss_ad_input ad_input; 996 struct mdp_calib_config_buffer calib_buffer; 997 struct mdp_calib_dcm_state calib_dcm; 998 struct mdp_pp_init_data init_data; 999 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1000 } data; 1001 }; 1002 #define FB_METADATA_VIDEO_INFO_CODE_SUPPORT 1 1003 enum { 1004 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1005 metadata_op_none, 1006 metadata_op_base_blend, 1007 metadata_op_frame_rate, 1008 metadata_op_vic, 1009 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1010 metadata_op_wb_format, 1011 metadata_op_wb_secure, 1012 metadata_op_get_caps, 1013 metadata_op_crc, 1014 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1015 metadata_op_get_ion_fd, 1016 metadata_op_max 1017 }; 1018 struct mdp_blend_cfg { 1019 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1020 uint32_t is_premultiplied; 1021 }; 1022 struct mdp_mixer_cfg { 1023 uint32_t writeback_format; 1024 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1025 uint32_t alpha; 1026 }; 1027 struct mdss_hw_caps { 1028 uint32_t mdp_rev; 1029 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1030 uint8_t rgb_pipes; 1031 uint8_t vig_pipes; 1032 uint8_t dma_pipes; 1033 uint8_t max_smp_cnt; 1034 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1035 uint8_t smp_per_pipe; 1036 uint32_t features; 1037 }; 1038 struct msmfb_metadata { 1039 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1040 uint32_t op; 1041 uint32_t flags; 1042 union { 1043 struct mdp_misr misr_request; 1044 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1045 struct mdp_blend_cfg blend_cfg; 1046 struct mdp_mixer_cfg mixer_cfg; 1047 uint32_t panel_frame_rate; 1048 uint32_t video_info_code; 1049 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1050 struct mdss_hw_caps caps; 1051 uint8_t secure_en; 1052 int fbmem_ionfd; 1053 } data; 1054 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1055 }; 1056 #define MDP_MAX_FENCE_FD 32 1057 #define MDP_BUF_SYNC_FLAG_WAIT 1 1058 #define MDP_BUF_SYNC_FLAG_RETIRE_FENCE 0x10 1059 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1060 struct mdp_buf_sync { 1061 uint32_t flags; 1062 uint32_t acq_fen_fd_cnt; 1063 uint32_t session_id; 1064 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1065 int * acq_fen_fd; 1066 int * rel_fen_fd; 1067 int * retire_fen_fd; 1068 }; 1069 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1070 struct mdp_async_blit_req_list { 1071 struct mdp_buf_sync sync; 1072 uint32_t count; 1073 struct mdp_blit_req req[]; 1074 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1075 }; 1076 #define MDP_DISPLAY_COMMIT_OVERLAY 1 1077 struct mdp_display_commit { 1078 uint32_t flags; 1079 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1080 uint32_t wait_for_finish; 1081 struct fb_var_screeninfo var; 1082 struct mdp_rect l_roi; 1083 struct mdp_rect r_roi; 1084 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1085 }; 1086 struct mdp_overlay_list { 1087 uint32_t num_overlays; 1088 struct mdp_overlay * * overlay_list; 1089 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1090 uint32_t flags; 1091 uint32_t processed_overlays; 1092 }; 1093 struct mdp_page_protection { 1094 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1095 uint32_t page_protection; 1096 }; 1097 struct mdp_mixer_info { 1098 int pndx; 1099 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1100 int pnum; 1101 int ptype; 1102 int mixer_num; 1103 int z_order; 1104 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1105 }; 1106 #define MAX_PIPE_PER_MIXER 7 1107 struct msmfb_mixer_info_req { 1108 int mixer_num; 1109 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1110 int cnt; 1111 struct mdp_mixer_info info[MAX_PIPE_PER_MIXER]; 1112 }; 1113 enum { 1114 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1115 DISPLAY_SUBSYSTEM_ID, 1116 ROTATOR_SUBSYSTEM_ID, 1117 }; 1118 enum { 1119 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1120 MDP_IOMMU_DOMAIN_CP, 1121 MDP_IOMMU_DOMAIN_NS, 1122 }; 1123 enum { 1124 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1125 MDP_WRITEBACK_MIRROR_OFF, 1126 MDP_WRITEBACK_MIRROR_ON, 1127 MDP_WRITEBACK_MIRROR_PAUSE, 1128 MDP_WRITEBACK_MIRROR_RESUME, 1129 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1130 }; 1131 enum { 1132 MDP_CSC_ITU_R_601, 1133 MDP_CSC_ITU_R_601_FR, 1134 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1135 MDP_CSC_ITU_R_709, 1136 }; 1137 #endif 1138 1139
