1 #ifndef _UAPI_MSM_MDP_H_ 2 #define _UAPI_MSM_MDP_H_ 3 4 #include <linux/types.h> 5 #include <linux/fb.h> 6 7 #define MSMFB_IOCTL_MAGIC 'm' 8 #define MSMFB_GRP_DISP _IOW(MSMFB_IOCTL_MAGIC, 1, unsigned int) 9 #define MSMFB_BLIT _IOW(MSMFB_IOCTL_MAGIC, 2, unsigned int) 10 #define MSMFB_SUSPEND_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 128, unsigned int) 11 #define MSMFB_RESUME_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 129, unsigned int) 12 #define MSMFB_CURSOR _IOW(MSMFB_IOCTL_MAGIC, 130, struct fb_cursor) 13 #define MSMFB_SET_LUT _IOW(MSMFB_IOCTL_MAGIC, 131, struct fb_cmap) 14 #define MSMFB_HISTOGRAM _IOWR(MSMFB_IOCTL_MAGIC, 132, struct mdp_histogram_data) 15 /* new ioctls's for set/get ccs matrix */ 16 #define MSMFB_GET_CCS_MATRIX _IOWR(MSMFB_IOCTL_MAGIC, 133, struct mdp_ccs) 17 #define MSMFB_SET_CCS_MATRIX _IOW(MSMFB_IOCTL_MAGIC, 134, struct mdp_ccs) 18 #define MSMFB_OVERLAY_SET _IOWR(MSMFB_IOCTL_MAGIC, 135, \ 19 struct mdp_overlay) 20 #define MSMFB_OVERLAY_UNSET _IOW(MSMFB_IOCTL_MAGIC, 136, unsigned int) 21 22 #define MSMFB_OVERLAY_PLAY _IOW(MSMFB_IOCTL_MAGIC, 137, \ 23 struct msmfb_overlay_data) 24 #define MSMFB_OVERLAY_QUEUE MSMFB_OVERLAY_PLAY 25 26 #define MSMFB_GET_PAGE_PROTECTION _IOR(MSMFB_IOCTL_MAGIC, 138, \ 27 struct mdp_page_protection) 28 #define MSMFB_SET_PAGE_PROTECTION _IOW(MSMFB_IOCTL_MAGIC, 139, \ 29 struct mdp_page_protection) 30 #define MSMFB_OVERLAY_GET _IOR(MSMFB_IOCTL_MAGIC, 140, \ 31 struct mdp_overlay) 32 #define MSMFB_OVERLAY_PLAY_ENABLE _IOW(MSMFB_IOCTL_MAGIC, 141, unsigned int) 33 #define MSMFB_OVERLAY_BLT _IOWR(MSMFB_IOCTL_MAGIC, 142, \ 34 struct msmfb_overlay_blt) 35 #define MSMFB_OVERLAY_BLT_OFFSET _IOW(MSMFB_IOCTL_MAGIC, 143, unsigned int) 36 #define MSMFB_HISTOGRAM_START _IOR(MSMFB_IOCTL_MAGIC, 144, \ 37 struct mdp_histogram_start_req) 38 #define MSMFB_HISTOGRAM_STOP _IOR(MSMFB_IOCTL_MAGIC, 145, unsigned int) 39 #define MSMFB_NOTIFY_UPDATE _IOWR(MSMFB_IOCTL_MAGIC, 146, unsigned int) 40 41 #define MSMFB_OVERLAY_3D _IOWR(MSMFB_IOCTL_MAGIC, 147, \ 42 struct msmfb_overlay_3d) 43 44 #define MSMFB_MIXER_INFO _IOWR(MSMFB_IOCTL_MAGIC, 148, \ 45 struct msmfb_mixer_info_req) 46 #define MSMFB_OVERLAY_PLAY_WAIT _IOWR(MSMFB_IOCTL_MAGIC, 149, \ 47 struct msmfb_overlay_data) 48 #define MSMFB_WRITEBACK_INIT _IO(MSMFB_IOCTL_MAGIC, 150) 49 #define MSMFB_WRITEBACK_START _IO(MSMFB_IOCTL_MAGIC, 151) 50 #define MSMFB_WRITEBACK_STOP _IO(MSMFB_IOCTL_MAGIC, 152) 51 #define MSMFB_WRITEBACK_QUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 153, \ 52 struct msmfb_data) 53 #define MSMFB_WRITEBACK_DEQUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 154, \ 54 struct msmfb_data) 55 #define MSMFB_WRITEBACK_TERMINATE _IO(MSMFB_IOCTL_MAGIC, 155) 56 #define MSMFB_MDP_PP _IOWR(MSMFB_IOCTL_MAGIC, 156, struct msmfb_mdp_pp) 57 #define MSMFB_OVERLAY_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 160, unsigned int) 58 #define MSMFB_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 161, unsigned int) 59 #define MSMFB_BUFFER_SYNC _IOW(MSMFB_IOCTL_MAGIC, 162, struct mdp_buf_sync) 60 #define MSMFB_OVERLAY_COMMIT _IO(MSMFB_IOCTL_MAGIC, 163) 61 #define MSMFB_DISPLAY_COMMIT _IOW(MSMFB_IOCTL_MAGIC, 164, \ 62 struct mdp_display_commit) 63 #define MSMFB_METADATA_SET _IOW(MSMFB_IOCTL_MAGIC, 165, struct msmfb_metadata) 64 #define MSMFB_METADATA_GET _IOW(MSMFB_IOCTL_MAGIC, 166, struct msmfb_metadata) 65 #define MSMFB_WRITEBACK_SET_MIRRORING_HINT _IOW(MSMFB_IOCTL_MAGIC, 167, \ 66 unsigned int) 67 #define MSMFB_ASYNC_BLIT _IOW(MSMFB_IOCTL_MAGIC, 168, unsigned int) 68 #define MSMFB_OVERLAY_PREPARE _IOWR(MSMFB_IOCTL_MAGIC, 169, \ 69 struct mdp_overlay_list) 70 #define MSMFB_LPM_ENABLE _IOWR(MSMFB_IOCTL_MAGIC, 170, unsigned int) 71 #define MSMFB_SET_PERSISTENCE_MODE _IOWR(MSMFB_IOCTL_MAGIC, 171, unsigned int) 72 73 #define FB_TYPE_3D_PANEL 0x10101010 74 #define MDP_IMGTYPE2_START 0x10000 75 #define MSMFB_DRIVER_VERSION 0xF9E8D701 76 77 /* HW Revisions for different MDSS targets */ 78 #define MDSS_GET_MAJOR(rev) ((rev) >> 28) 79 #define MDSS_GET_MINOR(rev) (((rev) >> 16) & 0xFFF) 80 #define MDSS_GET_STEP(rev) ((rev) & 0xFFFF) 81 #define MDSS_GET_MAJOR_MINOR(rev) ((rev) >> 16) 82 83 #define IS_MDSS_MAJOR_MINOR_SAME(rev1, rev2) \ 84 (MDSS_GET_MAJOR_MINOR((rev1)) == MDSS_GET_MAJOR_MINOR((rev2))) 85 86 #define MDSS_MDP_REV(major, minor, step) \ 87 ((((major) & 0x000F) << 28) | \ 88 (((minor) & 0x0FFF) << 16) | \ 89 ((step) & 0xFFFF)) 90 91 #define MDSS_MDP_HW_REV_100 MDSS_MDP_REV(1, 0, 0) /* 8974 v1.0 */ 92 #define MDSS_MDP_HW_REV_101 MDSS_MDP_REV(1, 1, 0) /* 8x26 v1.0 */ 93 #define MDSS_MDP_HW_REV_101_1 MDSS_MDP_REV(1, 1, 1) /* 8x26 v2.0, 8926 v1.0 */ 94 #define MDSS_MDP_HW_REV_101_2 MDSS_MDP_REV(1, 1, 2) /* 8926 v2.0 */ 95 #define MDSS_MDP_HW_REV_102 MDSS_MDP_REV(1, 2, 0) /* 8974 v2.0 */ 96 #define MDSS_MDP_HW_REV_102_1 MDSS_MDP_REV(1, 2, 1) /* 8974 v3.0 (Pro) */ 97 #define MDSS_MDP_HW_REV_103 MDSS_MDP_REV(1, 3, 0) /* 8084 v1.0 */ 98 #define MDSS_MDP_HW_REV_103_1 MDSS_MDP_REV(1, 3, 1) /* 8084 v1.1 */ 99 #define MDSS_MDP_HW_REV_105 MDSS_MDP_REV(1, 5, 0) /* 8994 v1.0 */ 100 #define MDSS_MDP_HW_REV_106 MDSS_MDP_REV(1, 6, 0) /* 8916 v1.0 */ 101 #define MDSS_MDP_HW_REV_107 MDSS_MDP_REV(1, 7, 0) 102 #define MDSS_MDP_HW_REV_108 MDSS_MDP_REV(1, 8, 0) /* 8939 v1.0 */ 103 #define MDSS_MDP_HW_REV_109 MDSS_MDP_REV(1, 9, 0) /* 8994 v2.0 */ 104 #define MDSS_MDP_HW_REV_110 MDSS_MDP_REV(1, 10, 0) /* 8992 v1.0 */ 105 #define MDSS_MDP_HW_REV_200 MDSS_MDP_REV(2, 0, 0) /* 8092 v1.0 */ 106 107 enum { 108 NOTIFY_UPDATE_INIT, 109 NOTIFY_UPDATE_DEINIT, 110 NOTIFY_UPDATE_START, 111 NOTIFY_UPDATE_STOP, 112 NOTIFY_UPDATE_POWER_OFF, 113 }; 114 115 enum { 116 NOTIFY_TYPE_NO_UPDATE, 117 NOTIFY_TYPE_SUSPEND, 118 NOTIFY_TYPE_UPDATE, 119 NOTIFY_TYPE_BL_UPDATE, 120 NOTIFY_TYPE_BL_AD_ATTEN_UPDATE, 121 }; 122 123 enum { 124 MDP_RGB_565, /* RGB 565 planer */ 125 MDP_XRGB_8888, /* RGB 888 padded */ 126 MDP_Y_CBCR_H2V2, /* Y and CbCr, pseudo planer w/ Cb is in MSB */ 127 MDP_Y_CBCR_H2V2_ADRENO, 128 MDP_ARGB_8888, /* ARGB 888 */ 129 MDP_RGB_888, /* RGB 888 planer */ 130 MDP_Y_CRCB_H2V2, /* Y and CrCb, pseudo planer w/ Cr is in MSB */ 131 MDP_YCRYCB_H2V1, /* YCrYCb interleave */ 132 MDP_CBYCRY_H2V1, /* CbYCrY interleave */ 133 MDP_Y_CRCB_H2V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */ 134 MDP_Y_CBCR_H2V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */ 135 MDP_Y_CRCB_H1V2, 136 MDP_Y_CBCR_H1V2, 137 MDP_RGBA_8888, /* ARGB 888 */ 138 MDP_BGRA_8888, /* ABGR 888 */ 139 MDP_RGBX_8888, /* RGBX 888 */ 140 MDP_Y_CRCB_H2V2_TILE, /* Y and CrCb, pseudo planer tile */ 141 MDP_Y_CBCR_H2V2_TILE, /* Y and CbCr, pseudo planer tile */ 142 MDP_Y_CR_CB_H2V2, /* Y, Cr and Cb, planar */ 143 MDP_Y_CR_CB_GH2V2, /* Y, Cr and Cb, planar aligned to Android YV12 */ 144 MDP_Y_CB_CR_H2V2, /* Y, Cb and Cr, planar */ 145 MDP_Y_CRCB_H1V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */ 146 MDP_Y_CBCR_H1V1, /* Y and CbCr, pseduo planer w/ Cb is in MSB */ 147 MDP_YCRCB_H1V1, /* YCrCb interleave */ 148 MDP_YCBCR_H1V1, /* YCbCr interleave */ 149 MDP_BGR_565, /* BGR 565 planer */ 150 MDP_BGR_888, /* BGR 888 */ 151 MDP_Y_CBCR_H2V2_VENUS, 152 MDP_BGRX_8888, /* BGRX 8888 */ 153 MDP_RGBA_8888_TILE, /* RGBA 8888 in tile format */ 154 MDP_ARGB_8888_TILE, /* ARGB 8888 in tile format */ 155 MDP_ABGR_8888_TILE, /* ABGR 8888 in tile format */ 156 MDP_BGRA_8888_TILE, /* BGRA 8888 in tile format */ 157 MDP_RGBX_8888_TILE, /* RGBX 8888 in tile format */ 158 MDP_XRGB_8888_TILE, /* XRGB 8888 in tile format */ 159 MDP_XBGR_8888_TILE, /* XBGR 8888 in tile format */ 160 MDP_BGRX_8888_TILE, /* BGRX 8888 in tile format */ 161 MDP_YCBYCR_H2V1, /* YCbYCr interleave */ 162 MDP_RGB_565_TILE, /* RGB 565 in tile format */ 163 MDP_BGR_565_TILE, /* BGR 565 in tile format */ 164 MDP_ARGB_1555, /*ARGB 1555*/ 165 MDP_RGBA_5551, /*RGBA 5551*/ 166 MDP_ARGB_4444, /*ARGB 4444*/ 167 MDP_RGBA_4444, /*RGBA 4444*/ 168 MDP_RGB_565_UBWC, 169 MDP_RGBA_8888_UBWC, 170 MDP_Y_CBCR_H2V2_UBWC, 171 MDP_IMGTYPE_LIMIT, 172 MDP_RGB_BORDERFILL, /* border fill pipe */ 173 MDP_FB_FORMAT = MDP_IMGTYPE2_START, /* framebuffer format */ 174 MDP_IMGTYPE_LIMIT2 /* Non valid image type after this enum */ 175 }; 176 177 enum { 178 PMEM_IMG, 179 FB_IMG, 180 }; 181 182 enum { 183 HSIC_HUE = 0, 184 HSIC_SAT, 185 HSIC_INT, 186 HSIC_CON, 187 NUM_HSIC_PARAM, 188 }; 189 190 #define MDSS_MDP_ROT_ONLY 0x80 191 #define MDSS_MDP_RIGHT_MIXER 0x100 192 #define MDSS_MDP_DUAL_PIPE 0x200 193 194 /* mdp_blit_req flag values */ 195 #define MDP_ROT_NOP 0 196 #define MDP_FLIP_LR 0x1 197 #define MDP_FLIP_UD 0x2 198 #define MDP_ROT_90 0x4 199 #define MDP_ROT_180 (MDP_FLIP_UD|MDP_FLIP_LR) 200 #define MDP_ROT_270 (MDP_ROT_90|MDP_FLIP_UD|MDP_FLIP_LR) 201 #define MDP_DITHER 0x8 202 #define MDP_BLUR 0x10 203 #define MDP_BLEND_FG_PREMULT 0x20000 204 #define MDP_IS_FG 0x40000 205 #define MDP_SOLID_FILL 0x00000020 206 #define MDP_VPU_PIPE 0x00000040 207 #define MDP_DEINTERLACE 0x80000000 208 #define MDP_SHARPENING 0x40000000 209 #define MDP_NO_DMA_BARRIER_START 0x20000000 210 #define MDP_NO_DMA_BARRIER_END 0x10000000 211 #define MDP_NO_BLIT 0x08000000 212 #define MDP_BLIT_WITH_DMA_BARRIERS 0x000 213 #define MDP_BLIT_WITH_NO_DMA_BARRIERS \ 214 (MDP_NO_DMA_BARRIER_START | MDP_NO_DMA_BARRIER_END) 215 #define MDP_BLIT_SRC_GEM 0x04000000 216 #define MDP_BLIT_DST_GEM 0x02000000 217 #define MDP_BLIT_NON_CACHED 0x01000000 218 #define MDP_OV_PIPE_SHARE 0x00800000 219 #define MDP_DEINTERLACE_ODD 0x00400000 220 #define MDP_OV_PLAY_NOWAIT 0x00200000 221 #define MDP_SOURCE_ROTATED_90 0x00100000 222 #define MDP_OVERLAY_PP_CFG_EN 0x00080000 223 #define MDP_BACKEND_COMPOSITION 0x00040000 224 #define MDP_BORDERFILL_SUPPORTED 0x00010000 225 #define MDP_SECURE_OVERLAY_SESSION 0x00008000 226 #define MDP_SECURE_DISPLAY_OVERLAY_SESSION 0x00002000 227 #define MDP_OV_PIPE_FORCE_DMA 0x00004000 228 #define MDP_MEMORY_ID_TYPE_FB 0x00001000 229 #define MDP_BWC_EN 0x00000400 230 #define MDP_DECIMATION_EN 0x00000800 231 #define MDP_SMP_FORCE_ALLOC 0x00200000 232 #define MDP_TRANSP_NOP 0xffffffff 233 #define MDP_ALPHA_NOP 0xff 234 235 /* 236 * MDP_DEINTERLACE & MDP_SHARPENING Flags are not valid for MDP3 237 * so using them together for MDP_SMART_BLIT. 238 */ 239 #define MDP_SMART_BLIT 0xC0000000 240 241 #define MDP_FB_PAGE_PROTECTION_NONCACHED (0) 242 #define MDP_FB_PAGE_PROTECTION_WRITECOMBINE (1) 243 #define MDP_FB_PAGE_PROTECTION_WRITETHROUGHCACHE (2) 244 #define MDP_FB_PAGE_PROTECTION_WRITEBACKCACHE (3) 245 #define MDP_FB_PAGE_PROTECTION_WRITEBACKWACACHE (4) 246 /* Sentinel: Don't use! */ 247 #define MDP_FB_PAGE_PROTECTION_INVALID (5) 248 /* Count of the number of MDP_FB_PAGE_PROTECTION_... values. */ 249 #define MDP_NUM_FB_PAGE_PROTECTION_VALUES (5) 250 251 struct mdp_rect { 252 uint32_t x; 253 uint32_t y; 254 uint32_t w; 255 uint32_t h; 256 }; 257 258 struct mdp_img { 259 uint32_t width; 260 uint32_t height; 261 uint32_t format; 262 uint32_t offset; 263 int memory_id; /* the file descriptor */ 264 uint32_t priv; 265 }; 266 267 /* 268 * {3x3} + {3} ccs matrix 269 */ 270 271 #define MDP_CCS_RGB2YUV 0 272 #define MDP_CCS_YUV2RGB 1 273 274 #define MDP_CCS_SIZE 9 275 #define MDP_BV_SIZE 3 276 277 struct mdp_ccs { 278 int direction; /* MDP_CCS_RGB2YUV or YUV2RGB */ 279 uint16_t ccs[MDP_CCS_SIZE]; /* 3x3 color coefficients */ 280 uint16_t bv[MDP_BV_SIZE]; /* 1x3 bias vector */ 281 }; 282 283 struct mdp_csc { 284 int id; 285 uint32_t csc_mv[9]; 286 uint32_t csc_pre_bv[3]; 287 uint32_t csc_post_bv[3]; 288 uint32_t csc_pre_lv[6]; 289 uint32_t csc_post_lv[6]; 290 }; 291 292 /* The version of the mdp_blit_req structure so that 293 * user applications can selectively decide which functionality 294 * to include 295 */ 296 297 #define MDP_BLIT_REQ_VERSION 2 298 299 struct color { 300 uint32_t r; 301 uint32_t g; 302 uint32_t b; 303 uint32_t alpha; 304 }; 305 306 struct mdp_blit_req { 307 struct mdp_img src; 308 struct mdp_img dst; 309 struct mdp_rect src_rect; 310 struct mdp_rect dst_rect; 311 struct color const_color; 312 uint32_t alpha; 313 uint32_t transp_mask; 314 uint32_t flags; 315 int sharpening_strength; /* -127 <--> 127, default 64 */ 316 uint8_t color_space; 317 uint32_t fps; 318 }; 319 320 struct mdp_blit_req_list { 321 uint32_t count; 322 struct mdp_blit_req req[]; 323 }; 324 325 #define MSMFB_DATA_VERSION 2 326 327 struct msmfb_data { 328 uint32_t offset; 329 int memory_id; 330 int id; 331 uint32_t flags; 332 uint32_t priv; 333 uint32_t iova; 334 }; 335 336 #define MSMFB_NEW_REQUEST -1 337 338 struct msmfb_overlay_data { 339 uint32_t id; 340 struct msmfb_data data; 341 uint32_t version_key; 342 struct msmfb_data plane1_data; 343 struct msmfb_data plane2_data; 344 struct msmfb_data dst_data; 345 }; 346 347 struct msmfb_img { 348 uint32_t width; 349 uint32_t height; 350 uint32_t format; 351 }; 352 353 #define MSMFB_WRITEBACK_DEQUEUE_BLOCKING 0x1 354 struct msmfb_writeback_data { 355 struct msmfb_data buf_info; 356 struct msmfb_img img; 357 }; 358 359 #define MDP_PP_OPS_ENABLE 0x1 360 #define MDP_PP_OPS_READ 0x2 361 #define MDP_PP_OPS_WRITE 0x4 362 #define MDP_PP_OPS_DISABLE 0x8 363 #define MDP_PP_IGC_FLAG_ROM0 0x10 364 #define MDP_PP_IGC_FLAG_ROM1 0x20 365 366 #define MDP_PP_PA_HUE_ENABLE 0x10 367 #define MDP_PP_PA_SAT_ENABLE 0x20 368 #define MDP_PP_PA_VAL_ENABLE 0x40 369 #define MDP_PP_PA_CONT_ENABLE 0x80 370 #define MDP_PP_PA_SIX_ZONE_ENABLE 0x100 371 #define MDP_PP_PA_SKIN_ENABLE 0x200 372 #define MDP_PP_PA_SKY_ENABLE 0x400 373 #define MDP_PP_PA_FOL_ENABLE 0x800 374 #define MDP_PP_PA_HUE_MASK 0x1000 375 #define MDP_PP_PA_SAT_MASK 0x2000 376 #define MDP_PP_PA_VAL_MASK 0x4000 377 #define MDP_PP_PA_CONT_MASK 0x8000 378 #define MDP_PP_PA_SIX_ZONE_HUE_MASK 0x10000 379 #define MDP_PP_PA_SIX_ZONE_SAT_MASK 0x20000 380 #define MDP_PP_PA_SIX_ZONE_VAL_MASK 0x40000 381 #define MDP_PP_PA_MEM_COL_SKIN_MASK 0x80000 382 #define MDP_PP_PA_MEM_COL_SKY_MASK 0x100000 383 #define MDP_PP_PA_MEM_COL_FOL_MASK 0x200000 384 #define MDP_PP_PA_MEM_PROTECT_EN 0x400000 385 #define MDP_PP_PA_SAT_ZERO_EXP_EN 0x800000 386 387 #define MDSS_PP_DSPP_CFG 0x000 388 #define MDSS_PP_SSPP_CFG 0x100 389 #define MDSS_PP_LM_CFG 0x200 390 #define MDSS_PP_WB_CFG 0x300 391 392 #define MDSS_PP_ARG_MASK 0x3C00 393 #define MDSS_PP_ARG_NUM 4 394 #define MDSS_PP_ARG_SHIFT 10 395 #define MDSS_PP_LOCATION_MASK 0x0300 396 #define MDSS_PP_LOGICAL_MASK 0x00FF 397 398 #define MDSS_PP_ADD_ARG(var, arg) ((var) | (0x1 << (MDSS_PP_ARG_SHIFT + (arg)))) 399 #define PP_ARG(x, var) ((var) & (0x1 << (MDSS_PP_ARG_SHIFT + (x)))) 400 #define PP_LOCAT(var) ((var) & MDSS_PP_LOCATION_MASK) 401 #define PP_BLOCK(var) ((var) & MDSS_PP_LOGICAL_MASK) 402 403 404 struct mdp_qseed_cfg { 405 uint32_t table_num; 406 uint32_t ops; 407 uint32_t len; 408 uint32_t *data; 409 }; 410 411 struct mdp_sharp_cfg { 412 uint32_t flags; 413 uint32_t strength; 414 uint32_t edge_thr; 415 uint32_t smooth_thr; 416 uint32_t noise_thr; 417 }; 418 419 struct mdp_qseed_cfg_data { 420 uint32_t block; 421 struct mdp_qseed_cfg qseed_data; 422 }; 423 424 #define MDP_OVERLAY_PP_CSC_CFG 0x1 425 #define MDP_OVERLAY_PP_QSEED_CFG 0x2 426 #define MDP_OVERLAY_PP_PA_CFG 0x4 427 #define MDP_OVERLAY_PP_IGC_CFG 0x8 428 #define MDP_OVERLAY_PP_SHARP_CFG 0x10 429 #define MDP_OVERLAY_PP_HIST_CFG 0x20 430 #define MDP_OVERLAY_PP_HIST_LUT_CFG 0x40 431 #define MDP_OVERLAY_PP_PA_V2_CFG 0x80 432 433 #define MDP_CSC_FLAG_ENABLE 0x1 434 #define MDP_CSC_FLAG_YUV_IN 0x2 435 #define MDP_CSC_FLAG_YUV_OUT 0x4 436 437 struct mdp_csc_cfg { 438 /* flags for enable CSC, toggling RGB,YUV input/output */ 439 uint32_t flags; 440 uint32_t csc_mv[9]; 441 uint32_t csc_pre_bv[3]; 442 uint32_t csc_post_bv[3]; 443 uint32_t csc_pre_lv[6]; 444 uint32_t csc_post_lv[6]; 445 }; 446 447 struct mdp_csc_cfg_data { 448 uint32_t block; 449 struct mdp_csc_cfg csc_data; 450 }; 451 452 struct mdp_pa_cfg { 453 uint32_t flags; 454 uint32_t hue_adj; 455 uint32_t sat_adj; 456 uint32_t val_adj; 457 uint32_t cont_adj; 458 }; 459 460 struct mdp_pa_mem_col_cfg { 461 uint32_t color_adjust_p0; 462 uint32_t color_adjust_p1; 463 uint32_t hue_region; 464 uint32_t sat_region; 465 uint32_t val_region; 466 }; 467 468 #define MDP_SIX_ZONE_LUT_SIZE 384 469 470 struct mdp_pa_v2_data { 471 /* Mask bits for PA features */ 472 uint32_t flags; 473 uint32_t global_hue_adj; 474 uint32_t global_sat_adj; 475 uint32_t global_val_adj; 476 uint32_t global_cont_adj; 477 struct mdp_pa_mem_col_cfg skin_cfg; 478 struct mdp_pa_mem_col_cfg sky_cfg; 479 struct mdp_pa_mem_col_cfg fol_cfg; 480 uint32_t six_zone_len; 481 uint32_t six_zone_thresh; 482 uint32_t *six_zone_curve_p0; 483 uint32_t *six_zone_curve_p1; 484 }; 485 486 struct mdp_igc_lut_data { 487 uint32_t block; 488 uint32_t len, ops; 489 uint32_t *c0_c1_data; 490 uint32_t *c2_data; 491 }; 492 493 struct mdp_histogram_cfg { 494 uint32_t ops; 495 uint32_t block; 496 uint8_t frame_cnt; 497 uint8_t bit_mask; 498 uint16_t num_bins; 499 }; 500 501 struct mdp_hist_lut_data { 502 uint32_t block; 503 uint32_t ops; 504 uint32_t len; 505 uint32_t *data; 506 }; 507 508 struct mdp_overlay_pp_params { 509 uint32_t config_ops; 510 struct mdp_csc_cfg csc_cfg; 511 struct mdp_qseed_cfg qseed_cfg[2]; 512 struct mdp_pa_cfg pa_cfg; 513 struct mdp_pa_v2_data pa_v2_cfg; 514 struct mdp_igc_lut_data igc_cfg; 515 struct mdp_sharp_cfg sharp_cfg; 516 struct mdp_histogram_cfg hist_cfg; 517 struct mdp_hist_lut_data hist_lut_cfg; 518 }; 519 520 /** 521 * enum mdss_mdp_blend_op - Different blend operations set by userspace 522 * 523 * @BLEND_OP_NOT_DEFINED: No blend operation defined for the layer. 524 * @BLEND_OP_OPAQUE: Apply a constant blend operation. The layer 525 * would appear opaque in case fg plane alpha is 526 * 0xff. 527 * @BLEND_OP_PREMULTIPLIED: Apply source over blend rule. Layer already has 528 * alpha pre-multiplication done. If fg plane alpha 529 * is less than 0xff, apply modulation as well. This 530 * operation is intended on layers having alpha 531 * channel. 532 * @BLEND_OP_COVERAGE: Apply source over blend rule. Layer is not alpha 533 * pre-multiplied. Apply pre-multiplication. If fg 534 * plane alpha is less than 0xff, apply modulation as 535 * well. 536 * @BLEND_OP_MAX: Used to track maximum blend operation possible by 537 * mdp. 538 */ 539 enum mdss_mdp_blend_op { 540 BLEND_OP_NOT_DEFINED = 0, 541 BLEND_OP_OPAQUE, 542 BLEND_OP_PREMULTIPLIED, 543 BLEND_OP_COVERAGE, 544 BLEND_OP_MAX, 545 }; 546 547 #define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci)) 548 #define MAX_PLANES 4 549 struct mdp_scale_data { 550 uint8_t enable_pxl_ext; 551 552 int init_phase_x[MAX_PLANES]; 553 int phase_step_x[MAX_PLANES]; 554 int init_phase_y[MAX_PLANES]; 555 int phase_step_y[MAX_PLANES]; 556 557 int num_ext_pxls_left[MAX_PLANES]; 558 int num_ext_pxls_right[MAX_PLANES]; 559 int num_ext_pxls_top[MAX_PLANES]; 560 int num_ext_pxls_btm[MAX_PLANES]; 561 562 int left_ftch[MAX_PLANES]; 563 int left_rpt[MAX_PLANES]; 564 int right_ftch[MAX_PLANES]; 565 int right_rpt[MAX_PLANES]; 566 567 int top_rpt[MAX_PLANES]; 568 int btm_rpt[MAX_PLANES]; 569 int top_ftch[MAX_PLANES]; 570 int btm_ftch[MAX_PLANES]; 571 572 uint32_t roi_w[MAX_PLANES]; 573 }; 574 575 /** 576 * enum mdp_overlay_pipe_type - Different pipe type set by userspace 577 * 578 * @PIPE_TYPE_AUTO: Not specified, pipe will be selected according to flags. 579 * @PIPE_TYPE_VIG: VIG pipe. 580 * @PIPE_TYPE_RGB: RGB pipe. 581 * @PIPE_TYPE_DMA: DMA pipe. 582 * @PIPE_TYPE_CURSOR: CURSOR pipe. 583 * @PIPE_TYPE_MAX: Used to track maximum number of pipe type. 584 */ 585 enum mdp_overlay_pipe_type { 586 PIPE_TYPE_AUTO = 0, 587 PIPE_TYPE_VIG, 588 PIPE_TYPE_RGB, 589 PIPE_TYPE_DMA, 590 PIPE_TYPE_CURSOR, 591 PIPE_TYPE_MAX, 592 }; 593 594 /** 595 * struct mdp_overlay - overlay surface structure 596 * @src: Source image information (width, height, format). 597 * @src_rect: Source crop rectangle, portion of image that will be fetched. 598 * This should always be within boundaries of source image. 599 * @dst_rect: Destination rectangle, the position and size of image on screen. 600 * This should always be within panel boundaries. 601 * @z_order: Blending stage to occupy in display, if multiple layers are 602 * present, highest z_order usually means the top most visible 603 * layer. The range acceptable is from 0-3 to support blending 604 * up to 4 layers. 605 * @is_fg: This flag is used to disable blending of any layers with z_order 606 * less than this overlay. It means that any layers with z_order 607 * less than this layer will not be blended and will be replaced 608 * by the background border color. 609 * @alpha: Used to set plane opacity. The range can be from 0-255, where 610 * 0 means completely transparent and 255 means fully opaque. 611 * @transp_mask: Color used as color key for transparency. Any pixel in fetched 612 * image matching this color will be transparent when blending. 613 * The color should be in same format as the source image format. 614 * @flags: This is used to customize operation of overlay. See MDP flags 615 * for more information. 616 * @pipe_type: Used to specify the type of overlay pipe. 617 * @user_data: DEPRECATED* Used to store user application specific information. 618 * @bg_color: Solid color used to fill the overlay surface when no source 619 * buffer is provided. 620 * @horz_deci: Horizontal decimation value, this indicates the amount of pixels 621 * dropped for each pixel that is fetched from a line. The value 622 * given should be power of two of decimation amount. 623 * 0: no decimation 624 * 1: decimate by 2 (drop 1 pixel for each pixel fetched) 625 * 2: decimate by 4 (drop 3 pixels for each pixel fetched) 626 * 3: decimate by 8 (drop 7 pixels for each pixel fetched) 627 * 4: decimate by 16 (drop 15 pixels for each pixel fetched) 628 * @vert_deci: Vertical decimation value, this indicates the amount of lines 629 * dropped for each line that is fetched from overlay. The value 630 * given should be power of two of decimation amount. 631 * 0: no decimation 632 * 1: decimation by 2 (drop 1 line for each line fetched) 633 * 2: decimation by 4 (drop 3 lines for each line fetched) 634 * 3: decimation by 8 (drop 7 lines for each line fetched) 635 * 4: decimation by 16 (drop 15 lines for each line fetched) 636 * @overlay_pp_cfg: Overlay post processing configuration, for more information 637 * see struct mdp_overlay_pp_params. 638 * @priority: Priority is returned by the driver when overlay is set for the 639 * first time. It indicates the priority of the underlying pipe 640 * serving the overlay. This priority can be used by user-space 641 * in source split when pipes are re-used and shuffled around to 642 * reduce fallbacks. 643 */ 644 struct mdp_overlay { 645 struct msmfb_img src; 646 struct mdp_rect src_rect; 647 struct mdp_rect dst_rect; 648 uint32_t z_order; /* stage number */ 649 uint32_t is_fg; /* control alpha & transp */ 650 uint32_t alpha; 651 uint32_t blend_op; 652 uint32_t transp_mask; 653 uint32_t flags; 654 uint32_t pipe_type; 655 uint32_t id; 656 uint8_t priority; 657 uint32_t user_data[6]; 658 uint32_t bg_color; 659 uint8_t horz_deci; 660 uint8_t vert_deci; 661 struct mdp_overlay_pp_params overlay_pp_cfg; 662 struct mdp_scale_data scale; 663 uint8_t color_space; 664 }; 665 666 struct msmfb_overlay_3d { 667 uint32_t is_3d; 668 uint32_t width; 669 uint32_t height; 670 }; 671 672 673 struct msmfb_overlay_blt { 674 uint32_t enable; 675 uint32_t offset; 676 uint32_t width; 677 uint32_t height; 678 uint32_t bpp; 679 }; 680 681 struct mdp_histogram { 682 uint32_t frame_cnt; 683 uint32_t bin_cnt; 684 uint32_t *r; 685 uint32_t *g; 686 uint32_t *b; 687 }; 688 689 #define MISR_CRC_BATCH_SIZE 32 690 enum { 691 DISPLAY_MISR_EDP, 692 DISPLAY_MISR_DSI0, 693 DISPLAY_MISR_DSI1, 694 DISPLAY_MISR_HDMI, 695 DISPLAY_MISR_LCDC, 696 DISPLAY_MISR_MDP, 697 DISPLAY_MISR_ATV, 698 DISPLAY_MISR_DSI_CMD, 699 DISPLAY_MISR_MAX 700 }; 701 702 enum { 703 MISR_OP_NONE, 704 MISR_OP_SFM, 705 MISR_OP_MFM, 706 MISR_OP_BM, 707 MISR_OP_MAX 708 }; 709 710 struct mdp_misr { 711 uint32_t block_id; 712 uint32_t frame_count; 713 uint32_t crc_op_mode; 714 uint32_t crc_value[MISR_CRC_BATCH_SIZE]; 715 }; 716 717 /* 718 719 mdp_block_type defines the identifiers for pipes in MDP 4.3 and up 720 721 MDP_BLOCK_RESERVED is provided for backward compatibility and is 722 deprecated. It corresponds to DMA_P. So MDP_BLOCK_DMA_P should be used 723 instead. 724 725 MDP_LOGICAL_BLOCK_DISP_0 identifies the display pipe which fb0 uses, 726 same for others. 727 728 */ 729 730 enum { 731 MDP_BLOCK_RESERVED = 0, 732 MDP_BLOCK_OVERLAY_0, 733 MDP_BLOCK_OVERLAY_1, 734 MDP_BLOCK_VG_1, 735 MDP_BLOCK_VG_2, 736 MDP_BLOCK_RGB_1, 737 MDP_BLOCK_RGB_2, 738 MDP_BLOCK_DMA_P, 739 MDP_BLOCK_DMA_S, 740 MDP_BLOCK_DMA_E, 741 MDP_BLOCK_OVERLAY_2, 742 MDP_LOGICAL_BLOCK_DISP_0 = 0x10, 743 MDP_LOGICAL_BLOCK_DISP_1, 744 MDP_LOGICAL_BLOCK_DISP_2, 745 MDP_BLOCK_MAX, 746 }; 747 748 /* 749 * mdp_histogram_start_req is used to provide the parameters for 750 * histogram start request 751 */ 752 753 struct mdp_histogram_start_req { 754 uint32_t block; 755 uint8_t frame_cnt; 756 uint8_t bit_mask; 757 uint16_t num_bins; 758 }; 759 760 /* 761 * mdp_histogram_data is used to return the histogram data, once 762 * the histogram is done/stopped/cance 763 */ 764 765 struct mdp_histogram_data { 766 uint32_t block; 767 uint32_t bin_cnt; 768 uint32_t *c0; 769 uint32_t *c1; 770 uint32_t *c2; 771 uint32_t *extra_info; 772 }; 773 774 struct mdp_pcc_coeff { 775 uint32_t c, r, g, b, rr, gg, bb, rg, gb, rb, rgb_0, rgb_1; 776 }; 777 778 struct mdp_pcc_cfg_data { 779 uint32_t block; 780 uint32_t ops; 781 struct mdp_pcc_coeff r, g, b; 782 }; 783 784 #define MDP_GAMUT_TABLE_NUM 8 785 786 enum { 787 mdp_lut_igc, 788 mdp_lut_pgc, 789 mdp_lut_hist, 790 mdp_lut_rgb, 791 mdp_lut_max, 792 }; 793 794 struct mdp_ar_gc_lut_data { 795 uint32_t x_start; 796 uint32_t slope; 797 uint32_t offset; 798 }; 799 800 struct mdp_pgc_lut_data { 801 uint32_t block; 802 uint32_t flags; 803 uint8_t num_r_stages; 804 uint8_t num_g_stages; 805 uint8_t num_b_stages; 806 struct mdp_ar_gc_lut_data *r_data; 807 struct mdp_ar_gc_lut_data *g_data; 808 struct mdp_ar_gc_lut_data *b_data; 809 }; 810 811 /* 812 * mdp_rgb_lut_data is used to provide parameters for configuring the 813 * generic RGB lut in case of gamma correction or other LUT updation usecases 814 */ 815 struct mdp_rgb_lut_data { 816 uint32_t flags; 817 uint32_t lut_type; 818 struct fb_cmap cmap; 819 }; 820 821 enum { 822 mdp_rgb_lut_gc, 823 mdp_rgb_lut_hist, 824 }; 825 826 struct mdp_lut_cfg_data { 827 uint32_t lut_type; 828 union { 829 struct mdp_igc_lut_data igc_lut_data; 830 struct mdp_pgc_lut_data pgc_lut_data; 831 struct mdp_hist_lut_data hist_lut_data; 832 struct mdp_rgb_lut_data rgb_lut_data; 833 } data; 834 }; 835 836 struct mdp_bl_scale_data { 837 uint32_t min_lvl; 838 uint32_t scale; 839 }; 840 841 struct mdp_pa_cfg_data { 842 uint32_t block; 843 struct mdp_pa_cfg pa_data; 844 }; 845 846 struct mdp_pa_v2_cfg_data { 847 uint32_t block; 848 struct mdp_pa_v2_data pa_v2_data; 849 }; 850 851 struct mdp_dither_cfg_data { 852 uint32_t block; 853 uint32_t flags; 854 uint32_t g_y_depth; 855 uint32_t r_cr_depth; 856 uint32_t b_cb_depth; 857 }; 858 859 struct mdp_gamut_cfg_data { 860 uint32_t block; 861 uint32_t flags; 862 uint32_t gamut_first; 863 uint32_t tbl_size[MDP_GAMUT_TABLE_NUM]; 864 uint16_t *r_tbl[MDP_GAMUT_TABLE_NUM]; 865 uint16_t *g_tbl[MDP_GAMUT_TABLE_NUM]; 866 uint16_t *b_tbl[MDP_GAMUT_TABLE_NUM]; 867 }; 868 869 struct mdp_calib_config_data { 870 uint32_t ops; 871 uint32_t addr; 872 uint32_t data; 873 }; 874 875 struct mdp_calib_config_buffer { 876 uint32_t ops; 877 uint32_t size; 878 uint32_t *buffer; 879 }; 880 881 struct mdp_calib_dcm_state { 882 uint32_t ops; 883 uint32_t dcm_state; 884 }; 885 886 struct mdp_pp_init_data { 887 uint32_t init_request; 888 }; 889 890 enum { 891 MDP_PP_DISABLE, 892 MDP_PP_ENABLE, 893 }; 894 895 enum { 896 DCM_UNINIT, 897 DCM_UNBLANK, 898 DCM_ENTER, 899 DCM_EXIT, 900 DCM_BLANK, 901 DTM_ENTER, 902 DTM_EXIT, 903 }; 904 905 #define MDSS_PP_SPLIT_LEFT_ONLY 0x10000000 906 #define MDSS_PP_SPLIT_RIGHT_ONLY 0x20000000 907 #define MDSS_PP_SPLIT_MASK 0x30000000 908 909 #define MDSS_MAX_BL_BRIGHTNESS 255 910 #define AD_BL_LIN_LEN 256 911 #define AD_BL_ATT_LUT_LEN 33 912 913 #define MDSS_AD_MODE_AUTO_BL 0x0 914 #define MDSS_AD_MODE_AUTO_STR 0x1 915 #define MDSS_AD_MODE_TARG_STR 0x3 916 #define MDSS_AD_MODE_MAN_STR 0x7 917 #define MDSS_AD_MODE_CALIB 0xF 918 919 #define MDP_PP_AD_INIT 0x10 920 #define MDP_PP_AD_CFG 0x20 921 922 struct mdss_ad_init { 923 uint32_t asym_lut[33]; 924 uint32_t color_corr_lut[33]; 925 uint8_t i_control[2]; 926 uint16_t black_lvl; 927 uint16_t white_lvl; 928 uint8_t var; 929 uint8_t limit_ampl; 930 uint8_t i_dither; 931 uint8_t slope_max; 932 uint8_t slope_min; 933 uint8_t dither_ctl; 934 uint8_t format; 935 uint8_t auto_size; 936 uint16_t frame_w; 937 uint16_t frame_h; 938 uint8_t logo_v; 939 uint8_t logo_h; 940 uint32_t alpha; 941 uint32_t alpha_base; 942 uint32_t bl_lin_len; 943 uint32_t bl_att_len; 944 uint32_t *bl_lin; 945 uint32_t *bl_lin_inv; 946 uint32_t *bl_att_lut; 947 }; 948 949 #define MDSS_AD_BL_CTRL_MODE_EN 1 950 #define MDSS_AD_BL_CTRL_MODE_DIS 0 951 struct mdss_ad_cfg { 952 uint32_t mode; 953 uint32_t al_calib_lut[33]; 954 uint16_t backlight_min; 955 uint16_t backlight_max; 956 uint16_t backlight_scale; 957 uint16_t amb_light_min; 958 uint16_t filter[2]; 959 uint16_t calib[4]; 960 uint8_t strength_limit; 961 uint8_t t_filter_recursion; 962 uint16_t stab_itr; 963 uint32_t bl_ctrl_mode; 964 }; 965 966 /* ops uses standard MDP_PP_* flags */ 967 struct mdss_ad_init_cfg { 968 uint32_t ops; 969 union { 970 struct mdss_ad_init init; 971 struct mdss_ad_cfg cfg; 972 } params; 973 }; 974 975 /* mode uses MDSS_AD_MODE_* flags */ 976 struct mdss_ad_input { 977 uint32_t mode; 978 union { 979 uint32_t amb_light; 980 uint32_t strength; 981 uint32_t calib_bl; 982 } in; 983 uint32_t output; 984 }; 985 986 #define MDSS_CALIB_MODE_BL 0x1 987 struct mdss_calib_cfg { 988 uint32_t ops; 989 uint32_t calib_mask; 990 }; 991 992 enum { 993 mdp_op_pcc_cfg, 994 mdp_op_csc_cfg, 995 mdp_op_lut_cfg, 996 mdp_op_qseed_cfg, 997 mdp_bl_scale_cfg, 998 mdp_op_pa_cfg, 999 mdp_op_pa_v2_cfg, 1000 mdp_op_dither_cfg, 1001 mdp_op_gamut_cfg, 1002 mdp_op_calib_cfg, 1003 mdp_op_ad_cfg, 1004 mdp_op_ad_input, 1005 mdp_op_calib_mode, 1006 mdp_op_calib_buffer, 1007 mdp_op_calib_dcm_state, 1008 mdp_op_max, 1009 mdp_op_pp_init_cfg, 1010 }; 1011 1012 enum { 1013 WB_FORMAT_NV12, 1014 WB_FORMAT_RGB_565, 1015 WB_FORMAT_RGB_888, 1016 WB_FORMAT_xRGB_8888, 1017 WB_FORMAT_ARGB_8888, 1018 WB_FORMAT_BGRA_8888, 1019 WB_FORMAT_BGRX_8888, 1020 WB_FORMAT_ARGB_8888_INPUT_ALPHA /* Need to support */ 1021 }; 1022 1023 struct msmfb_mdp_pp { 1024 uint32_t op; 1025 union { 1026 struct mdp_pcc_cfg_data pcc_cfg_data; 1027 struct mdp_csc_cfg_data csc_cfg_data; 1028 struct mdp_lut_cfg_data lut_cfg_data; 1029 struct mdp_qseed_cfg_data qseed_cfg_data; 1030 struct mdp_bl_scale_data bl_scale_data; 1031 struct mdp_pa_cfg_data pa_cfg_data; 1032 struct mdp_pa_v2_cfg_data pa_v2_cfg_data; 1033 struct mdp_dither_cfg_data dither_cfg_data; 1034 struct mdp_gamut_cfg_data gamut_cfg_data; 1035 struct mdp_calib_config_data calib_cfg; 1036 struct mdss_ad_init_cfg ad_init_cfg; 1037 struct mdss_calib_cfg mdss_calib_cfg; 1038 struct mdss_ad_input ad_input; 1039 struct mdp_calib_config_buffer calib_buffer; 1040 struct mdp_calib_dcm_state calib_dcm; 1041 struct mdp_pp_init_data init_data; 1042 } data; 1043 }; 1044 1045 #define FB_METADATA_VIDEO_INFO_CODE_SUPPORT 1 1046 enum { 1047 metadata_op_none, 1048 metadata_op_base_blend, 1049 metadata_op_frame_rate, 1050 metadata_op_vic, 1051 metadata_op_wb_format, 1052 metadata_op_wb_secure, 1053 metadata_op_get_caps, 1054 metadata_op_crc, 1055 metadata_op_get_ion_fd, 1056 metadata_op_max 1057 }; 1058 1059 struct mdp_blend_cfg { 1060 uint32_t is_premultiplied; 1061 }; 1062 1063 struct mdp_mixer_cfg { 1064 uint32_t writeback_format; 1065 uint32_t alpha; 1066 }; 1067 1068 struct mdss_hw_caps { 1069 uint32_t mdp_rev; 1070 uint8_t rgb_pipes; 1071 uint8_t vig_pipes; 1072 uint8_t dma_pipes; 1073 uint8_t max_smp_cnt; 1074 uint8_t smp_per_pipe; 1075 uint32_t features; 1076 }; 1077 1078 struct msmfb_metadata { 1079 uint32_t op; 1080 uint32_t flags; 1081 union { 1082 struct mdp_misr misr_request; 1083 struct mdp_blend_cfg blend_cfg; 1084 struct mdp_mixer_cfg mixer_cfg; 1085 uint32_t panel_frame_rate; 1086 uint32_t video_info_code; 1087 struct mdss_hw_caps caps; 1088 uint8_t secure_en; 1089 int fbmem_ionfd; 1090 } data; 1091 }; 1092 1093 #define MDP_MAX_FENCE_FD 32 1094 #define MDP_BUF_SYNC_FLAG_WAIT 1 1095 #define MDP_BUF_SYNC_FLAG_RETIRE_FENCE 0x10 1096 1097 struct mdp_buf_sync { 1098 uint32_t flags; 1099 uint32_t acq_fen_fd_cnt; 1100 uint32_t session_id; 1101 int *acq_fen_fd; 1102 int *rel_fen_fd; 1103 int *retire_fen_fd; 1104 }; 1105 1106 struct mdp_async_blit_req_list { 1107 struct mdp_buf_sync sync; 1108 uint32_t count; 1109 struct mdp_blit_req req[]; 1110 }; 1111 1112 #define MDP_DISPLAY_COMMIT_OVERLAY 1 1113 1114 struct mdp_display_commit { 1115 uint32_t flags; 1116 uint32_t wait_for_finish; 1117 struct fb_var_screeninfo var; 1118 struct mdp_rect l_roi; 1119 struct mdp_rect r_roi; 1120 }; 1121 1122 /** 1123 * struct mdp_overlay_list - argument for ioctl MSMFB_OVERLAY_PREPARE 1124 * @num_overlays: Number of overlay layers as part of the frame. 1125 * @overlay_list: Pointer to a list of overlay structures identifying 1126 * the layers as part of the frame 1127 * @flags: Flags can be used to extend behavior. 1128 * @processed_overlays: Output parameter indicating how many pipes were 1129 * successful. If there are no errors this number should 1130 * match num_overlays. Otherwise it will indicate the last 1131 * successful index for overlay that couldn't be set. 1132 */ 1133 struct mdp_overlay_list { 1134 uint32_t num_overlays; 1135 struct mdp_overlay **overlay_list; 1136 uint32_t flags; 1137 uint32_t processed_overlays; 1138 }; 1139 1140 struct mdp_page_protection { 1141 uint32_t page_protection; 1142 }; 1143 1144 1145 struct mdp_mixer_info { 1146 int pndx; 1147 int pnum; 1148 int ptype; 1149 int mixer_num; 1150 int z_order; 1151 }; 1152 1153 #define MAX_PIPE_PER_MIXER 7 1154 1155 struct msmfb_mixer_info_req { 1156 int mixer_num; 1157 int cnt; 1158 struct mdp_mixer_info info[MAX_PIPE_PER_MIXER]; 1159 }; 1160 1161 enum { 1162 DISPLAY_SUBSYSTEM_ID, 1163 ROTATOR_SUBSYSTEM_ID, 1164 }; 1165 1166 enum { 1167 MDP_IOMMU_DOMAIN_CP, 1168 MDP_IOMMU_DOMAIN_NS, 1169 }; 1170 1171 enum { 1172 MDP_WRITEBACK_MIRROR_OFF, 1173 MDP_WRITEBACK_MIRROR_ON, 1174 MDP_WRITEBACK_MIRROR_PAUSE, 1175 MDP_WRITEBACK_MIRROR_RESUME, 1176 }; 1177 1178 enum { 1179 MDP_CSC_ITU_R_601, 1180 MDP_CSC_ITU_R_601_FR, 1181 MDP_CSC_ITU_R_709, 1182 }; 1183 #endif /*_UAPI_MSM_MDP_H_*/ 1184
