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      1 #ifndef MSM_CAM_ISPIF_H
      2 #define MSM_CAM_ISPIF_H
      3 
      4 #define CSID_VERSION_V20                      0x02000011
      5 #define CSID_VERSION_V22                      0x02001000
      6 #define CSID_VERSION_V30                      0x30000000
      7 #define CSID_VERSION_V3                      0x30000000
      8 
      9 enum msm_ispif_vfe_intf {
     10 	VFE0,
     11 	VFE1,
     12 	VFE_MAX
     13 };
     14 #define VFE0_MASK    (1 << VFE0)
     15 #define VFE1_MASK    (1 << VFE1)
     16 
     17 enum msm_ispif_intftype {
     18 	PIX0,
     19 	RDI0,
     20 	PIX1,
     21 	RDI1,
     22 	RDI2,
     23 	INTF_MAX
     24 };
     25 #define MAX_PARAM_ENTRIES (INTF_MAX * 2)
     26 #define MAX_CID_CH	8
     27 
     28 #define PIX0_MASK (1 << PIX0)
     29 #define PIX1_MASK (1 << PIX1)
     30 #define RDI0_MASK (1 << RDI0)
     31 #define RDI1_MASK (1 << RDI1)
     32 #define RDI2_MASK (1 << RDI2)
     33 
     34 
     35 enum msm_ispif_vc {
     36 	VC0,
     37 	VC1,
     38 	VC2,
     39 	VC3,
     40 	VC_MAX
     41 };
     42 
     43 enum msm_ispif_cid {
     44 	CID0,
     45 	CID1,
     46 	CID2,
     47 	CID3,
     48 	CID4,
     49 	CID5,
     50 	CID6,
     51 	CID7,
     52 	CID8,
     53 	CID9,
     54 	CID10,
     55 	CID11,
     56 	CID12,
     57 	CID13,
     58 	CID14,
     59 	CID15,
     60 	CID_MAX
     61 };
     62 
     63 enum msm_ispif_csid {
     64 	CSID0,
     65 	CSID1,
     66 	CSID2,
     67 	CSID3,
     68 	CSID_MAX
     69 };
     70 
     71 struct msm_ispif_params_entry {
     72 	enum msm_ispif_vfe_intf vfe_intf;
     73 	enum msm_ispif_intftype intftype;
     74 	int num_cids;
     75 	enum msm_ispif_cid cids[3];
     76 	enum msm_ispif_csid csid;
     77 	int crop_enable;
     78 	uint16_t crop_start_pixel;
     79 	uint16_t crop_end_pixel;
     80 };
     81 
     82 struct msm_ispif_param_data {
     83 	uint32_t num;
     84 	struct msm_ispif_params_entry entries[MAX_PARAM_ENTRIES];
     85 };
     86 
     87 struct msm_isp_info {
     88 	uint32_t max_resolution;
     89 	uint32_t id;
     90 	uint32_t ver;
     91 };
     92 
     93 struct msm_ispif_vfe_info {
     94 	int num_vfe;
     95 	struct msm_isp_info info[VFE_MAX];
     96 };
     97 
     98 enum ispif_cfg_type_t {
     99 	ISPIF_CLK_ENABLE,
    100 	ISPIF_CLK_DISABLE,
    101 	ISPIF_INIT,
    102 	ISPIF_CFG,
    103 	ISPIF_START_FRAME_BOUNDARY,
    104 	ISPIF_RESTART_FRAME_BOUNDARY,
    105 	ISPIF_STOP_FRAME_BOUNDARY,
    106 	ISPIF_STOP_IMMEDIATELY,
    107 	ISPIF_RELEASE,
    108 	ISPIF_ENABLE_REG_DUMP,
    109 	ISPIF_SET_VFE_INFO,
    110 };
    111 
    112 struct ispif_cfg_data {
    113 	enum ispif_cfg_type_t cfg_type;
    114 	union {
    115 		int reg_dump;                        /* ISPIF_ENABLE_REG_DUMP */
    116 		uint32_t csid_version;               /* ISPIF_INIT */
    117 		struct msm_ispif_vfe_info vfe_info;  /* ISPIF_SET_VFE_INFO */
    118 		struct msm_ispif_param_data params;  /* CFG, START, STOP */
    119 	};
    120 };
    121 
    122 #define VIDIOC_MSM_ISPIF_CFG \
    123 	_IOWR('V', BASE_VIDIOC_PRIVATE, struct ispif_cfg_data)
    124 
    125 #endif /* MSM_CAM_ISPIF_H */
    126