1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef _MSM_MDP_H_ 20 #define _MSM_MDP_H_ 21 #include <stdint.h> 22 #include <linux/fb.h> 23 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 24 #define MSMFB_IOCTL_MAGIC 'm' 25 #define MSMFB_GRP_DISP _IOW(MSMFB_IOCTL_MAGIC, 1, unsigned int) 26 #define MSMFB_BLIT _IOW(MSMFB_IOCTL_MAGIC, 2, unsigned int) 27 #define MSMFB_SUSPEND_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 128, unsigned int) 28 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 29 #define MSMFB_RESUME_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 129, unsigned int) 30 #define MSMFB_CURSOR _IOW(MSMFB_IOCTL_MAGIC, 130, struct fb_cursor) 31 #define MSMFB_SET_LUT _IOW(MSMFB_IOCTL_MAGIC, 131, struct fb_cmap) 32 #define MSMFB_HISTOGRAM _IOWR(MSMFB_IOCTL_MAGIC, 132, struct mdp_histogram_data) 33 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 34 #define MSMFB_GET_CCS_MATRIX _IOWR(MSMFB_IOCTL_MAGIC, 133, struct mdp_ccs) 35 #define MSMFB_SET_CCS_MATRIX _IOW(MSMFB_IOCTL_MAGIC, 134, struct mdp_ccs) 36 #define MSMFB_OVERLAY_SET _IOWR(MSMFB_IOCTL_MAGIC, 135, struct mdp_overlay) 37 #define MSMFB_OVERLAY_UNSET _IOW(MSMFB_IOCTL_MAGIC, 136, unsigned int) 38 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 39 #define MSMFB_OVERLAY_PLAY _IOW(MSMFB_IOCTL_MAGIC, 137, struct msmfb_overlay_data) 40 #define MSMFB_OVERLAY_QUEUE MSMFB_OVERLAY_PLAY 41 #define MSMFB_GET_PAGE_PROTECTION _IOR(MSMFB_IOCTL_MAGIC, 138, struct mdp_page_protection) 42 #define MSMFB_SET_PAGE_PROTECTION _IOW(MSMFB_IOCTL_MAGIC, 139, struct mdp_page_protection) 43 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 44 #define MSMFB_OVERLAY_GET _IOR(MSMFB_IOCTL_MAGIC, 140, struct mdp_overlay) 45 #define MSMFB_OVERLAY_PLAY_ENABLE _IOW(MSMFB_IOCTL_MAGIC, 141, unsigned int) 46 #define MSMFB_OVERLAY_BLT _IOWR(MSMFB_IOCTL_MAGIC, 142, struct msmfb_overlay_blt) 47 #define MSMFB_OVERLAY_BLT_OFFSET _IOW(MSMFB_IOCTL_MAGIC, 143, unsigned int) 48 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 49 #define MSMFB_HISTOGRAM_START _IOR(MSMFB_IOCTL_MAGIC, 144, struct mdp_histogram_start_req) 50 #define MSMFB_HISTOGRAM_STOP _IOR(MSMFB_IOCTL_MAGIC, 145, unsigned int) 51 #define MSMFB_NOTIFY_UPDATE _IOWR(MSMFB_IOCTL_MAGIC, 146, unsigned int) 52 #define MSMFB_OVERLAY_3D _IOWR(MSMFB_IOCTL_MAGIC, 147, struct msmfb_overlay_3d) 53 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 54 #define MSMFB_MIXER_INFO _IOWR(MSMFB_IOCTL_MAGIC, 148, struct msmfb_mixer_info_req) 55 #define MSMFB_OVERLAY_PLAY_WAIT _IOWR(MSMFB_IOCTL_MAGIC, 149, struct msmfb_overlay_data) 56 #define MSMFB_WRITEBACK_INIT _IO(MSMFB_IOCTL_MAGIC, 150) 57 #define MSMFB_WRITEBACK_START _IO(MSMFB_IOCTL_MAGIC, 151) 58 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 59 #define MSMFB_WRITEBACK_STOP _IO(MSMFB_IOCTL_MAGIC, 152) 60 #define MSMFB_WRITEBACK_QUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 153, struct msmfb_data) 61 #define MSMFB_WRITEBACK_DEQUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 154, struct msmfb_data) 62 #define MSMFB_WRITEBACK_TERMINATE _IO(MSMFB_IOCTL_MAGIC, 155) 63 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 64 #define MSMFB_MDP_PP _IOWR(MSMFB_IOCTL_MAGIC, 156, struct msmfb_mdp_pp) 65 #define MSMFB_OVERLAY_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 160, unsigned int) 66 #define MSMFB_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 161, unsigned int) 67 #define MSMFB_BUFFER_SYNC _IOW(MSMFB_IOCTL_MAGIC, 162, struct mdp_buf_sync) 68 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 69 #define MSMFB_OVERLAY_COMMIT _IO(MSMFB_IOCTL_MAGIC, 163) 70 #define MSMFB_DISPLAY_COMMIT _IOW(MSMFB_IOCTL_MAGIC, 164, struct mdp_display_commit) 71 #define MSMFB_METADATA_SET _IOW(MSMFB_IOCTL_MAGIC, 165, struct msmfb_metadata) 72 #define MSMFB_METADATA_GET _IOW(MSMFB_IOCTL_MAGIC, 166, struct msmfb_metadata) 73 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 74 #define MSMFB_WRITEBACK_SET_MIRRORING_HINT _IOW(MSMFB_IOCTL_MAGIC, 167, unsigned int) 75 #define MSMFB_ASYNC_BLIT _IOW(MSMFB_IOCTL_MAGIC, 168, unsigned int) 76 #define MSMFB_OVERLAY_PREPARE _IOWR(MSMFB_IOCTL_MAGIC, 169, struct mdp_overlay_list) 77 #define MSMFB_LPM_ENABLE _IOWR(MSMFB_IOCTL_MAGIC, 170, unsigned int) 78 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 79 #define MSMFB_MDP_PP_GET_FEATURE_VERSION _IOWR(MSMFB_IOCTL_MAGIC, 171, struct mdp_pp_feature_version) 80 #define FB_TYPE_3D_PANEL 0x10101010 81 #define MDP_IMGTYPE2_START 0x10000 82 #define MSMFB_DRIVER_VERSION 0xF9E8D701 83 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 84 #define MDP_IMGTYPE_END 0x100 85 #define MDSS_GET_MAJOR(rev) ((rev) >> 28) 86 #define MDSS_GET_MINOR(rev) (((rev) >> 16) & 0xFFF) 87 #define MDSS_GET_STEP(rev) ((rev) & 0xFFFF) 88 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 89 #define MDSS_GET_MAJOR_MINOR(rev) ((rev) >> 16) 90 #define IS_MDSS_MAJOR_MINOR_SAME(rev1,rev2) (MDSS_GET_MAJOR_MINOR((rev1)) == MDSS_GET_MAJOR_MINOR((rev2))) 91 #define MDSS_MDP_REV(major,minor,step) ((((major) & 0x000F) << 28) | (((minor) & 0x0FFF) << 16) | ((step) & 0xFFFF)) 92 #define MDSS_MDP_HW_REV_100 MDSS_MDP_REV(1, 0, 0) 93 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 94 #define MDSS_MDP_HW_REV_101 MDSS_MDP_REV(1, 1, 0) 95 #define MDSS_MDP_HW_REV_101_1 MDSS_MDP_REV(1, 1, 1) 96 #define MDSS_MDP_HW_REV_101_2 MDSS_MDP_REV(1, 1, 2) 97 #define MDSS_MDP_HW_REV_102 MDSS_MDP_REV(1, 2, 0) 98 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 99 #define MDSS_MDP_HW_REV_102_1 MDSS_MDP_REV(1, 2, 1) 100 #define MDSS_MDP_HW_REV_103 MDSS_MDP_REV(1, 3, 0) 101 #define MDSS_MDP_HW_REV_103_1 MDSS_MDP_REV(1, 3, 1) 102 #define MDSS_MDP_HW_REV_105 MDSS_MDP_REV(1, 5, 0) 103 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 104 #define MDSS_MDP_HW_REV_106 MDSS_MDP_REV(1, 6, 0) 105 #define MDSS_MDP_HW_REV_107 MDSS_MDP_REV(1, 7, 0) 106 #define MDSS_MDP_HW_REV_107_1 MDSS_MDP_REV(1, 7, 1) 107 #define MDSS_MDP_HW_REV_107_2 MDSS_MDP_REV(1, 7, 2) 108 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 109 #define MDSS_MDP_HW_REV_108 MDSS_MDP_REV(1, 8, 0) 110 #define MDSS_MDP_HW_REV_109 MDSS_MDP_REV(1, 9, 0) 111 #define MDSS_MDP_HW_REV_110 MDSS_MDP_REV(1, 10, 0) 112 #define MDSS_MDP_HW_REV_200 MDSS_MDP_REV(2, 0, 0) 113 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 114 #define MDSS_MDP_HW_REV_112 MDSS_MDP_REV(1, 12, 0) 115 #define MDSS_MDP_HW_REV_114 MDSS_MDP_REV(1, 14, 0) 116 #define MDSS_MDP_HW_REV_115 MDSS_MDP_REV(1, 15, 0) 117 #define MDSS_MDP_HW_REV_116 MDSS_MDP_REV(1, 16, 0) 118 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 119 #define MDSS_MDP_HW_REV_300 MDSS_MDP_REV(3, 0, 0) 120 #define MDSS_MDP_HW_REV_301 MDSS_MDP_REV(3, 0, 1) 121 #define MDSS_MDP_HW_REV_320 MDSS_MDP_REV(3, 2, 0) 122 #define MDSS_MDP_HW_REV_330 MDSS_MDP_REV(3, 3, 0) 123 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 124 enum { 125 NOTIFY_UPDATE_INIT, 126 NOTIFY_UPDATE_DEINIT, 127 NOTIFY_UPDATE_START, 128 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 129 NOTIFY_UPDATE_STOP, 130 NOTIFY_UPDATE_POWER_OFF, 131 }; 132 enum { 133 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 134 NOTIFY_TYPE_NO_UPDATE, 135 NOTIFY_TYPE_SUSPEND, 136 NOTIFY_TYPE_UPDATE, 137 NOTIFY_TYPE_BL_UPDATE, 138 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 139 NOTIFY_TYPE_BL_AD_ATTEN_UPDATE, 140 }; 141 enum { 142 MDP_RGB_565, 143 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 144 MDP_XRGB_8888, 145 MDP_Y_CBCR_H2V2, 146 MDP_Y_CBCR_H2V2_ADRENO, 147 MDP_ARGB_8888, 148 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 149 MDP_RGB_888, 150 MDP_Y_CRCB_H2V2, 151 MDP_YCRYCB_H2V1, 152 MDP_CBYCRY_H2V1, 153 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 154 MDP_Y_CRCB_H2V1, 155 MDP_Y_CBCR_H2V1, 156 MDP_Y_CRCB_H1V2, 157 MDP_Y_CBCR_H1V2, 158 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 159 MDP_RGBA_8888, 160 MDP_BGRA_8888, 161 MDP_RGBX_8888, 162 MDP_Y_CRCB_H2V2_TILE, 163 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 164 MDP_Y_CBCR_H2V2_TILE, 165 MDP_Y_CR_CB_H2V2, 166 MDP_Y_CR_CB_GH2V2, 167 MDP_Y_CB_CR_H2V2, 168 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 169 MDP_Y_CRCB_H1V1, 170 MDP_Y_CBCR_H1V1, 171 MDP_YCRCB_H1V1, 172 MDP_YCBCR_H1V1, 173 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 174 MDP_BGR_565, 175 MDP_BGR_888, 176 MDP_Y_CBCR_H2V2_VENUS, 177 MDP_BGRX_8888, 178 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 179 MDP_RGBA_8888_TILE, 180 MDP_ARGB_8888_TILE, 181 MDP_ABGR_8888_TILE, 182 MDP_BGRA_8888_TILE, 183 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 184 MDP_RGBX_8888_TILE, 185 MDP_XRGB_8888_TILE, 186 MDP_XBGR_8888_TILE, 187 MDP_BGRX_8888_TILE, 188 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 189 MDP_YCBYCR_H2V1, 190 MDP_RGB_565_TILE, 191 MDP_BGR_565_TILE, 192 MDP_ARGB_1555, 193 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 194 MDP_RGBA_5551, 195 MDP_ARGB_4444, 196 MDP_RGBA_4444, 197 MDP_RGB_565_UBWC, 198 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 199 MDP_RGBA_8888_UBWC, 200 MDP_Y_CBCR_H2V2_UBWC, 201 MDP_RGBX_8888_UBWC, 202 MDP_Y_CRCB_H2V2_VENUS, 203 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 204 MDP_IMGTYPE_LIMIT, 205 MDP_RGB_BORDERFILL, 206 MDP_XRGB_1555, 207 MDP_RGBX_5551, 208 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 209 MDP_XRGB_4444, 210 MDP_RGBX_4444, 211 MDP_ABGR_1555, 212 MDP_BGRA_5551, 213 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 214 MDP_XBGR_1555, 215 MDP_BGRX_5551, 216 MDP_ABGR_4444, 217 MDP_BGRA_4444, 218 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 219 MDP_XBGR_4444, 220 MDP_BGRX_4444, 221 MDP_ABGR_8888, 222 MDP_XBGR_8888, 223 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 224 MDP_RGBA_1010102, 225 MDP_ARGB_2101010, 226 MDP_RGBX_1010102, 227 MDP_XRGB_2101010, 228 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 229 MDP_BGRA_1010102, 230 MDP_ABGR_2101010, 231 MDP_BGRX_1010102, 232 MDP_XBGR_2101010, 233 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 234 MDP_RGBA_1010102_UBWC, 235 MDP_RGBX_1010102_UBWC, 236 MDP_Y_CBCR_H2V2_P010, 237 MDP_Y_CBCR_H2V2_TP10_UBWC, 238 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 239 MDP_CRYCBY_H2V1, 240 MDP_IMGTYPE_LIMIT1 = MDP_IMGTYPE_END, 241 MDP_FB_FORMAT = MDP_IMGTYPE2_START, 242 MDP_IMGTYPE_LIMIT2 243 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 244 }; 245 #define MDP_CRYCBY_H2V1 MDP_CRYCBY_H2V1 246 enum { 247 PMEM_IMG, 248 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 249 FB_IMG, 250 }; 251 enum { 252 HSIC_HUE = 0, 253 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 254 HSIC_SAT, 255 HSIC_INT, 256 HSIC_CON, 257 NUM_HSIC_PARAM, 258 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 259 }; 260 enum mdss_mdp_max_bw_mode { 261 MDSS_MAX_BW_LIMIT_DEFAULT = 0x1, 262 MDSS_MAX_BW_LIMIT_CAMERA = 0x2, 263 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 264 MDSS_MAX_BW_LIMIT_HFLIP = 0x4, 265 MDSS_MAX_BW_LIMIT_VFLIP = 0x8, 266 }; 267 #define MDSS_MDP_ROT_ONLY 0x80 268 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 269 #define MDSS_MDP_RIGHT_MIXER 0x100 270 #define MDSS_MDP_DUAL_PIPE 0x200 271 #define MDP_ROT_NOP 0 272 #define MDP_FLIP_LR 0x1 273 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 274 #define MDP_FLIP_UD 0x2 275 #define MDP_ROT_90 0x4 276 #define MDP_ROT_180 (MDP_FLIP_UD | MDP_FLIP_LR) 277 #define MDP_ROT_270 (MDP_ROT_90 | MDP_FLIP_UD | MDP_FLIP_LR) 278 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 279 #define MDP_DITHER 0x8 280 #define MDP_BLUR 0x10 281 #define MDP_BLEND_FG_PREMULT 0x20000 282 #define MDP_IS_FG 0x40000 283 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 284 #define MDP_SOLID_FILL 0x00000020 285 #define MDP_VPU_PIPE 0x00000040 286 #define MDP_DEINTERLACE 0x80000000 287 #define MDP_SHARPENING 0x40000000 288 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 289 #define MDP_NO_DMA_BARRIER_START 0x20000000 290 #define MDP_NO_DMA_BARRIER_END 0x10000000 291 #define MDP_NO_BLIT 0x08000000 292 #define MDP_BLIT_WITH_DMA_BARRIERS 0x000 293 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 294 #define MDP_BLIT_WITH_NO_DMA_BARRIERS (MDP_NO_DMA_BARRIER_START | MDP_NO_DMA_BARRIER_END) 295 #define MDP_BLIT_SRC_GEM 0x04000000 296 #define MDP_BLIT_DST_GEM 0x02000000 297 #define MDP_BLIT_NON_CACHED 0x01000000 298 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 299 #define MDP_OV_PIPE_SHARE 0x00800000 300 #define MDP_DEINTERLACE_ODD 0x00400000 301 #define MDP_OV_PLAY_NOWAIT 0x00200000 302 #define MDP_SOURCE_ROTATED_90 0x00100000 303 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 304 #define MDP_OVERLAY_PP_CFG_EN 0x00080000 305 #define MDP_BACKEND_COMPOSITION 0x00040000 306 #define MDP_BORDERFILL_SUPPORTED 0x00010000 307 #define MDP_SECURE_OVERLAY_SESSION 0x00008000 308 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 309 #define MDP_SECURE_DISPLAY_OVERLAY_SESSION 0x00002000 310 #define MDP_OV_PIPE_FORCE_DMA 0x00004000 311 #define MDP_MEMORY_ID_TYPE_FB 0x00001000 312 #define MDP_BWC_EN 0x00000400 313 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 314 #define MDP_DECIMATION_EN 0x00000800 315 #define MDP_SMP_FORCE_ALLOC 0x00200000 316 #define MDP_TRANSP_NOP 0xffffffff 317 #define MDP_ALPHA_NOP 0xff 318 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 319 #define MDP_FB_PAGE_PROTECTION_NONCACHED (0) 320 #define MDP_FB_PAGE_PROTECTION_WRITECOMBINE (1) 321 #define MDP_FB_PAGE_PROTECTION_WRITETHROUGHCACHE (2) 322 #define MDP_FB_PAGE_PROTECTION_WRITEBACKCACHE (3) 323 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 324 #define MDP_FB_PAGE_PROTECTION_WRITEBACKWACACHE (4) 325 #define MDP_FB_PAGE_PROTECTION_INVALID (5) 326 #define MDP_NUM_FB_PAGE_PROTECTION_VALUES (5) 327 #define MDP_DEEP_COLOR_YUV444 0x1 328 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 329 #define MDP_DEEP_COLOR_RGB30B 0x2 330 #define MDP_DEEP_COLOR_RGB36B 0x4 331 #define MDP_DEEP_COLOR_RGB48B 0x8 332 struct mdp_rect { 333 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 334 uint32_t x; 335 uint32_t y; 336 uint32_t w; 337 uint32_t h; 338 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 339 }; 340 struct mdp_img { 341 uint32_t width; 342 uint32_t height; 343 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 344 uint32_t format; 345 uint32_t offset; 346 int memory_id; 347 uint32_t priv; 348 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 349 }; 350 struct mult_factor { 351 uint32_t numer; 352 uint32_t denom; 353 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 354 }; 355 #define MDP_CCS_RGB2YUV 0 356 #define MDP_CCS_YUV2RGB 1 357 #define MDP_CCS_SIZE 9 358 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 359 #define MDP_BV_SIZE 3 360 struct mdp_ccs { 361 int direction; 362 uint16_t ccs[MDP_CCS_SIZE]; 363 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 364 uint16_t bv[MDP_BV_SIZE]; 365 }; 366 struct mdp_csc { 367 int id; 368 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 369 uint32_t csc_mv[9]; 370 uint32_t csc_pre_bv[3]; 371 uint32_t csc_post_bv[3]; 372 uint32_t csc_pre_lv[6]; 373 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 374 uint32_t csc_post_lv[6]; 375 }; 376 #define MDP_BLIT_REQ_VERSION 3 377 struct color { 378 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 379 uint32_t r; 380 uint32_t g; 381 uint32_t b; 382 uint32_t alpha; 383 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 384 }; 385 struct mdp_blit_req { 386 struct mdp_img src; 387 struct mdp_img dst; 388 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 389 struct mdp_rect src_rect; 390 struct mdp_rect dst_rect; 391 struct color const_color; 392 uint32_t alpha; 393 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 394 uint32_t transp_mask; 395 uint32_t flags; 396 int sharpening_strength; 397 uint8_t color_space; 398 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 399 uint32_t fps; 400 }; 401 struct mdp_blit_req_list { 402 uint32_t count; 403 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 404 struct mdp_blit_req req[]; 405 }; 406 #define MSMFB_DATA_VERSION 2 407 struct msmfb_data { 408 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 409 uint32_t offset; 410 int memory_id; 411 int id; 412 uint32_t flags; 413 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 414 uint32_t priv; 415 uint32_t iova; 416 }; 417 #define MSMFB_NEW_REQUEST - 1 418 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 419 struct msmfb_overlay_data { 420 uint32_t id; 421 struct msmfb_data data; 422 uint32_t version_key; 423 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 424 struct msmfb_data plane1_data; 425 struct msmfb_data plane2_data; 426 struct msmfb_data dst_data; 427 }; 428 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 429 struct msmfb_img { 430 uint32_t width; 431 uint32_t height; 432 uint32_t format; 433 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 434 }; 435 #define MSMFB_WRITEBACK_DEQUEUE_BLOCKING 0x1 436 struct msmfb_writeback_data { 437 struct msmfb_data buf_info; 438 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 439 struct msmfb_img img; 440 }; 441 #define MDP_PP_OPS_ENABLE 0x1 442 #define MDP_PP_OPS_READ 0x2 443 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 444 #define MDP_PP_OPS_WRITE 0x4 445 #define MDP_PP_OPS_DISABLE 0x8 446 #define MDP_PP_IGC_FLAG_ROM0 0x10 447 #define MDP_PP_IGC_FLAG_ROM1 0x20 448 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 449 #define MDSS_PP_DSPP_CFG 0x000 450 #define MDSS_PP_SSPP_CFG 0x100 451 #define MDSS_PP_LM_CFG 0x200 452 #define MDSS_PP_WB_CFG 0x300 453 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 454 #define MDSS_PP_ARG_MASK 0x3C00 455 #define MDSS_PP_ARG_NUM 4 456 #define MDSS_PP_ARG_SHIFT 10 457 #define MDSS_PP_LOCATION_MASK 0x0300 458 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 459 #define MDSS_PP_LOGICAL_MASK 0x00FF 460 #define MDSS_PP_ADD_ARG(var,arg) ((var) | (0x1 << (MDSS_PP_ARG_SHIFT + (arg)))) 461 #define PP_ARG(x,var) ((var) & (0x1 << (MDSS_PP_ARG_SHIFT + (x)))) 462 #define PP_LOCAT(var) ((var) & MDSS_PP_LOCATION_MASK) 463 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 464 #define PP_BLOCK(var) ((var) & MDSS_PP_LOGICAL_MASK) 465 struct mdp_qseed_cfg { 466 uint32_t table_num; 467 uint32_t ops; 468 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 469 uint32_t len; 470 uint32_t * data; 471 }; 472 struct mdp_sharp_cfg { 473 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 474 uint32_t flags; 475 uint32_t strength; 476 uint32_t edge_thr; 477 uint32_t smooth_thr; 478 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 479 uint32_t noise_thr; 480 }; 481 struct mdp_qseed_cfg_data { 482 uint32_t block; 483 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 484 struct mdp_qseed_cfg qseed_data; 485 }; 486 #define MDP_OVERLAY_PP_CSC_CFG 0x1 487 #define MDP_OVERLAY_PP_QSEED_CFG 0x2 488 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 489 #define MDP_OVERLAY_PP_PA_CFG 0x4 490 #define MDP_OVERLAY_PP_IGC_CFG 0x8 491 #define MDP_OVERLAY_PP_SHARP_CFG 0x10 492 #define MDP_OVERLAY_PP_HIST_CFG 0x20 493 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 494 #define MDP_OVERLAY_PP_HIST_LUT_CFG 0x40 495 #define MDP_OVERLAY_PP_PA_V2_CFG 0x80 496 #define MDP_OVERLAY_PP_PCC_CFG 0x100 497 #define MDP_CSC_FLAG_ENABLE 0x1 498 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 499 #define MDP_CSC_FLAG_YUV_IN 0x2 500 #define MDP_CSC_FLAG_YUV_OUT 0x4 501 #define MDP_CSC_MATRIX_COEFF_SIZE 9 502 #define MDP_CSC_CLAMP_SIZE 6 503 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 504 #define MDP_CSC_BIAS_SIZE 3 505 struct mdp_csc_cfg { 506 uint32_t flags; 507 uint32_t csc_mv[MDP_CSC_MATRIX_COEFF_SIZE]; 508 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 509 uint32_t csc_pre_bv[MDP_CSC_BIAS_SIZE]; 510 uint32_t csc_post_bv[MDP_CSC_BIAS_SIZE]; 511 uint32_t csc_pre_lv[MDP_CSC_CLAMP_SIZE]; 512 uint32_t csc_post_lv[MDP_CSC_CLAMP_SIZE]; 513 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 514 }; 515 struct mdp_csc_cfg_data { 516 uint32_t block; 517 struct mdp_csc_cfg csc_data; 518 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 519 }; 520 struct mdp_pa_cfg { 521 uint32_t flags; 522 uint32_t hue_adj; 523 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 524 uint32_t sat_adj; 525 uint32_t val_adj; 526 uint32_t cont_adj; 527 }; 528 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 529 struct mdp_pa_mem_col_cfg { 530 uint32_t color_adjust_p0; 531 uint32_t color_adjust_p1; 532 uint32_t hue_region; 533 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 534 uint32_t sat_region; 535 uint32_t val_region; 536 }; 537 #define MDP_SIX_ZONE_LUT_SIZE 384 538 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 539 #define MDP_PP_PA_HUE_ENABLE 0x10 540 #define MDP_PP_PA_SAT_ENABLE 0x20 541 #define MDP_PP_PA_VAL_ENABLE 0x40 542 #define MDP_PP_PA_CONT_ENABLE 0x80 543 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 544 #define MDP_PP_PA_SIX_ZONE_ENABLE 0x100 545 #define MDP_PP_PA_SKIN_ENABLE 0x200 546 #define MDP_PP_PA_SKY_ENABLE 0x400 547 #define MDP_PP_PA_FOL_ENABLE 0x800 548 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 549 #define MDP_PP_PA_MEM_PROT_HUE_EN 0x1 550 #define MDP_PP_PA_MEM_PROT_SAT_EN 0x2 551 #define MDP_PP_PA_MEM_PROT_VAL_EN 0x4 552 #define MDP_PP_PA_MEM_PROT_CONT_EN 0x8 553 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 554 #define MDP_PP_PA_MEM_PROT_SIX_EN 0x10 555 #define MDP_PP_PA_MEM_PROT_BLEND_EN 0x20 556 #define MDP_PP_PA_HUE_MASK 0x1000 557 #define MDP_PP_PA_SAT_MASK 0x2000 558 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 559 #define MDP_PP_PA_VAL_MASK 0x4000 560 #define MDP_PP_PA_CONT_MASK 0x8000 561 #define MDP_PP_PA_SIX_ZONE_HUE_MASK 0x10000 562 #define MDP_PP_PA_SIX_ZONE_SAT_MASK 0x20000 563 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 564 #define MDP_PP_PA_SIX_ZONE_VAL_MASK 0x40000 565 #define MDP_PP_PA_MEM_COL_SKIN_MASK 0x80000 566 #define MDP_PP_PA_MEM_COL_SKY_MASK 0x100000 567 #define MDP_PP_PA_MEM_COL_FOL_MASK 0x200000 568 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 569 #define MDP_PP_PA_MEM_PROTECT_EN 0x400000 570 #define MDP_PP_PA_SAT_ZERO_EXP_EN 0x800000 571 #define MDP_PP_PA_LEFT_HOLD 0x1 572 #define MDP_PP_PA_RIGHT_HOLD 0x2 573 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 574 struct mdp_pa_v2_data { 575 uint32_t flags; 576 uint32_t global_hue_adj; 577 uint32_t global_sat_adj; 578 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 579 uint32_t global_val_adj; 580 uint32_t global_cont_adj; 581 struct mdp_pa_mem_col_cfg skin_cfg; 582 struct mdp_pa_mem_col_cfg sky_cfg; 583 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 584 struct mdp_pa_mem_col_cfg fol_cfg; 585 uint32_t six_zone_len; 586 uint32_t six_zone_thresh; 587 uint32_t * six_zone_curve_p0; 588 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 589 uint32_t * six_zone_curve_p1; 590 }; 591 struct mdp_pa_mem_col_data_v1_7 { 592 uint32_t color_adjust_p0; 593 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 594 uint32_t color_adjust_p1; 595 uint32_t color_adjust_p2; 596 uint32_t blend_gain; 597 uint8_t sat_hold; 598 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 599 uint8_t val_hold; 600 uint32_t hue_region; 601 uint32_t sat_region; 602 uint32_t val_region; 603 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 604 }; 605 struct mdp_pa_data_v1_7 { 606 uint32_t mode; 607 uint32_t global_hue_adj; 608 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 609 uint32_t global_sat_adj; 610 uint32_t global_val_adj; 611 uint32_t global_cont_adj; 612 struct mdp_pa_mem_col_data_v1_7 skin_cfg; 613 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 614 struct mdp_pa_mem_col_data_v1_7 sky_cfg; 615 struct mdp_pa_mem_col_data_v1_7 fol_cfg; 616 uint32_t six_zone_thresh; 617 uint32_t six_zone_adj_p0; 618 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 619 uint32_t six_zone_adj_p1; 620 uint8_t six_zone_sat_hold; 621 uint8_t six_zone_val_hold; 622 uint32_t six_zone_len; 623 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 624 uint32_t * six_zone_curve_p0; 625 uint32_t * six_zone_curve_p1; 626 }; 627 struct mdp_pa_v2_cfg_data { 628 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 629 uint32_t version; 630 uint32_t block; 631 uint32_t flags; 632 struct mdp_pa_v2_data pa_v2_data; 633 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 634 void * cfg_payload; 635 }; 636 enum { 637 mdp_igc_rec601 = 1, 638 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 639 mdp_igc_rec709, 640 mdp_igc_srgb, 641 mdp_igc_custom, 642 mdp_igc_rec_max, 643 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 644 }; 645 struct mdp_igc_lut_data { 646 uint32_t block; 647 uint32_t version; 648 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 649 uint32_t len, ops; 650 uint32_t * c0_c1_data; 651 uint32_t * c2_data; 652 void * cfg_payload; 653 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 654 }; 655 struct mdp_igc_lut_data_v1_7 { 656 uint32_t table_fmt; 657 uint32_t len; 658 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 659 uint32_t * c0_c1_data; 660 uint32_t * c2_data; 661 }; 662 struct mdp_igc_lut_data_payload { 663 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 664 uint32_t table_fmt; 665 uint32_t len; 666 uint64_t c0_c1_data; 667 uint64_t c2_data; 668 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 669 uint32_t strength; 670 }; 671 struct mdp_histogram_cfg { 672 uint32_t ops; 673 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 674 uint32_t block; 675 uint8_t frame_cnt; 676 uint8_t bit_mask; 677 uint16_t num_bins; 678 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 679 }; 680 struct mdp_hist_lut_data_v1_7 { 681 uint32_t len; 682 uint32_t * data; 683 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 684 }; 685 struct mdp_hist_lut_data { 686 uint32_t block; 687 uint32_t version; 688 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 689 uint32_t hist_lut_first; 690 uint32_t ops; 691 uint32_t len; 692 uint32_t * data; 693 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 694 void * cfg_payload; 695 }; 696 struct mdp_pcc_coeff { 697 uint32_t c, r, g, b, rr, gg, bb, rg, gb, rb, rgb_0, rgb_1; 698 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 699 }; 700 struct mdp_pcc_coeff_v1_7 { 701 uint32_t c, r, g, b, rg, gb, rb, rgb; 702 }; 703 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 704 struct mdp_pcc_data_v1_7 { 705 struct mdp_pcc_coeff_v1_7 r, g, b; 706 }; 707 struct mdp_pcc_cfg_data { 708 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 709 uint32_t version; 710 uint32_t block; 711 uint32_t ops; 712 struct mdp_pcc_coeff r, g, b; 713 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 714 void * cfg_payload; 715 }; 716 enum { 717 mdp_lut_igc, 718 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 719 mdp_lut_pgc, 720 mdp_lut_hist, 721 mdp_lut_rgb, 722 mdp_lut_max, 723 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 724 }; 725 struct mdp_overlay_pp_params { 726 uint32_t config_ops; 727 struct mdp_csc_cfg csc_cfg; 728 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 729 struct mdp_qseed_cfg qseed_cfg[2]; 730 struct mdp_pa_cfg pa_cfg; 731 struct mdp_pa_v2_data pa_v2_cfg; 732 struct mdp_igc_lut_data igc_cfg; 733 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 734 struct mdp_sharp_cfg sharp_cfg; 735 struct mdp_histogram_cfg hist_cfg; 736 struct mdp_hist_lut_data hist_lut_cfg; 737 struct mdp_pa_v2_cfg_data pa_v2_cfg_data; 738 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 739 struct mdp_pcc_cfg_data pcc_cfg_data; 740 }; 741 enum mdss_mdp_blend_op { 742 BLEND_OP_NOT_DEFINED = 0, 743 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 744 BLEND_OP_OPAQUE, 745 BLEND_OP_PREMULTIPLIED, 746 BLEND_OP_COVERAGE, 747 BLEND_OP_MAX, 748 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 749 }; 750 #define DECIMATED_DIMENSION(dim,deci) (((dim) + ((1 << (deci)) - 1)) >> (deci)) 751 #define MAX_PLANES 4 752 struct mdp_scale_data { 753 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 754 uint8_t enable_pxl_ext; 755 int init_phase_x[MAX_PLANES]; 756 int phase_step_x[MAX_PLANES]; 757 int init_phase_y[MAX_PLANES]; 758 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 759 int phase_step_y[MAX_PLANES]; 760 int num_ext_pxls_left[MAX_PLANES]; 761 int num_ext_pxls_right[MAX_PLANES]; 762 int num_ext_pxls_top[MAX_PLANES]; 763 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 764 int num_ext_pxls_btm[MAX_PLANES]; 765 int left_ftch[MAX_PLANES]; 766 int left_rpt[MAX_PLANES]; 767 int right_ftch[MAX_PLANES]; 768 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 769 int right_rpt[MAX_PLANES]; 770 int top_rpt[MAX_PLANES]; 771 int btm_rpt[MAX_PLANES]; 772 int top_ftch[MAX_PLANES]; 773 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 774 int btm_ftch[MAX_PLANES]; 775 uint32_t roi_w[MAX_PLANES]; 776 }; 777 enum mdp_overlay_pipe_type { 778 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 779 PIPE_TYPE_AUTO = 0, 780 PIPE_TYPE_VIG, 781 PIPE_TYPE_RGB, 782 PIPE_TYPE_DMA, 783 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 784 PIPE_TYPE_CURSOR, 785 PIPE_TYPE_MAX, 786 }; 787 struct mdp_overlay { 788 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 789 struct msmfb_img src; 790 struct mdp_rect src_rect; 791 struct mdp_rect dst_rect; 792 uint32_t z_order; 793 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 794 uint32_t is_fg; 795 uint32_t alpha; 796 uint32_t blend_op; 797 uint32_t transp_mask; 798 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 799 uint32_t flags; 800 uint32_t pipe_type; 801 uint32_t id; 802 uint8_t priority; 803 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 804 uint32_t user_data[6]; 805 uint32_t bg_color; 806 uint8_t horz_deci; 807 uint8_t vert_deci; 808 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 809 struct mdp_overlay_pp_params overlay_pp_cfg; 810 struct mdp_scale_data scale; 811 uint8_t color_space; 812 uint32_t frame_rate; 813 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 814 }; 815 struct msmfb_overlay_3d { 816 uint32_t is_3d; 817 uint32_t width; 818 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 819 uint32_t height; 820 }; 821 struct msmfb_overlay_blt { 822 uint32_t enable; 823 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 824 uint32_t offset; 825 uint32_t width; 826 uint32_t height; 827 uint32_t bpp; 828 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 829 }; 830 struct mdp_histogram { 831 uint32_t frame_cnt; 832 uint32_t bin_cnt; 833 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 834 uint32_t * r; 835 uint32_t * g; 836 uint32_t * b; 837 }; 838 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 839 #define MISR_CRC_BATCH_SIZE 32 840 enum { 841 DISPLAY_MISR_EDP, 842 DISPLAY_MISR_DSI0, 843 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 844 DISPLAY_MISR_DSI1, 845 DISPLAY_MISR_HDMI, 846 DISPLAY_MISR_LCDC, 847 DISPLAY_MISR_MDP, 848 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 849 DISPLAY_MISR_ATV, 850 DISPLAY_MISR_DSI_CMD, 851 DISPLAY_MISR_MAX 852 }; 853 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 854 enum { 855 MISR_OP_NONE, 856 MISR_OP_SFM, 857 MISR_OP_MFM, 858 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 859 MISR_OP_BM, 860 MISR_OP_MAX 861 }; 862 struct mdp_misr { 863 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 864 uint32_t block_id; 865 uint32_t frame_count; 866 uint32_t crc_op_mode; 867 uint32_t crc_value[MISR_CRC_BATCH_SIZE]; 868 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 869 }; 870 enum { 871 MDP_BLOCK_RESERVED = 0, 872 MDP_BLOCK_OVERLAY_0, 873 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 874 MDP_BLOCK_OVERLAY_1, 875 MDP_BLOCK_VG_1, 876 MDP_BLOCK_VG_2, 877 MDP_BLOCK_RGB_1, 878 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 879 MDP_BLOCK_RGB_2, 880 MDP_BLOCK_DMA_P, 881 MDP_BLOCK_DMA_S, 882 MDP_BLOCK_DMA_E, 883 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 884 MDP_BLOCK_OVERLAY_2, 885 MDP_LOGICAL_BLOCK_DISP_0 = 0x10, 886 MDP_LOGICAL_BLOCK_DISP_1, 887 MDP_LOGICAL_BLOCK_DISP_2, 888 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 889 MDP_BLOCK_MAX, 890 }; 891 struct mdp_histogram_start_req { 892 uint32_t block; 893 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 894 uint8_t frame_cnt; 895 uint8_t bit_mask; 896 uint16_t num_bins; 897 }; 898 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 899 struct mdp_histogram_data { 900 uint32_t block; 901 uint32_t bin_cnt; 902 uint32_t * c0; 903 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 904 uint32_t * c1; 905 uint32_t * c2; 906 uint32_t * extra_info; 907 }; 908 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 909 #define GC_LUT_ENTRIES_V1_7 512 910 struct mdp_ar_gc_lut_data { 911 uint32_t x_start; 912 uint32_t slope; 913 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 914 uint32_t offset; 915 }; 916 #define MDP_PP_PGC_ROUNDING_ENABLE 0x10 917 struct mdp_pgc_lut_data { 918 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 919 uint32_t version; 920 uint32_t block; 921 uint32_t flags; 922 uint8_t num_r_stages; 923 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 924 uint8_t num_g_stages; 925 uint8_t num_b_stages; 926 struct mdp_ar_gc_lut_data * r_data; 927 struct mdp_ar_gc_lut_data * g_data; 928 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 929 struct mdp_ar_gc_lut_data * b_data; 930 void * cfg_payload; 931 }; 932 #define PGC_LUT_ENTRIES 1024 933 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 934 struct mdp_pgc_lut_data_v1_7 { 935 uint32_t len; 936 uint32_t * c0_data; 937 uint32_t * c1_data; 938 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 939 uint32_t * c2_data; 940 }; 941 struct mdp_rgb_lut_data { 942 uint32_t flags; 943 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 944 uint32_t lut_type; 945 struct fb_cmap cmap; 946 }; 947 enum { 948 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 949 mdp_rgb_lut_gc, 950 mdp_rgb_lut_hist, 951 }; 952 struct mdp_lut_cfg_data { 953 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 954 uint32_t lut_type; 955 union { 956 struct mdp_igc_lut_data igc_lut_data; 957 struct mdp_pgc_lut_data pgc_lut_data; 958 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 959 struct mdp_hist_lut_data hist_lut_data; 960 struct mdp_rgb_lut_data rgb_lut_data; 961 } data; 962 }; 963 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 964 struct mdp_bl_scale_data { 965 uint32_t min_lvl; 966 uint32_t scale; 967 }; 968 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 969 struct mdp_pa_cfg_data { 970 uint32_t block; 971 struct mdp_pa_cfg pa_data; 972 }; 973 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 974 #define MDP_DITHER_DATA_V1_7_SZ 16 975 struct mdp_dither_data_v1_7 { 976 uint32_t g_y_depth; 977 uint32_t r_cr_depth; 978 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 979 uint32_t b_cb_depth; 980 uint32_t len; 981 uint32_t data[MDP_DITHER_DATA_V1_7_SZ]; 982 uint32_t temporal_en; 983 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 984 }; 985 struct mdp_pa_dither_data { 986 uint64_t data_flags; 987 uint32_t matrix_sz; 988 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 989 uint64_t matrix_data; 990 uint32_t strength; 991 uint32_t offset_en; 992 }; 993 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 994 struct mdp_dither_cfg_data { 995 uint32_t version; 996 uint32_t block; 997 uint32_t flags; 998 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 999 uint32_t mode; 1000 uint32_t g_y_depth; 1001 uint32_t r_cr_depth; 1002 uint32_t b_cb_depth; 1003 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1004 void * cfg_payload; 1005 }; 1006 #define MDP_GAMUT_TABLE_NUM 8 1007 #define MDP_GAMUT_TABLE_NUM_V1_7 4 1008 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1009 #define MDP_GAMUT_SCALE_OFF_TABLE_NUM 3 1010 #define MDP_GAMUT_TABLE_V1_7_SZ 1229 1011 #define MDP_GAMUT_SCALE_OFF_SZ 16 1012 #define MDP_GAMUT_TABLE_V1_7_COARSE_SZ 32 1013 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1014 struct mdp_gamut_cfg_data { 1015 uint32_t block; 1016 uint32_t flags; 1017 uint32_t version; 1018 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1019 uint32_t gamut_first; 1020 uint32_t tbl_size[MDP_GAMUT_TABLE_NUM]; 1021 uint16_t * r_tbl[MDP_GAMUT_TABLE_NUM]; 1022 uint16_t * g_tbl[MDP_GAMUT_TABLE_NUM]; 1023 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1024 uint16_t * b_tbl[MDP_GAMUT_TABLE_NUM]; 1025 void * cfg_payload; 1026 }; 1027 enum { 1028 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1029 mdp_gamut_fine_mode = 0x1, 1030 mdp_gamut_coarse_mode, 1031 }; 1032 struct mdp_gamut_data_v1_7 { 1033 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1034 uint32_t mode; 1035 uint32_t map_en; 1036 uint32_t tbl_size[MDP_GAMUT_TABLE_NUM_V1_7]; 1037 uint32_t * c0_data[MDP_GAMUT_TABLE_NUM_V1_7]; 1038 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1039 uint32_t * c1_c2_data[MDP_GAMUT_TABLE_NUM_V1_7]; 1040 uint32_t tbl_scale_off_sz[MDP_GAMUT_SCALE_OFF_TABLE_NUM]; 1041 uint32_t * scale_off_data[MDP_GAMUT_SCALE_OFF_TABLE_NUM]; 1042 }; 1043 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1044 struct mdp_calib_config_data { 1045 uint32_t ops; 1046 uint32_t addr; 1047 uint32_t data; 1048 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1049 }; 1050 struct mdp_calib_config_buffer { 1051 uint32_t ops; 1052 uint32_t size; 1053 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1054 uint32_t * buffer; 1055 }; 1056 struct mdp_calib_dcm_state { 1057 uint32_t ops; 1058 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1059 uint32_t dcm_state; 1060 }; 1061 enum { 1062 DCM_UNINIT, 1063 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1064 DCM_UNBLANK, 1065 DCM_ENTER, 1066 DCM_EXIT, 1067 DCM_BLANK, 1068 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1069 DTM_ENTER, 1070 DTM_EXIT, 1071 }; 1072 #define MDSS_PP_SPLIT_LEFT_ONLY 0x10000000 1073 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1074 #define MDSS_PP_SPLIT_RIGHT_ONLY 0x20000000 1075 #define MDSS_PP_SPLIT_MASK 0x30000000 1076 #define MDSS_MAX_BL_BRIGHTNESS 255 1077 #define AD_BL_LIN_LEN 256 1078 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1079 #define AD_BL_ATT_LUT_LEN 33 1080 #define MDSS_AD_MODE_AUTO_BL 0x0 1081 #define MDSS_AD_MODE_AUTO_STR 0x1 1082 #define MDSS_AD_MODE_TARG_STR 0x3 1083 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1084 #define MDSS_AD_MODE_MAN_STR 0x7 1085 #define MDSS_AD_MODE_CALIB 0xF 1086 #define MDP_PP_AD_INIT 0x10 1087 #define MDP_PP_AD_CFG 0x20 1088 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1089 struct mdss_ad_init { 1090 uint32_t asym_lut[33]; 1091 uint32_t color_corr_lut[33]; 1092 uint8_t i_control[2]; 1093 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1094 uint16_t black_lvl; 1095 uint16_t white_lvl; 1096 uint8_t var; 1097 uint8_t limit_ampl; 1098 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1099 uint8_t i_dither; 1100 uint8_t slope_max; 1101 uint8_t slope_min; 1102 uint8_t dither_ctl; 1103 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1104 uint8_t format; 1105 uint8_t auto_size; 1106 uint16_t frame_w; 1107 uint16_t frame_h; 1108 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1109 uint8_t logo_v; 1110 uint8_t logo_h; 1111 uint32_t alpha; 1112 uint32_t alpha_base; 1113 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1114 uint32_t al_thresh; 1115 uint32_t bl_lin_len; 1116 uint32_t bl_att_len; 1117 uint32_t * bl_lin; 1118 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1119 uint32_t * bl_lin_inv; 1120 uint32_t * bl_att_lut; 1121 }; 1122 #define MDSS_AD_BL_CTRL_MODE_EN 1 1123 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1124 #define MDSS_AD_BL_CTRL_MODE_DIS 0 1125 struct mdss_ad_cfg { 1126 uint32_t mode; 1127 uint32_t al_calib_lut[33]; 1128 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1129 uint16_t backlight_min; 1130 uint16_t backlight_max; 1131 uint16_t backlight_scale; 1132 uint16_t amb_light_min; 1133 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1134 uint16_t filter[2]; 1135 uint16_t calib[4]; 1136 uint8_t strength_limit; 1137 uint8_t t_filter_recursion; 1138 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1139 uint16_t stab_itr; 1140 uint32_t bl_ctrl_mode; 1141 }; 1142 struct mdss_ad_bl_cfg { 1143 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1144 uint32_t bl_min_delta; 1145 uint32_t bl_low_limit; 1146 }; 1147 struct mdss_ad_init_cfg { 1148 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1149 uint32_t ops; 1150 union { 1151 struct mdss_ad_init init; 1152 struct mdss_ad_cfg cfg; 1153 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1154 } params; 1155 }; 1156 struct mdss_ad_input { 1157 uint32_t mode; 1158 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1159 union { 1160 uint32_t amb_light; 1161 uint32_t strength; 1162 uint32_t calib_bl; 1163 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1164 } in; 1165 uint32_t output; 1166 }; 1167 #define MDSS_CALIB_MODE_BL 0x1 1168 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1169 struct mdss_calib_cfg { 1170 uint32_t ops; 1171 uint32_t calib_mask; 1172 }; 1173 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1174 enum { 1175 mdp_op_pcc_cfg, 1176 mdp_op_csc_cfg, 1177 mdp_op_lut_cfg, 1178 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1179 mdp_op_qseed_cfg, 1180 mdp_bl_scale_cfg, 1181 mdp_op_pa_cfg, 1182 mdp_op_pa_v2_cfg, 1183 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1184 mdp_op_dither_cfg, 1185 mdp_op_gamut_cfg, 1186 mdp_op_calib_cfg, 1187 mdp_op_ad_cfg, 1188 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1189 mdp_op_ad_input, 1190 mdp_op_calib_mode, 1191 mdp_op_calib_buffer, 1192 mdp_op_calib_dcm_state, 1193 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1194 mdp_op_max, 1195 mdp_op_pa_dither_cfg, 1196 mdp_op_ad_bl_cfg, 1197 mdp_op_pp_max = 255, 1198 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1199 }; 1200 #define mdp_op_pa_dither_cfg mdp_op_pa_dither_cfg 1201 #define mdp_op_pp_max mdp_op_pp_max 1202 #define mdp_op_ad_bl_cfg mdp_op_ad_bl_cfg 1203 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1204 enum { 1205 WB_FORMAT_NV12, 1206 WB_FORMAT_RGB_565, 1207 WB_FORMAT_RGB_888, 1208 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1209 WB_FORMAT_xRGB_8888, 1210 WB_FORMAT_ARGB_8888, 1211 WB_FORMAT_BGRA_8888, 1212 WB_FORMAT_BGRX_8888, 1213 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1214 WB_FORMAT_ARGB_8888_INPUT_ALPHA 1215 }; 1216 struct msmfb_mdp_pp { 1217 uint32_t op; 1218 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1219 union { 1220 struct mdp_pcc_cfg_data pcc_cfg_data; 1221 struct mdp_csc_cfg_data csc_cfg_data; 1222 struct mdp_lut_cfg_data lut_cfg_data; 1223 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1224 struct mdp_qseed_cfg_data qseed_cfg_data; 1225 struct mdp_bl_scale_data bl_scale_data; 1226 struct mdp_pa_cfg_data pa_cfg_data; 1227 struct mdp_pa_v2_cfg_data pa_v2_cfg_data; 1228 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1229 struct mdp_dither_cfg_data dither_cfg_data; 1230 struct mdp_gamut_cfg_data gamut_cfg_data; 1231 struct mdp_calib_config_data calib_cfg; 1232 struct mdss_ad_init_cfg ad_init_cfg; 1233 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1234 struct mdss_calib_cfg mdss_calib_cfg; 1235 struct mdss_ad_input ad_input; 1236 struct mdp_calib_config_buffer calib_buffer; 1237 struct mdp_calib_dcm_state calib_dcm; 1238 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1239 struct mdss_ad_bl_cfg ad_bl_cfg; 1240 } data; 1241 }; 1242 #define FB_METADATA_VIDEO_INFO_CODE_SUPPORT 1 1243 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1244 enum { 1245 metadata_op_none, 1246 metadata_op_base_blend, 1247 metadata_op_frame_rate, 1248 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1249 metadata_op_vic, 1250 metadata_op_wb_format, 1251 metadata_op_wb_secure, 1252 metadata_op_get_caps, 1253 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1254 metadata_op_crc, 1255 metadata_op_get_ion_fd, 1256 metadata_op_max 1257 }; 1258 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1259 struct mdp_blend_cfg { 1260 uint32_t is_premultiplied; 1261 }; 1262 struct mdp_mixer_cfg { 1263 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1264 uint32_t writeback_format; 1265 uint32_t alpha; 1266 }; 1267 struct mdss_hw_caps { 1268 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1269 uint32_t mdp_rev; 1270 uint8_t rgb_pipes; 1271 uint8_t vig_pipes; 1272 uint8_t dma_pipes; 1273 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1274 uint8_t max_smp_cnt; 1275 uint8_t smp_per_pipe; 1276 uint32_t features; 1277 }; 1278 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1279 struct msmfb_metadata { 1280 uint32_t op; 1281 uint32_t flags; 1282 union { 1283 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1284 struct mdp_misr misr_request; 1285 struct mdp_blend_cfg blend_cfg; 1286 struct mdp_mixer_cfg mixer_cfg; 1287 uint32_t panel_frame_rate; 1288 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1289 uint32_t video_info_code; 1290 struct mdss_hw_caps caps; 1291 uint8_t secure_en; 1292 int fbmem_ionfd; 1293 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1294 } data; 1295 }; 1296 #define MDP_MAX_FENCE_FD 32 1297 #define MDP_BUF_SYNC_FLAG_WAIT 1 1298 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1299 #define MDP_BUF_SYNC_FLAG_RETIRE_FENCE 0x10 1300 struct mdp_buf_sync { 1301 uint32_t flags; 1302 uint32_t acq_fen_fd_cnt; 1303 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1304 uint32_t session_id; 1305 int * acq_fen_fd; 1306 int * rel_fen_fd; 1307 int * retire_fen_fd; 1308 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1309 }; 1310 struct mdp_async_blit_req_list { 1311 struct mdp_buf_sync sync; 1312 uint32_t count; 1313 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1314 struct mdp_blit_req req[]; 1315 }; 1316 #define MDP_DISPLAY_COMMIT_OVERLAY 1 1317 struct mdp_display_commit { 1318 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1319 uint32_t flags; 1320 uint32_t wait_for_finish; 1321 struct fb_var_screeninfo var; 1322 struct mdp_rect l_roi; 1323 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1324 struct mdp_rect r_roi; 1325 }; 1326 struct mdp_overlay_list { 1327 uint32_t num_overlays; 1328 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1329 struct mdp_overlay * * overlay_list; 1330 uint32_t flags; 1331 uint32_t processed_overlays; 1332 }; 1333 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1334 struct mdp_page_protection { 1335 uint32_t page_protection; 1336 }; 1337 struct mdp_mixer_info { 1338 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1339 int pndx; 1340 int pnum; 1341 int ptype; 1342 int mixer_num; 1343 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1344 int z_order; 1345 }; 1346 #define MAX_PIPE_PER_MIXER 7 1347 struct msmfb_mixer_info_req { 1348 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1349 int mixer_num; 1350 int cnt; 1351 struct mdp_mixer_info info[MAX_PIPE_PER_MIXER]; 1352 }; 1353 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1354 enum { 1355 DISPLAY_SUBSYSTEM_ID, 1356 ROTATOR_SUBSYSTEM_ID, 1357 }; 1358 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1359 enum { 1360 MDP_IOMMU_DOMAIN_CP, 1361 MDP_IOMMU_DOMAIN_NS, 1362 }; 1363 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1364 enum { 1365 MDP_WRITEBACK_MIRROR_OFF, 1366 MDP_WRITEBACK_MIRROR_ON, 1367 MDP_WRITEBACK_MIRROR_PAUSE, 1368 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1369 MDP_WRITEBACK_MIRROR_RESUME, 1370 }; 1371 enum mdp_color_space { 1372 MDP_CSC_ITU_R_601, 1373 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1374 MDP_CSC_ITU_R_601_FR, 1375 MDP_CSC_ITU_R_709, 1376 }; 1377 #define MDP_CSC_ITU_R_2020 (MDP_CSC_ITU_R_709 + 1) 1378 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1379 #define MDP_CSC_ITU_R_2020_FR (MDP_CSC_ITU_R_2020 + 1) 1380 enum { 1381 mdp_igc_v1_7 = 1, 1382 mdp_igc_vmax, 1383 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1384 mdp_hist_lut_v1_7, 1385 mdp_hist_lut_vmax, 1386 mdp_pgc_v1_7, 1387 mdp_pgc_vmax, 1388 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1389 mdp_dither_v1_7, 1390 mdp_dither_vmax, 1391 mdp_gamut_v1_7, 1392 mdp_gamut_vmax, 1393 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1394 mdp_pa_v1_7, 1395 mdp_pa_vmax, 1396 mdp_pcc_v1_7, 1397 mdp_pcc_vmax, 1398 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1399 mdp_pp_legacy, 1400 mdp_dither_pa_v1_7, 1401 mdp_igc_v3, 1402 mdp_pp_unknown = 255 1403 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1404 }; 1405 #define mdp_dither_pa_v1_7 mdp_dither_pa_v1_7 1406 #define mdp_pp_unknown mdp_pp_unknown 1407 #define mdp_igc_v3 mdp_igc_v3 1408 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1409 enum { 1410 IGC = 1, 1411 PCC, 1412 GC, 1413 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1414 PA, 1415 GAMUT, 1416 DITHER, 1417 QSEED, 1418 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1419 HIST_LUT, 1420 HIST, 1421 PP_FEATURE_MAX, 1422 PA_DITHER, 1423 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1424 PP_MAX_FEATURES = 25, 1425 }; 1426 #define PA_DITHER PA_DITHER 1427 #define PP_MAX_FEATURES PP_MAX_FEATURES 1428 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1429 struct mdp_pp_feature_version { 1430 uint32_t pp_feature; 1431 uint32_t version_info; 1432 }; 1433 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1434 #endif 1435 1436
