1 #ifndef _MSM_MDP_EXT_H_ 2 #define _MSM_MDP_EXT_H_ 3 4 #include <linux/msm_mdp.h> 5 6 #define MDP_IOCTL_MAGIC 'S' 7 /* atomic commit ioctl used for validate and commit request */ 8 #define MSMFB_ATOMIC_COMMIT _IOWR(MDP_IOCTL_MAGIC, 128, void *) 9 10 /* 11 * Ioctl for updating the layer position asynchronously. Initially, pipes 12 * should be configured with MDP_LAYER_ASYNC flag set during the atomic commit, 13 * after which any number of position update calls can be made. This would 14 * enable multiple position updates within a single vsync. However, the screen 15 * update would happen only after vsync, which would pick the latest update. 16 * 17 * Limitations: 18 * - Currently supported only for video mode panels with single LM or dual LM 19 * with source_split enabled. 20 * - Only position update is supported with no scaling/cropping. 21 * - Async layers should have unique z_order. 22 */ 23 #define MSMFB_ASYNC_POSITION_UPDATE _IOWR(MDP_IOCTL_MAGIC, 129, \ 24 struct mdp_position_update) 25 26 /* 27 * Ioctl for sending the config information. 28 * QSEED3 coefficeint LUT tables is passed by the user space using this IOCTL. 29 */ 30 #define MSMFB_MDP_SET_CFG _IOW(MDP_IOCTL_MAGIC, 130, \ 31 struct mdp_set_cfg) 32 33 /* 34 * Ioctl for setting the PLL PPM. 35 * PLL PPM is passed by the user space using this IOCTL. 36 */ 37 #define MSMFB_MDP_SET_PANEL_PPM _IOW(MDP_IOCTL_MAGIC, 131, int) 38 39 /* 40 * To allow proper structure padding for 64bit/32bit target 41 */ 42 #ifdef __LP64 43 #define MDP_LAYER_COMMIT_V1_PAD 2 44 #else 45 #define MDP_LAYER_COMMIT_V1_PAD 3 46 #endif 47 48 /********************************************************************** 49 LAYER FLAG CONFIGURATION 50 **********************************************************************/ 51 /* left-right layer flip flag */ 52 #define MDP_LAYER_FLIP_LR 0x1 53 54 /* up-down layer flip flag */ 55 #define MDP_LAYER_FLIP_UD 0x2 56 57 /* 58 * This flag enables pixel extension for the current layer. Validate/commit 59 * call uses scale parameters when this flag is enabled. 60 */ 61 #define MDP_LAYER_ENABLE_PIXEL_EXT 0x4 62 63 /* Flag indicates that layer is foreground layer */ 64 #define MDP_LAYER_FORGROUND 0x8 65 66 /* Flag indicates that layer is associated with secure session */ 67 #define MDP_LAYER_SECURE_SESSION 0x10 68 69 /* 70 * Flag indicates that layer is drawing solid fill. Validate/commit call 71 * does not expect buffer when this flag is enabled. 72 */ 73 #define MDP_LAYER_SOLID_FILL 0x20 74 75 /* Layer format is deinterlace */ 76 #define MDP_LAYER_DEINTERLACE 0x40 77 78 /* layer contains bandwidth compressed format data */ 79 #define MDP_LAYER_BWC 0x80 80 81 /* layer is async position updatable */ 82 #define MDP_LAYER_ASYNC 0x100 83 84 /* layer contains postprocessing configuration data */ 85 #define MDP_LAYER_PP 0x200 86 87 /* Flag indicates that layer is associated with secure display session */ 88 #define MDP_LAYER_SECURE_DISPLAY_SESSION 0x400 89 90 /* Flag enabled qseed3 scaling for the current layer */ 91 #define MDP_LAYER_ENABLE_QSEED3_SCALE 0x800 92 93 /* 94 * layer will work in multirect mode, where single hardware should 95 * fetch multiple rectangles with a single hardware 96 */ 97 #define MDP_LAYER_MULTIRECT_ENABLE 0x1000 98 99 /* 100 * if flag present and multirect is enabled, multirect will work in parallel 101 * fetch mode, otherwise it will default to serial fetch mode. 102 */ 103 #define MDP_LAYER_MULTIRECT_PARALLEL_MODE 0x2000 104 105 106 /* Flag indicates that layer is associated with secure camera session */ 107 #define MDP_LAYER_SECURE_CAMERA_SESSION 0x4000 108 109 /********************************************************************** 110 DESTINATION SCALER FLAG CONFIGURATION 111 **********************************************************************/ 112 113 /* Enable/disable Destination scaler */ 114 #define MDP_DESTSCALER_ENABLE 0x1 115 116 /* 117 * Indicating mdp_destination_scaler_data contains 118 * Scaling parameter update. Can be set anytime. 119 */ 120 #define MDP_DESTSCALER_SCALE_UPDATE 0x2 121 122 /* 123 * Indicating mdp_destination_scaler_data contains 124 * Detail enhancement setting update. Can be set anytime. 125 */ 126 #define MDP_DESTSCALER_ENHANCER_UPDATE 0x4 127 128 /* 129 * Indicating a partial update to panel ROI. ROI can be 130 * applied anytime when Destination scaler is enabled. 131 */ 132 #define MDP_DESTSCALER_ROI_ENABLE 0x8 133 134 /********************************************************************** 135 VALIDATE/COMMIT FLAG CONFIGURATION 136 **********************************************************************/ 137 138 /* 139 * Client enables it to inform that call is to validate layers before commit. 140 * If this flag is not set then driver will use MSMFB_ATOMIC_COMMIT for commit. 141 */ 142 #define MDP_VALIDATE_LAYER 0x01 143 144 /* 145 * This flag is only valid for commit call. Commit behavior is synchronous 146 * when this flag is defined. It blocks current call till processing is 147 * complete. Behavior is asynchronous otherwise. 148 */ 149 #define MDP_COMMIT_WAIT_FOR_FINISH 0x02 150 151 /* 152 * This flag is only valid for commit call and used for debugging purpose. It 153 * forces the to wait for sync fences. 154 */ 155 #define MDP_COMMIT_SYNC_FENCE_WAIT 0x04 156 157 /* Flag to enable AVR(Adaptive variable refresh) feature. */ 158 #define MDP_COMMIT_AVR_EN 0x08 159 160 /* 161 * Flag to select one shot mode when AVR feature is enabled. 162 * Default mode is continuous mode. 163 */ 164 #define MDP_COMMIT_AVR_ONE_SHOT_MODE 0x10 165 166 /* Flag to indicate dual partial ROI update */ 167 #define MDP_COMMIT_PARTIAL_UPDATE_DUAL_ROI 0x20 168 169 /* Flag to update brightness when commit */ 170 #define MDP_COMMIT_UPDATE_BRIGHTNESS 0x40 171 172 /* Flag to enable concurrent writeback for the frame */ 173 #define MDP_COMMIT_CWB_EN 0x800 174 175 /* 176 * Flag to select DSPP as the data point for CWB. If CWB 177 * is enabled without this flag, LM will be selected as data point. 178 */ 179 #define MDP_COMMIT_CWB_DSPP 0x1000 180 181 #define MDP_COMMIT_VERSION_1_0 0x00010000 182 183 #define OUT_LAYER_COLOR_SPACE 184 185 /* From CEA.861.3 */ 186 #define MDP_HDR_EOTF_SMTPE_ST2084 0x2 187 #define MDP_HDR_EOTF_HLG 0x3 188 189 /* From Vesa DPv1.4 - Pixel Encoding - Table 2-120 */ 190 #define MDP_PIXEL_ENCODING_RGB 0x0 191 #define MDP_PIXEL_ENCODING_YCBCR_444 0x1 192 #define MDP_PIXEL_ENCODING_YCBCR_422 0x2 193 #define MDP_PIXEL_ENCODING_YCBCR_420 0x3 194 #define MDP_PIXEL_ENCODING_Y_ONLY 0x4 195 #define MDP_PIXEL_ENCODING_RAW 0x5 196 197 /* From Vesa DPv1.4 - Colorimetry Formats - Table 2-120 */ 198 /* RGB - used with MDP_DP_PIXEL_ENCODING_RGB */ 199 #define MDP_COLORIMETRY_RGB_SRGB 0x0 200 #define MDP_COLORIMETRY_RGB_WIDE_FIXED_POINT 0x1 201 #define MDP_COLORIMETRY_RGB_WIDE_FLOAT_POINT 0x2 202 #define MDP_COLORIMETRY_RGB_ADOBE 0x3 203 #define MDP_COLORIMETRY_RGB_DPI_P3 0x4 204 #define MDP_COLORIMETRY_RGB_CUSTOM 0x5 205 #define MDP_COLORIMETRY_RGB_ITU_R_BT_2020 0x6 206 207 /* YUV - used with MDP_DP_PIXEL_ENCODING_YCBCR(444 or 422 or 420) */ 208 #define MDP_COLORIMETRY_YCBCR_ITU_R_BT_601 0x0 209 #define MDP_COLORIMETRY_YCBCR_ITU_R_BT_709 0x1 210 #define MDP_COLORIMETRY_YCBCR_XV_YCC_601 0x2 211 #define MDP_COLORIMETRY_YCBCR_XV_YCC_709 0x3 212 #define MDP_COLORIMETRY_YCBCR_S_YCC_601 0x4 213 #define MDP_COLORIMETRY_YCBCR_ADOBE_YCC_601 0x5 214 #define MDP_COLORIMETRY_YCBCR_ITU_R_BT_2020_YCBCR_CONST 0x6 215 #define MDP_COLORIMETRY_YCBCR_ITU_R_BT_2020_YCBCR 0x7 216 217 /* Dynamic Range - Table 2-120 */ 218 /* Full range */ 219 #define MDP_DYNAMIC_RANGE_VESA 0x0 220 /* Limited range */ 221 #define MDP_DYNAMIC_RANGE_CEA 0x1 222 223 /* Bits per component(bpc) for Pixel encoding format RGB from Table 2-120 */ 224 #define MDP_RGB_6_BPC 0x0 225 #define MDP_RGB_8_BPC 0x1 226 #define MDP_RGB_10_BPC 0x2 227 #define MDP_RGB_12_BPC 0x3 228 #define MDP_RGB_16_BPC 0x4 229 230 /* 231 * Bits per component(bpc) for Pixel encoding format YCbCr444, YCbCr422, 232 * YCbCr420 and Y only 233 * from Table 2-120 234 */ 235 #define MDP_YUV_8_BPC 0x1 236 #define MDP_YUV_10_BPC 0x2 237 #define MDP_YUV_12_BPC 0x3 238 #define MDP_YUV_16_BPC 0x4 239 240 /* Bits per component(bpc) for Pixel encoding format RAW from Table 2-120 */ 241 #define MDP_RAW_6_BPC 0x1 242 #define MDP_RAW_7_BPC 0x2 243 #define MDP_RAW_8_BPC 0x3 244 #define MDP_RAW_10_BPC 0x4 245 #define MDP_RAW_12_BPC 0x5 246 #define MDP_RAW_14_BPC 0x6 247 #define MDP_RAW16_BPC 0x7 248 249 /* Content Type - Table 2-120 */ 250 #define MDP_CONTENT_TYPE_NOT_DEFINED 0x0 251 #define MDP_CONTENT_TYPE_GRAPHICS 0x1 252 #define MDP_CONTENT_TYPE_PHOTO 0x2 253 #define MDP_CONTENT_TYPE_VIDEO 0x3 254 #define MDP_CONTENT_TYPE_GAME 0x4 255 256 /********************************************************************** 257 Configuration structures 258 All parameters are input to driver unless mentioned output parameter 259 explicitly. 260 **********************************************************************/ 261 struct mdp_layer_plane { 262 /* DMA buffer file descriptor information. */ 263 int fd; 264 265 /* Pixel offset in the dma buffer. */ 266 uint32_t offset; 267 268 /* Number of bytes in one scan line including padding bytes. */ 269 uint32_t stride; 270 }; 271 272 struct mdp_layer_buffer { 273 /* layer width in pixels. */ 274 uint32_t width; 275 276 /* layer height in pixels. */ 277 uint32_t height; 278 279 /* 280 * layer format in DRM-style fourcc, refer drm_fourcc.h for 281 * standard formats 282 */ 283 uint32_t format; 284 285 /* plane to hold the fd, offset, etc for all color components */ 286 struct mdp_layer_plane planes[MAX_PLANES]; 287 288 /* valid planes count in layer planes list */ 289 uint32_t plane_count; 290 291 /* compression ratio factor, value depends on the pixel format */ 292 struct mult_factor comp_ratio; 293 294 /* 295 * SyncFence associated with this buffer. It is used in two ways. 296 * 297 * 1. Driver waits to consume the buffer till producer signals in case 298 * of primary and external display. 299 * 300 * 2. Writeback device uses buffer structure for output buffer where 301 * driver is producer. However, client sends the fence with buffer to 302 * indicate that consumer is still using the buffer and it is not ready 303 * for new content. 304 */ 305 int fence; 306 307 /* 32bits reserved value for future usage. */ 308 uint32_t reserved; 309 }; 310 311 /* 312 * One layer holds configuration for one pipe. If client wants to stage single 313 * layer on two pipes then it should send two different layers with relative 314 * (x,y) information. Client must send same information during validate and 315 * commit call. Commit call may fail if client sends different layer information 316 * attached to same pipe during validate and commit. Device invalidate the pipe 317 * once it receives the vsync for that commit. 318 */ 319 struct mdp_input_layer { 320 /* 321 * Flag to enable/disable properties for layer configuration. Refer 322 * layer flag configuration section for all possible flags. 323 */ 324 uint32_t flags; 325 326 /* 327 * Pipe selection for this layer by client. Client provides the index 328 * in validate and commit call. Device reserves the pipe once validate 329 * is successful. Device only uses validated pipe during commit call. 330 * If client sends different layer/pipe configuration in validate & 331 * commit then commit may fail. 332 */ 333 uint32_t pipe_ndx; 334 335 /* 336 * Horizontal decimation value, this indicates the amount of pixels 337 * dropped for each pixel that is fetched from a line. It does not 338 * result in bandwidth reduction because pixels are still fetched from 339 * memory but dropped internally by hardware. 340 * The decimation value given should be power of two of decimation 341 * amount. 342 * 0: no decimation 343 * 1: decimate by 2 (drop 1 pixel for each pixel fetched) 344 * 2: decimate by 4 (drop 3 pixels for each pixel fetched) 345 * 3: decimate by 8 (drop 7 pixels for each pixel fetched) 346 * 4: decimate by 16 (drop 15 pixels for each pixel fetched) 347 */ 348 uint8_t horz_deci; 349 350 /* 351 * Vertical decimation value, this indicates the amount of lines 352 * dropped for each line that is fetched from overlay. It saves 353 * bandwidth because decimated pixels are not fetched. 354 * The decimation value given should be power of two of decimation 355 * amount. 356 * 0: no decimation 357 * 1: decimation by 2 (drop 1 line for each line fetched) 358 * 2: decimation by 4 (drop 3 lines for each line fetched) 359 * 3: decimation by 8 (drop 7 lines for each line fetched) 360 * 4: decimation by 16 (drop 15 lines for each line fetched) 361 */ 362 uint8_t vert_deci; 363 364 /* 365 * Used to set plane opacity. The range can be from 0-255, where 366 * 0 means completely transparent and 255 means fully opaque. 367 */ 368 uint8_t alpha; 369 370 /* 371 * Blending stage to occupy in display, if multiple layers are present, 372 * highest z_order usually means the top most visible layer. The range 373 * acceptable is from 0-7 to support blending up to 8 layers. 374 */ 375 uint16_t z_order; 376 377 /* 378 * Color used as color key for transparency. Any pixel in fetched 379 * image matching this color will be transparent when blending. 380 * The color should be in same format as the source image format. 381 */ 382 uint32_t transp_mask; 383 384 /* 385 * Solid color used to fill the overlay surface when no source 386 * buffer is provided. 387 */ 388 uint32_t bg_color; 389 390 /* blend operation defined in "mdss_mdp_blend_op" enum. */ 391 enum mdss_mdp_blend_op blend_op; 392 393 /* color space of the source */ 394 enum mdp_color_space color_space; 395 396 /* 397 * Source crop rectangle, portion of image that will be fetched. This 398 * should always be within boundaries of source image. 399 */ 400 struct mdp_rect src_rect; 401 402 /* 403 * Destination rectangle, the position and size of image on screen. 404 * This should always be within panel boundaries. 405 */ 406 struct mdp_rect dst_rect; 407 408 /* Scaling parameters. */ 409 void *scale; 410 411 /* Buffer attached with each layer. Device uses it for commit call. */ 412 struct mdp_layer_buffer buffer; 413 414 /* 415 * Source side post processing configuration information for each 416 * layer. 417 */ 418 void *pp_info; 419 420 /* 421 * This is an output parameter. 422 * 423 * Only for validate call. Frame buffer device sets error code 424 * based on validate call failure scenario. 425 */ 426 int error_code; 427 428 /* 32bits reserved value for future usage. */ 429 uint32_t reserved[6]; 430 }; 431 432 struct mdp_output_layer { 433 /* 434 * Flag to enable/disable properties for layer configuration. Refer 435 * layer flag config section for all possible flags. 436 */ 437 uint32_t flags; 438 439 /* 440 * Writeback destination selection for output. Client provides the index 441 * in validate and commit call. 442 */ 443 uint32_t writeback_ndx; 444 445 /* Buffer attached with output layer. Device uses it for commit call */ 446 struct mdp_layer_buffer buffer; 447 448 /* color space of the destination */ 449 enum mdp_color_space color_space; 450 451 /* 32bits reserved value for future usage. */ 452 uint32_t reserved[5]; 453 }; 454 455 /* 456 * Destination scaling info structure holds setup paramaters for upscaling 457 * setting in the destination scaling block. 458 */ 459 struct mdp_destination_scaler_data { 460 /* 461 * Flag to switch between mode for destination scaler. Please Refer to 462 * destination scaler flag config for all possible setting. 463 */ 464 uint32_t flags; 465 466 /* 467 * Destination scaler selection index. Client provides the index in 468 * validate and commit call. 469 */ 470 uint32_t dest_scaler_ndx; 471 472 /* 473 * LM width configuration per Destination scaling updates 474 */ 475 uint32_t lm_width; 476 477 /* 478 * LM height configuration per Destination scaling updates 479 */ 480 uint32_t lm_height; 481 482 /* 483 * The scaling parameters for all the mode except disable. For 484 * disabling the scaler, there is no need to provide the scale. 485 * A userspace pointer points to struct mdp_scale_data_v2. 486 */ 487 uint64_t scale; 488 489 /* 490 * Panel ROI is used when partial update is required in 491 * current commit call. 492 */ 493 struct mdp_rect panel_roi; 494 }; 495 496 /* 497 * Commit structure holds layer stack send by client for validate and commit 498 * call. If layers are different between validate and commit call then commit 499 * call will also do validation. In such case, commit may fail. 500 */ 501 struct mdp_layer_commit_v1 { 502 /* 503 * Flag to enable/disable properties for commit/validate call. Refer 504 * validate/commit flag config section for all possible flags. 505 */ 506 uint32_t flags; 507 508 /* 509 * This is an output parameter. 510 * 511 * Frame buffer device provides release fence handle to client. It 512 * triggers release fence when display hardware has consumed all the 513 * buffers attached to this commit call and buffer is ready for reuse 514 * for primary and external. For writeback case, it triggers it when 515 * output buffer is ready for consumer. 516 */ 517 int release_fence; 518 519 /* 520 * Left_roi is optional configuration. Client configures it only when 521 * partial update is enabled. It defines the "region of interest" on 522 * left part of panel when it is split display. For non-split display, 523 * it defines the "region of interest" on the panel. 524 */ 525 struct mdp_rect left_roi; 526 527 /* 528 * Right_roi is optional configuration. Client configures it only when 529 * partial update is enabled. It defines the "region of interest" on 530 * right part of panel for split display configuration. It is not 531 * required for non-split display. 532 */ 533 struct mdp_rect right_roi; 534 535 /* Pointer to a list of input layers for composition. */ 536 struct mdp_input_layer *input_layers; 537 538 /* Input layer count present in input list */ 539 uint32_t input_layer_cnt; 540 541 /* 542 * Output layer for writeback display. It supports only one 543 * layer as output layer. This is not required for primary 544 * and external displays 545 */ 546 struct mdp_output_layer *output_layer; 547 548 /* 549 * This is an output parameter. 550 * 551 * Frame buffer device provides retire fence handle if 552 * COMMIT_RETIRE_FENCE flag is set in commit call. It triggers 553 * retire fence when current layers are swapped with new layers 554 * on display hardware. For video mode panel and writeback, 555 * retire fence and release fences are triggered at the same 556 * time while command mode panel triggers release fence first 557 * (on pingpong done) and retire fence (on rdptr done) 558 * after that. 559 */ 560 int retire_fence; 561 562 /* 563 * Scaler data and control for setting up destination scaler. 564 * A userspace pointer that points to a list of 565 * struct mdp_destination_scaler_data. 566 */ 567 void *dest_scaler; 568 569 /* 570 * Represents number of Destination scaler data provied by userspace. 571 */ 572 uint32_t dest_scaler_cnt; 573 574 /* Backlight level that would update when display commit */ 575 uint32_t bl_level; 576 577 /* 32-bits reserved value for future usage. */ 578 uint32_t reserved[MDP_LAYER_COMMIT_V1_PAD]; 579 }; 580 581 /* 582 * mdp_overlay_list - argument for ioctl MSMFB_ATOMIC_COMMIT 583 */ 584 struct mdp_layer_commit { 585 /* 586 * 32bit version indicates the commit structure selection 587 * from union. Lower 16bits indicates the minor version while 588 * higher 16bits indicates the major version. It selects the 589 * commit structure based on major version selection. Minor version 590 * indicates that reserved fields are in use. 591 * 592 * Current supported version is 1.0 (Major:1 Minor:0) 593 */ 594 uint32_t version; 595 union { 596 /* Layer commit/validate definition for V1 */ 597 struct mdp_layer_commit_v1 commit_v1; 598 }; 599 }; 600 601 struct mdp_point { 602 uint32_t x; 603 uint32_t y; 604 }; 605 606 /* 607 * Async updatable layers. One layer holds configuration for one pipe. 608 */ 609 struct mdp_async_layer { 610 /* 611 * Flag to enable/disable properties for layer configuration. Refer 612 * layer flag config section for all possible flags. 613 */ 614 uint32_t flags; 615 616 /* 617 * Pipe selection for this layer by client. Client provides the 618 * pipe index that the device reserved during ATOMIC_COMMIT. 619 */ 620 uint32_t pipe_ndx; 621 622 /* Source start x,y. */ 623 struct mdp_point src; 624 625 /* Destination start x,y. */ 626 struct mdp_point dst; 627 628 /* 629 * This is an output parameter. 630 * 631 * Frame buffer device sets error code based on the failure. 632 */ 633 int error_code; 634 635 uint32_t reserved[3]; 636 }; 637 638 /* 639 * mdp_position_update - argument for ioctl MSMFB_ASYNC_POSITION_UPDATE 640 */ 641 struct mdp_position_update { 642 /* Pointer to a list of async updatable input layers */ 643 struct mdp_async_layer *input_layers; 644 645 /* Input layer count present in input list */ 646 uint32_t input_layer_cnt; 647 }; 648 649 #define MAX_DET_CURVES 3 650 struct mdp_det_enhance_data { 651 uint32_t enable; 652 int16_t sharpen_level1; 653 int16_t sharpen_level2; 654 uint16_t clip; 655 uint16_t limit; 656 uint16_t thr_quiet; 657 uint16_t thr_dieout; 658 uint16_t thr_low; 659 uint16_t thr_high; 660 uint16_t prec_shift; 661 int16_t adjust_a[MAX_DET_CURVES]; 662 int16_t adjust_b[MAX_DET_CURVES]; 663 int16_t adjust_c[MAX_DET_CURVES]; 664 }; 665 666 /* Flags to enable Scaler and its sub components */ 667 #define ENABLE_SCALE 0x1 668 #define ENABLE_DETAIL_ENHANCE 0x2 669 #define ENABLE_DIRECTION_DETECTION 0x4 670 671 /* LUT configuration flags */ 672 #define SCALER_LUT_SWAP 0x1 673 #define SCALER_LUT_DIR_WR 0x2 674 #define SCALER_LUT_Y_CIR_WR 0x4 675 #define SCALER_LUT_UV_CIR_WR 0x8 676 #define SCALER_LUT_Y_SEP_WR 0x10 677 #define SCALER_LUT_UV_SEP_WR 0x20 678 679 /* Y/RGB and UV filter configuration */ 680 #define FILTER_EDGE_DIRECTED_2D 0x0 681 #define FILTER_CIRCULAR_2D 0x1 682 #define FILTER_SEPARABLE_1D 0x2 683 #define FILTER_BILINEAR 0x3 684 685 /* Alpha filters */ 686 #define FILTER_ALPHA_DROP_REPEAT 0x0 687 #define FILTER_ALPHA_BILINEAR 0x1 688 689 /** 690 * struct mdp_scale_data_v2 691 * Driver uses this new Data structure for storing all scaling params 692 * This structure contains all pixel extension data and QSEED3 filter 693 * configuration and coefficient table indices 694 */ 695 struct mdp_scale_data_v2 { 696 uint32_t enable; 697 698 /* Init phase values */ 699 int32_t init_phase_x[MAX_PLANES]; 700 int32_t phase_step_x[MAX_PLANES]; 701 int32_t init_phase_y[MAX_PLANES]; 702 int32_t phase_step_y[MAX_PLANES]; 703 704 /* This should be set to toal horizontal pixels 705 * left + right + width */ 706 uint32_t num_ext_pxls_left[MAX_PLANES]; 707 708 /* Unused param for backward compatibility */ 709 uint32_t num_ext_pxls_right[MAX_PLANES]; 710 711 /* This should be set to vertical pixels 712 * top + bottom + height */ 713 uint32_t num_ext_pxls_top[MAX_PLANES]; 714 715 /* Unused param for backward compatibility */ 716 uint32_t num_ext_pxls_btm[MAX_PLANES]; 717 718 /* over fetch pixels */ 719 int32_t left_ftch[MAX_PLANES]; 720 int32_t left_rpt[MAX_PLANES]; 721 int32_t right_ftch[MAX_PLANES]; 722 int32_t right_rpt[MAX_PLANES]; 723 724 /* Repeat pixels */ 725 uint32_t top_rpt[MAX_PLANES]; 726 uint32_t btm_rpt[MAX_PLANES]; 727 uint32_t top_ftch[MAX_PLANES]; 728 uint32_t btm_ftch[MAX_PLANES]; 729 730 uint32_t roi_w[MAX_PLANES]; 731 732 /* alpha plane can only be scaled using bilinear or pixel 733 * repeat/drop, specify these for Y and UV planes only */ 734 uint32_t preload_x[MAX_PLANES]; 735 uint32_t preload_y[MAX_PLANES]; 736 uint32_t src_width[MAX_PLANES]; 737 uint32_t src_height[MAX_PLANES]; 738 739 uint32_t dst_width; 740 uint32_t dst_height; 741 742 uint32_t y_rgb_filter_cfg; 743 uint32_t uv_filter_cfg; 744 uint32_t alpha_filter_cfg; 745 uint32_t blend_cfg; 746 747 uint32_t lut_flag; 748 uint32_t dir_lut_idx; 749 750 /* for Y(RGB) and UV planes*/ 751 uint32_t y_rgb_cir_lut_idx; 752 uint32_t uv_cir_lut_idx; 753 uint32_t y_rgb_sep_lut_idx; 754 uint32_t uv_sep_lut_idx; 755 756 struct mdp_det_enhance_data detail_enhance; 757 758 /* reserved value for future usage. */ 759 uint64_t reserved[8]; 760 }; 761 762 /** 763 * struct mdp_scale_luts_info 764 * This struct pointer is received as payload in SET_CFG_IOCTL when the flags 765 * is set to MDP_QSEED3_LUT_CFG 766 * @dir_lut: Direction detection coefficients table 767 * @cir_lut: Circular coefficeints table 768 * @sep_lut: Separable coefficeints table 769 * @dir_lut_size: Size of direction coefficients table 770 * @cir_lut_size: Size of circular coefficients table 771 * @sep_lut_size: Size of separable coefficients table 772 */ 773 struct mdp_scale_luts_info { 774 uint64_t dir_lut; 775 uint64_t cir_lut; 776 uint64_t sep_lut; 777 uint32_t dir_lut_size; 778 uint32_t cir_lut_size; 779 uint32_t sep_lut_size; 780 }; 781 782 #define MDP_QSEED3_LUT_CFG 0x1 783 784 struct mdp_set_cfg { 785 uint64_t flags; 786 uint32_t len; 787 uint64_t payload; 788 }; 789 790 #define HDR_PRIMARIES_COUNT 3 791 792 #define MDP_HDR_STREAM 793 794 struct mdp_hdr_stream { 795 uint32_t eotf; 796 uint32_t display_primaries_x[HDR_PRIMARIES_COUNT]; 797 uint32_t display_primaries_y[HDR_PRIMARIES_COUNT]; 798 uint32_t white_point_x; 799 uint32_t white_point_y; 800 uint32_t max_luminance; 801 uint32_t min_luminance; 802 uint32_t max_content_light_level; 803 uint32_t max_average_light_level; 804 /* DP related */ 805 uint32_t pixel_encoding; 806 uint32_t colorimetry; 807 uint32_t range; 808 uint32_t bits_per_component; 809 uint32_t content_type; 810 uint32_t reserved[5]; 811 }; 812 #endif 813
