1 #ifndef _MSM_VIDC_DEC_H_ 2 #define _MSM_VIDC_DEC_H_ 3 4 #include <linux/types.h> 5 #include <linux/ioctl.h> 6 7 /* STATUS CODES */ 8 /* Base value for status codes */ 9 #define VDEC_S_BASE 0x40000000 10 /* Success */ 11 #define VDEC_S_SUCCESS (VDEC_S_BASE) 12 /* General failure */ 13 #define VDEC_S_EFAIL (VDEC_S_BASE + 1) 14 /* Fatal irrecoverable failure. Need to tear down session. */ 15 #define VDEC_S_EFATAL (VDEC_S_BASE + 2) 16 /* Error detected in the passed parameters */ 17 #define VDEC_S_EBADPARAM (VDEC_S_BASE + 3) 18 /* Command called in invalid state. */ 19 #define VDEC_S_EINVALSTATE (VDEC_S_BASE + 4) 20 /* Insufficient OS resources - thread, memory etc. */ 21 #define VDEC_S_ENOSWRES (VDEC_S_BASE + 5) 22 /* Insufficient HW resources - core capacity maxed out. */ 23 #define VDEC_S_ENOHWRES (VDEC_S_BASE + 6) 24 /* Invalid command called */ 25 #define VDEC_S_EINVALCMD (VDEC_S_BASE + 7) 26 /* Command timeout. */ 27 #define VDEC_S_ETIMEOUT (VDEC_S_BASE + 8) 28 /* Pre-requirement is not met for API. */ 29 #define VDEC_S_ENOPREREQ (VDEC_S_BASE + 9) 30 /* Command queue is full. */ 31 #define VDEC_S_ECMDQFULL (VDEC_S_BASE + 10) 32 /* Command is not supported by this driver */ 33 #define VDEC_S_ENOTSUPP (VDEC_S_BASE + 11) 34 /* Command is not implemented by thedriver. */ 35 #define VDEC_S_ENOTIMPL (VDEC_S_BASE + 12) 36 /* Command is not implemented by the driver. */ 37 #define VDEC_S_BUSY (VDEC_S_BASE + 13) 38 #define VDEC_S_INPUT_BITSTREAM_ERR (VDEC_S_BASE + 14) 39 40 #define VDEC_INTF_VER 1 41 #define VDEC_MSG_BASE 0x0000000 42 /* Codes to identify asynchronous message responses and events that driver 43 wants to communicate to the app.*/ 44 #define VDEC_MSG_INVALID (VDEC_MSG_BASE + 0) 45 #define VDEC_MSG_RESP_INPUT_BUFFER_DONE (VDEC_MSG_BASE + 1) 46 #define VDEC_MSG_RESP_OUTPUT_BUFFER_DONE (VDEC_MSG_BASE + 2) 47 #define VDEC_MSG_RESP_INPUT_FLUSHED (VDEC_MSG_BASE + 3) 48 #define VDEC_MSG_RESP_OUTPUT_FLUSHED (VDEC_MSG_BASE + 4) 49 #define VDEC_MSG_RESP_FLUSH_INPUT_DONE (VDEC_MSG_BASE + 5) 50 #define VDEC_MSG_RESP_FLUSH_OUTPUT_DONE (VDEC_MSG_BASE + 6) 51 #define VDEC_MSG_RESP_START_DONE (VDEC_MSG_BASE + 7) 52 #define VDEC_MSG_RESP_STOP_DONE (VDEC_MSG_BASE + 8) 53 #define VDEC_MSG_RESP_PAUSE_DONE (VDEC_MSG_BASE + 9) 54 #define VDEC_MSG_RESP_RESUME_DONE (VDEC_MSG_BASE + 10) 55 #define VDEC_MSG_RESP_RESOURCE_LOADED (VDEC_MSG_BASE + 11) 56 #define VDEC_EVT_RESOURCES_LOST (VDEC_MSG_BASE + 12) 57 #define VDEC_MSG_EVT_CONFIG_CHANGED (VDEC_MSG_BASE + 13) 58 #define VDEC_MSG_EVT_HW_ERROR (VDEC_MSG_BASE + 14) 59 #define VDEC_MSG_EVT_INFO_CONFIG_CHANGED (VDEC_MSG_BASE + 15) 60 #define VDEC_MSG_EVT_INFO_FIELD_DROPPED (VDEC_MSG_BASE + 16) 61 #define VDEC_MSG_EVT_HW_OVERLOAD (VDEC_MSG_BASE + 17) 62 #define VDEC_MSG_EVT_MAX_CLIENTS (VDEC_MSG_BASE + 18) 63 #define VDEC_MSG_EVT_HW_UNSUPPORTED (VDEC_MSG_BASE + 19) 64 65 /*Buffer flags bits masks.*/ 66 #define VDEC_BUFFERFLAG_EOS 0x00000001 67 #define VDEC_BUFFERFLAG_DECODEONLY 0x00000004 68 #define VDEC_BUFFERFLAG_DATACORRUPT 0x00000008 69 #define VDEC_BUFFERFLAG_ENDOFFRAME 0x00000010 70 #define VDEC_BUFFERFLAG_SYNCFRAME 0x00000020 71 #define VDEC_BUFFERFLAG_EXTRADATA 0x00000040 72 #define VDEC_BUFFERFLAG_CODECCONFIG 0x00000080 73 74 /*Post processing flags bit masks*/ 75 #define VDEC_EXTRADATA_NONE 0x001 76 #define VDEC_EXTRADATA_QP 0x004 77 #define VDEC_EXTRADATA_MB_ERROR_MAP 0x008 78 #define VDEC_EXTRADATA_SEI 0x010 79 #define VDEC_EXTRADATA_VUI 0x020 80 #define VDEC_EXTRADATA_VC1 0x040 81 82 #define VDEC_EXTRADATA_EXT_DATA 0x0800 83 #define VDEC_EXTRADATA_USER_DATA 0x1000 84 #define VDEC_EXTRADATA_EXT_BUFFER 0x2000 85 86 #define VDEC_CMDBASE 0x800 87 #define VDEC_CMD_SET_INTF_VERSION (VDEC_CMDBASE) 88 89 #define VDEC_IOCTL_MAGIC 'v' 90 91 struct vdec_ioctl_msg { 92 void *in; 93 void *out; 94 }; 95 96 /* CMD params: InputParam:enum vdec_codec 97 OutputParam: struct vdec_profile_level*/ 98 #define VDEC_IOCTL_GET_PROFILE_LEVEL_SUPPORTED \ 99 _IOWR(VDEC_IOCTL_MAGIC, 0, struct vdec_ioctl_msg) 100 101 /*CMD params:InputParam: NULL 102 OutputParam: uint32_t(bitmask)*/ 103 #define VDEC_IOCTL_GET_INTERLACE_FORMAT \ 104 _IOR(VDEC_IOCTL_MAGIC, 1, struct vdec_ioctl_msg) 105 106 /* CMD params: InputParam: enum vdec_codec 107 OutputParam: struct vdec_profile_level*/ 108 #define VDEC_IOCTL_GET_CURRENT_PROFILE_LEVEL \ 109 _IOWR(VDEC_IOCTL_MAGIC, 2, struct vdec_ioctl_msg) 110 111 /*CMD params: SET: InputParam: enum vdec_output_fromat OutputParam: NULL 112 GET: InputParam: NULL OutputParam: enum vdec_output_fromat*/ 113 #define VDEC_IOCTL_SET_OUTPUT_FORMAT \ 114 _IOWR(VDEC_IOCTL_MAGIC, 3, struct vdec_ioctl_msg) 115 #define VDEC_IOCTL_GET_OUTPUT_FORMAT \ 116 _IOWR(VDEC_IOCTL_MAGIC, 4, struct vdec_ioctl_msg) 117 118 /*CMD params: SET: InputParam: enum vdec_codec OutputParam: NULL 119 GET: InputParam: NULL OutputParam: enum vdec_codec*/ 120 #define VDEC_IOCTL_SET_CODEC \ 121 _IOW(VDEC_IOCTL_MAGIC, 5, struct vdec_ioctl_msg) 122 #define VDEC_IOCTL_GET_CODEC \ 123 _IOR(VDEC_IOCTL_MAGIC, 6, struct vdec_ioctl_msg) 124 125 /*CMD params: SET: InputParam: struct vdec_picsize outputparam: NULL 126 GET: InputParam: NULL outputparam: struct vdec_picsize*/ 127 #define VDEC_IOCTL_SET_PICRES \ 128 _IOW(VDEC_IOCTL_MAGIC, 7, struct vdec_ioctl_msg) 129 #define VDEC_IOCTL_GET_PICRES \ 130 _IOR(VDEC_IOCTL_MAGIC, 8, struct vdec_ioctl_msg) 131 132 #define VDEC_IOCTL_SET_EXTRADATA \ 133 _IOW(VDEC_IOCTL_MAGIC, 9, struct vdec_ioctl_msg) 134 #define VDEC_IOCTL_GET_EXTRADATA \ 135 _IOR(VDEC_IOCTL_MAGIC, 10, struct vdec_ioctl_msg) 136 137 #define VDEC_IOCTL_SET_SEQUENCE_HEADER \ 138 _IOW(VDEC_IOCTL_MAGIC, 11, struct vdec_ioctl_msg) 139 140 /* CMD params: SET: InputParam - vdec_allocatorproperty, OutputParam - NULL 141 GET: InputParam - NULL, OutputParam - vdec_allocatorproperty*/ 142 #define VDEC_IOCTL_SET_BUFFER_REQ \ 143 _IOW(VDEC_IOCTL_MAGIC, 12, struct vdec_ioctl_msg) 144 #define VDEC_IOCTL_GET_BUFFER_REQ \ 145 _IOR(VDEC_IOCTL_MAGIC, 13, struct vdec_ioctl_msg) 146 /* CMD params: InputParam - vdec_buffer, OutputParam - uint8_t** */ 147 #define VDEC_IOCTL_ALLOCATE_BUFFER \ 148 _IOWR(VDEC_IOCTL_MAGIC, 14, struct vdec_ioctl_msg) 149 /* CMD params: InputParam - uint8_t *, OutputParam - NULL.*/ 150 #define VDEC_IOCTL_FREE_BUFFER \ 151 _IOW(VDEC_IOCTL_MAGIC, 15, struct vdec_ioctl_msg) 152 153 /*CMD params: CMD: InputParam - struct vdec_setbuffer_cmd, OutputParam - NULL*/ 154 #define VDEC_IOCTL_SET_BUFFER \ 155 _IOW(VDEC_IOCTL_MAGIC, 16, struct vdec_ioctl_msg) 156 157 /* CMD params: InputParam - struct vdec_fillbuffer_cmd, OutputParam - NULL*/ 158 #define VDEC_IOCTL_FILL_OUTPUT_BUFFER \ 159 _IOW(VDEC_IOCTL_MAGIC, 17, struct vdec_ioctl_msg) 160 161 /*CMD params: InputParam - struct vdec_frameinfo , OutputParam - NULL*/ 162 #define VDEC_IOCTL_DECODE_FRAME \ 163 _IOW(VDEC_IOCTL_MAGIC, 18, struct vdec_ioctl_msg) 164 165 #define VDEC_IOCTL_LOAD_RESOURCES _IO(VDEC_IOCTL_MAGIC, 19) 166 #define VDEC_IOCTL_CMD_START _IO(VDEC_IOCTL_MAGIC, 20) 167 #define VDEC_IOCTL_CMD_STOP _IO(VDEC_IOCTL_MAGIC, 21) 168 #define VDEC_IOCTL_CMD_PAUSE _IO(VDEC_IOCTL_MAGIC, 22) 169 #define VDEC_IOCTL_CMD_RESUME _IO(VDEC_IOCTL_MAGIC, 23) 170 171 /*CMD params: InputParam - enum vdec_bufferflush , OutputParam - NULL */ 172 #define VDEC_IOCTL_CMD_FLUSH _IOW(VDEC_IOCTL_MAGIC, 24, struct vdec_ioctl_msg) 173 174 /* ======================================================== 175 * IOCTL for getting asynchronous notification from driver 176 * ========================================================*/ 177 178 /*IOCTL params: InputParam - NULL, OutputParam - struct vdec_msginfo*/ 179 #define VDEC_IOCTL_GET_NEXT_MSG \ 180 _IOR(VDEC_IOCTL_MAGIC, 25, struct vdec_ioctl_msg) 181 182 #define VDEC_IOCTL_STOP_NEXT_MSG _IO(VDEC_IOCTL_MAGIC, 26) 183 184 #define VDEC_IOCTL_GET_NUMBER_INSTANCES \ 185 _IOR(VDEC_IOCTL_MAGIC, 27, struct vdec_ioctl_msg) 186 187 #define VDEC_IOCTL_SET_PICTURE_ORDER \ 188 _IOW(VDEC_IOCTL_MAGIC, 28, struct vdec_ioctl_msg) 189 190 #define VDEC_IOCTL_SET_FRAME_RATE \ 191 _IOW(VDEC_IOCTL_MAGIC, 29, struct vdec_ioctl_msg) 192 193 #define VDEC_IOCTL_SET_H264_MV_BUFFER \ 194 _IOW(VDEC_IOCTL_MAGIC, 30, struct vdec_ioctl_msg) 195 196 #define VDEC_IOCTL_FREE_H264_MV_BUFFER \ 197 _IOW(VDEC_IOCTL_MAGIC, 31, struct vdec_ioctl_msg) 198 199 #define VDEC_IOCTL_GET_MV_BUFFER_SIZE \ 200 _IOR(VDEC_IOCTL_MAGIC, 32, struct vdec_ioctl_msg) 201 202 #define VDEC_IOCTL_SET_IDR_ONLY_DECODING \ 203 _IO(VDEC_IOCTL_MAGIC, 33) 204 205 #define VDEC_IOCTL_SET_CONT_ON_RECONFIG \ 206 _IO(VDEC_IOCTL_MAGIC, 34) 207 208 #define VDEC_IOCTL_SET_DISABLE_DMX \ 209 _IOW(VDEC_IOCTL_MAGIC, 35, struct vdec_ioctl_msg) 210 211 #define VDEC_IOCTL_GET_DISABLE_DMX \ 212 _IOR(VDEC_IOCTL_MAGIC, 36, struct vdec_ioctl_msg) 213 214 #define VDEC_IOCTL_GET_DISABLE_DMX_SUPPORT \ 215 _IOR(VDEC_IOCTL_MAGIC, 37, struct vdec_ioctl_msg) 216 217 #define VDEC_IOCTL_SET_PERF_CLK \ 218 _IOR(VDEC_IOCTL_MAGIC, 38, struct vdec_ioctl_msg) 219 220 #define VDEC_IOCTL_SET_META_BUFFERS \ 221 _IOW(VDEC_IOCTL_MAGIC, 39, struct vdec_ioctl_msg) 222 223 #define VDEC_IOCTL_FREE_META_BUFFERS \ 224 _IO(VDEC_IOCTL_MAGIC, 40) 225 226 enum vdec_picture { 227 PICTURE_TYPE_I, 228 PICTURE_TYPE_P, 229 PICTURE_TYPE_B, 230 PICTURE_TYPE_BI, 231 PICTURE_TYPE_SKIP, 232 PICTURE_TYPE_IDR, 233 PICTURE_TYPE_UNKNOWN 234 }; 235 236 enum vdec_buffer { 237 VDEC_BUFFER_TYPE_INPUT, 238 VDEC_BUFFER_TYPE_OUTPUT 239 }; 240 241 struct vdec_allocatorproperty { 242 enum vdec_buffer buffer_type; 243 uint32_t mincount; 244 uint32_t maxcount; 245 uint32_t actualcount; 246 size_t buffer_size; 247 uint32_t alignment; 248 uint32_t buf_poolid; 249 size_t meta_buffer_size; 250 }; 251 252 struct vdec_bufferpayload { 253 void *bufferaddr; 254 size_t buffer_len; 255 int pmem_fd; 256 size_t offset; 257 size_t mmaped_size; 258 }; 259 260 struct vdec_setbuffer_cmd { 261 enum vdec_buffer buffer_type; 262 struct vdec_bufferpayload buffer; 263 }; 264 265 struct vdec_fillbuffer_cmd { 266 struct vdec_bufferpayload buffer; 267 void *client_data; 268 }; 269 270 enum vdec_bufferflush { 271 VDEC_FLUSH_TYPE_INPUT, 272 VDEC_FLUSH_TYPE_OUTPUT, 273 VDEC_FLUSH_TYPE_ALL 274 }; 275 276 enum vdec_codec { 277 VDEC_CODECTYPE_H264 = 0x1, 278 VDEC_CODECTYPE_H263 = 0x2, 279 VDEC_CODECTYPE_MPEG4 = 0x3, 280 VDEC_CODECTYPE_DIVX_3 = 0x4, 281 VDEC_CODECTYPE_DIVX_4 = 0x5, 282 VDEC_CODECTYPE_DIVX_5 = 0x6, 283 VDEC_CODECTYPE_DIVX_6 = 0x7, 284 VDEC_CODECTYPE_XVID = 0x8, 285 VDEC_CODECTYPE_MPEG1 = 0x9, 286 VDEC_CODECTYPE_MPEG2 = 0xa, 287 VDEC_CODECTYPE_VC1 = 0xb, 288 VDEC_CODECTYPE_VC1_RCV = 0xc, 289 VDEC_CODECTYPE_HEVC = 0xd, 290 VDEC_CODECTYPE_MVC = 0xe, 291 VDEC_CODECTYPE_VP8 = 0xf, 292 VDEC_CODECTYPE_VP9 = 0x10, 293 }; 294 295 enum vdec_mpeg2_profile { 296 VDEC_MPEG2ProfileSimple = 0x1, 297 VDEC_MPEG2ProfileMain = 0x2, 298 VDEC_MPEG2Profile422 = 0x4, 299 VDEC_MPEG2ProfileSNR = 0x8, 300 VDEC_MPEG2ProfileSpatial = 0x10, 301 VDEC_MPEG2ProfileHigh = 0x20, 302 VDEC_MPEG2ProfileKhronosExtensions = 0x6F000000, 303 VDEC_MPEG2ProfileVendorStartUnused = 0x7F000000, 304 VDEC_MPEG2ProfileMax = 0x7FFFFFFF 305 }; 306 307 enum vdec_mpeg2_level { 308 309 VDEC_MPEG2LevelLL = 0x1, 310 VDEC_MPEG2LevelML = 0x2, 311 VDEC_MPEG2LevelH14 = 0x4, 312 VDEC_MPEG2LevelHL = 0x8, 313 VDEC_MPEG2LevelKhronosExtensions = 0x6F000000, 314 VDEC_MPEG2LevelVendorStartUnused = 0x7F000000, 315 VDEC_MPEG2LevelMax = 0x7FFFFFFF 316 }; 317 318 enum vdec_mpeg4_profile { 319 VDEC_MPEG4ProfileSimple = 0x01, 320 VDEC_MPEG4ProfileSimpleScalable = 0x02, 321 VDEC_MPEG4ProfileCore = 0x04, 322 VDEC_MPEG4ProfileMain = 0x08, 323 VDEC_MPEG4ProfileNbit = 0x10, 324 VDEC_MPEG4ProfileScalableTexture = 0x20, 325 VDEC_MPEG4ProfileSimpleFace = 0x40, 326 VDEC_MPEG4ProfileSimpleFBA = 0x80, 327 VDEC_MPEG4ProfileBasicAnimated = 0x100, 328 VDEC_MPEG4ProfileHybrid = 0x200, 329 VDEC_MPEG4ProfileAdvancedRealTime = 0x400, 330 VDEC_MPEG4ProfileCoreScalable = 0x800, 331 VDEC_MPEG4ProfileAdvancedCoding = 0x1000, 332 VDEC_MPEG4ProfileAdvancedCore = 0x2000, 333 VDEC_MPEG4ProfileAdvancedScalable = 0x4000, 334 VDEC_MPEG4ProfileAdvancedSimple = 0x8000, 335 VDEC_MPEG4ProfileKhronosExtensions = 0x6F000000, 336 VDEC_MPEG4ProfileVendorStartUnused = 0x7F000000, 337 VDEC_MPEG4ProfileMax = 0x7FFFFFFF 338 }; 339 340 enum vdec_mpeg4_level { 341 VDEC_MPEG4Level0 = 0x01, 342 VDEC_MPEG4Level0b = 0x02, 343 VDEC_MPEG4Level1 = 0x04, 344 VDEC_MPEG4Level2 = 0x08, 345 VDEC_MPEG4Level3 = 0x10, 346 VDEC_MPEG4Level4 = 0x20, 347 VDEC_MPEG4Level4a = 0x40, 348 VDEC_MPEG4Level5 = 0x80, 349 VDEC_MPEG4LevelKhronosExtensions = 0x6F000000, 350 VDEC_MPEG4LevelVendorStartUnused = 0x7F000000, 351 VDEC_MPEG4LevelMax = 0x7FFFFFFF 352 }; 353 354 enum vdec_avc_profile { 355 VDEC_AVCProfileBaseline = 0x01, 356 VDEC_AVCProfileMain = 0x02, 357 VDEC_AVCProfileExtended = 0x04, 358 VDEC_AVCProfileHigh = 0x08, 359 VDEC_AVCProfileHigh10 = 0x10, 360 VDEC_AVCProfileHigh422 = 0x20, 361 VDEC_AVCProfileHigh444 = 0x40, 362 VDEC_AVCProfileKhronosExtensions = 0x6F000000, 363 VDEC_AVCProfileVendorStartUnused = 0x7F000000, 364 VDEC_AVCProfileMax = 0x7FFFFFFF 365 }; 366 367 enum vdec_avc_level { 368 VDEC_AVCLevel1 = 0x01, 369 VDEC_AVCLevel1b = 0x02, 370 VDEC_AVCLevel11 = 0x04, 371 VDEC_AVCLevel12 = 0x08, 372 VDEC_AVCLevel13 = 0x10, 373 VDEC_AVCLevel2 = 0x20, 374 VDEC_AVCLevel21 = 0x40, 375 VDEC_AVCLevel22 = 0x80, 376 VDEC_AVCLevel3 = 0x100, 377 VDEC_AVCLevel31 = 0x200, 378 VDEC_AVCLevel32 = 0x400, 379 VDEC_AVCLevel4 = 0x800, 380 VDEC_AVCLevel41 = 0x1000, 381 VDEC_AVCLevel42 = 0x2000, 382 VDEC_AVCLevel5 = 0x4000, 383 VDEC_AVCLevel51 = 0x8000, 384 VDEC_AVCLevelKhronosExtensions = 0x6F000000, 385 VDEC_AVCLevelVendorStartUnused = 0x7F000000, 386 VDEC_AVCLevelMax = 0x7FFFFFFF 387 }; 388 389 enum vdec_divx_profile { 390 VDEC_DIVXProfile_qMobile = 0x01, 391 VDEC_DIVXProfile_Mobile = 0x02, 392 VDEC_DIVXProfile_HD = 0x04, 393 VDEC_DIVXProfile_Handheld = 0x08, 394 VDEC_DIVXProfile_Portable = 0x10, 395 VDEC_DIVXProfile_HomeTheater = 0x20 396 }; 397 398 enum vdec_xvid_profile { 399 VDEC_XVIDProfile_Simple = 0x1, 400 VDEC_XVIDProfile_Advanced_Realtime_Simple = 0x2, 401 VDEC_XVIDProfile_Advanced_Simple = 0x4 402 }; 403 404 enum vdec_xvid_level { 405 VDEC_XVID_LEVEL_S_L0 = 0x1, 406 VDEC_XVID_LEVEL_S_L1 = 0x2, 407 VDEC_XVID_LEVEL_S_L2 = 0x4, 408 VDEC_XVID_LEVEL_S_L3 = 0x8, 409 VDEC_XVID_LEVEL_ARTS_L1 = 0x10, 410 VDEC_XVID_LEVEL_ARTS_L2 = 0x20, 411 VDEC_XVID_LEVEL_ARTS_L3 = 0x40, 412 VDEC_XVID_LEVEL_ARTS_L4 = 0x80, 413 VDEC_XVID_LEVEL_AS_L0 = 0x100, 414 VDEC_XVID_LEVEL_AS_L1 = 0x200, 415 VDEC_XVID_LEVEL_AS_L2 = 0x400, 416 VDEC_XVID_LEVEL_AS_L3 = 0x800, 417 VDEC_XVID_LEVEL_AS_L4 = 0x1000 418 }; 419 420 enum vdec_h263profile { 421 VDEC_H263ProfileBaseline = 0x01, 422 VDEC_H263ProfileH320Coding = 0x02, 423 VDEC_H263ProfileBackwardCompatible = 0x04, 424 VDEC_H263ProfileISWV2 = 0x08, 425 VDEC_H263ProfileISWV3 = 0x10, 426 VDEC_H263ProfileHighCompression = 0x20, 427 VDEC_H263ProfileInternet = 0x40, 428 VDEC_H263ProfileInterlace = 0x80, 429 VDEC_H263ProfileHighLatency = 0x100, 430 VDEC_H263ProfileKhronosExtensions = 0x6F000000, 431 VDEC_H263ProfileVendorStartUnused = 0x7F000000, 432 VDEC_H263ProfileMax = 0x7FFFFFFF 433 }; 434 435 enum vdec_h263level { 436 VDEC_H263Level10 = 0x01, 437 VDEC_H263Level20 = 0x02, 438 VDEC_H263Level30 = 0x04, 439 VDEC_H263Level40 = 0x08, 440 VDEC_H263Level45 = 0x10, 441 VDEC_H263Level50 = 0x20, 442 VDEC_H263Level60 = 0x40, 443 VDEC_H263Level70 = 0x80, 444 VDEC_H263LevelKhronosExtensions = 0x6F000000, 445 VDEC_H263LevelVendorStartUnused = 0x7F000000, 446 VDEC_H263LevelMax = 0x7FFFFFFF 447 }; 448 449 enum vdec_wmv_format { 450 VDEC_WMVFormatUnused = 0x01, 451 VDEC_WMVFormat7 = 0x02, 452 VDEC_WMVFormat8 = 0x04, 453 VDEC_WMVFormat9 = 0x08, 454 VDEC_WMFFormatKhronosExtensions = 0x6F000000, 455 VDEC_WMFFormatVendorStartUnused = 0x7F000000, 456 VDEC_WMVFormatMax = 0x7FFFFFFF 457 }; 458 459 enum vdec_vc1_profile { 460 VDEC_VC1ProfileSimple = 0x1, 461 VDEC_VC1ProfileMain = 0x2, 462 VDEC_VC1ProfileAdvanced = 0x4 463 }; 464 465 enum vdec_vc1_level { 466 VDEC_VC1_LEVEL_S_Low = 0x1, 467 VDEC_VC1_LEVEL_S_Medium = 0x2, 468 VDEC_VC1_LEVEL_M_Low = 0x4, 469 VDEC_VC1_LEVEL_M_Medium = 0x8, 470 VDEC_VC1_LEVEL_M_High = 0x10, 471 VDEC_VC1_LEVEL_A_L0 = 0x20, 472 VDEC_VC1_LEVEL_A_L1 = 0x40, 473 VDEC_VC1_LEVEL_A_L2 = 0x80, 474 VDEC_VC1_LEVEL_A_L3 = 0x100, 475 VDEC_VC1_LEVEL_A_L4 = 0x200 476 }; 477 478 struct vdec_profile_level { 479 uint32_t profiles; 480 uint32_t levels; 481 }; 482 483 enum vdec_interlaced_format { 484 VDEC_InterlaceFrameProgressive = 0x1, 485 VDEC_InterlaceInterleaveFrameTopFieldFirst = 0x2, 486 VDEC_InterlaceInterleaveFrameBottomFieldFirst = 0x4 487 }; 488 489 #define VDEC_YUV_FORMAT_NV12_TP10_UBWC \ 490 VDEC_YUV_FORMAT_NV12_TP10_UBWC 491 492 enum vdec_output_fromat { 493 VDEC_YUV_FORMAT_NV12 = 0x1, 494 VDEC_YUV_FORMAT_TILE_4x2 = 0x2, 495 VDEC_YUV_FORMAT_NV12_UBWC = 0x3, 496 VDEC_YUV_FORMAT_NV12_TP10_UBWC = 0x4 497 }; 498 499 enum vdec_output_order { 500 VDEC_ORDER_DISPLAY = 0x1, 501 VDEC_ORDER_DECODE = 0x2 502 }; 503 504 struct vdec_picsize { 505 uint32_t frame_width; 506 uint32_t frame_height; 507 uint32_t stride; 508 uint32_t scan_lines; 509 }; 510 511 struct vdec_seqheader { 512 void *ptr_seqheader; 513 size_t seq_header_len; 514 int pmem_fd; 515 size_t pmem_offset; 516 }; 517 518 struct vdec_mberror { 519 void *ptr_errormap; 520 size_t err_mapsize; 521 }; 522 523 struct vdec_input_frameinfo { 524 void *bufferaddr; 525 size_t offset; 526 size_t datalen; 527 uint32_t flags; 528 int64_t timestamp; 529 void *client_data; 530 int pmem_fd; 531 size_t pmem_offset; 532 void *desc_addr; 533 uint32_t desc_size; 534 }; 535 536 struct vdec_framesize { 537 uint32_t left; 538 uint32_t top; 539 uint32_t right; 540 uint32_t bottom; 541 }; 542 543 struct vdec_aspectratioinfo { 544 uint32_t aspect_ratio; 545 uint32_t par_width; 546 uint32_t par_height; 547 }; 548 549 struct vdec_sep_metadatainfo { 550 void *metabufaddr; 551 uint32_t size; 552 int fd; 553 int offset; 554 uint32_t buffer_size; 555 }; 556 557 struct vdec_output_frameinfo { 558 void *bufferaddr; 559 size_t offset; 560 size_t len; 561 uint32_t flags; 562 int64_t time_stamp; 563 enum vdec_picture pic_type; 564 void *client_data; 565 void *input_frame_clientdata; 566 struct vdec_picsize picsize; 567 struct vdec_framesize framesize; 568 enum vdec_interlaced_format interlaced_format; 569 struct vdec_aspectratioinfo aspect_ratio_info; 570 struct vdec_sep_metadatainfo metadata_info; 571 }; 572 573 union vdec_msgdata { 574 struct vdec_output_frameinfo output_frame; 575 void *input_frame_clientdata; 576 }; 577 578 struct vdec_msginfo { 579 uint32_t status_code; 580 uint32_t msgcode; 581 union vdec_msgdata msgdata; 582 size_t msgdatasize; 583 }; 584 585 struct vdec_framerate { 586 unsigned long fps_denominator; 587 unsigned long fps_numerator; 588 }; 589 590 struct vdec_h264_mv{ 591 size_t size; 592 int count; 593 int pmem_fd; 594 int offset; 595 }; 596 597 struct vdec_mv_buff_size{ 598 int width; 599 int height; 600 int size; 601 int alignment; 602 }; 603 604 struct vdec_meta_buffers { 605 size_t size; 606 int count; 607 int pmem_fd; 608 int pmem_fd_iommu; 609 int offset; 610 }; 611 612 #endif /* end of macro _VDECDECODER_H_ */ 613
