1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef _UAPI_MSM_MDP_H_ 20 #define _UAPI_MSM_MDP_H_ 21 #include <linux/types.h> 22 #include <linux/fb.h> 23 #define MSMFB_IOCTL_MAGIC 'm' 24 #define MSMFB_GRP_DISP _IOW(MSMFB_IOCTL_MAGIC, 1, unsigned int) 25 #define MSMFB_BLIT _IOW(MSMFB_IOCTL_MAGIC, 2, unsigned int) 26 #define MSMFB_SUSPEND_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 128, unsigned int) 27 #define MSMFB_RESUME_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 129, unsigned int) 28 #define MSMFB_CURSOR _IOW(MSMFB_IOCTL_MAGIC, 130, struct fb_cursor) 29 #define MSMFB_SET_LUT _IOW(MSMFB_IOCTL_MAGIC, 131, struct fb_cmap) 30 #define MSMFB_HISTOGRAM _IOWR(MSMFB_IOCTL_MAGIC, 132, struct mdp_histogram_data) 31 #define MSMFB_GET_CCS_MATRIX _IOWR(MSMFB_IOCTL_MAGIC, 133, struct mdp_ccs) 32 #define MSMFB_SET_CCS_MATRIX _IOW(MSMFB_IOCTL_MAGIC, 134, struct mdp_ccs) 33 #define MSMFB_OVERLAY_SET _IOWR(MSMFB_IOCTL_MAGIC, 135, struct mdp_overlay) 34 #define MSMFB_OVERLAY_UNSET _IOW(MSMFB_IOCTL_MAGIC, 136, unsigned int) 35 #define MSMFB_OVERLAY_PLAY _IOW(MSMFB_IOCTL_MAGIC, 137, struct msmfb_overlay_data) 36 #define MSMFB_OVERLAY_QUEUE MSMFB_OVERLAY_PLAY 37 #define MSMFB_GET_PAGE_PROTECTION _IOR(MSMFB_IOCTL_MAGIC, 138, struct mdp_page_protection) 38 #define MSMFB_SET_PAGE_PROTECTION _IOW(MSMFB_IOCTL_MAGIC, 139, struct mdp_page_protection) 39 #define MSMFB_OVERLAY_GET _IOR(MSMFB_IOCTL_MAGIC, 140, struct mdp_overlay) 40 #define MSMFB_OVERLAY_PLAY_ENABLE _IOW(MSMFB_IOCTL_MAGIC, 141, unsigned int) 41 #define MSMFB_OVERLAY_BLT _IOWR(MSMFB_IOCTL_MAGIC, 142, struct msmfb_overlay_blt) 42 #define MSMFB_OVERLAY_BLT_OFFSET _IOW(MSMFB_IOCTL_MAGIC, 143, unsigned int) 43 #define MSMFB_HISTOGRAM_START _IOR(MSMFB_IOCTL_MAGIC, 144, struct mdp_histogram_start_req) 44 #define MSMFB_HISTOGRAM_STOP _IOR(MSMFB_IOCTL_MAGIC, 145, unsigned int) 45 #define MSMFB_NOTIFY_UPDATE _IOWR(MSMFB_IOCTL_MAGIC, 146, unsigned int) 46 #define MSMFB_OVERLAY_3D _IOWR(MSMFB_IOCTL_MAGIC, 147, struct msmfb_overlay_3d) 47 #define MSMFB_MIXER_INFO _IOWR(MSMFB_IOCTL_MAGIC, 148, struct msmfb_mixer_info_req) 48 #define MSMFB_OVERLAY_PLAY_WAIT _IOWR(MSMFB_IOCTL_MAGIC, 149, struct msmfb_overlay_data) 49 #define MSMFB_WRITEBACK_INIT _IO(MSMFB_IOCTL_MAGIC, 150) 50 #define MSMFB_WRITEBACK_START _IO(MSMFB_IOCTL_MAGIC, 151) 51 #define MSMFB_WRITEBACK_STOP _IO(MSMFB_IOCTL_MAGIC, 152) 52 #define MSMFB_WRITEBACK_QUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 153, struct msmfb_data) 53 #define MSMFB_WRITEBACK_DEQUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 154, struct msmfb_data) 54 #define MSMFB_WRITEBACK_TERMINATE _IO(MSMFB_IOCTL_MAGIC, 155) 55 #define MSMFB_MDP_PP _IOWR(MSMFB_IOCTL_MAGIC, 156, struct msmfb_mdp_pp) 56 #define MSMFB_OVERLAY_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 160, unsigned int) 57 #define MSMFB_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 161, unsigned int) 58 #define MSMFB_BUFFER_SYNC _IOW(MSMFB_IOCTL_MAGIC, 162, struct mdp_buf_sync) 59 #define MSMFB_OVERLAY_COMMIT _IO(MSMFB_IOCTL_MAGIC, 163) 60 #define MSMFB_DISPLAY_COMMIT _IOW(MSMFB_IOCTL_MAGIC, 164, struct mdp_display_commit) 61 #define MSMFB_METADATA_SET _IOW(MSMFB_IOCTL_MAGIC, 165, struct msmfb_metadata) 62 #define MSMFB_METADATA_GET _IOW(MSMFB_IOCTL_MAGIC, 166, struct msmfb_metadata) 63 #define MSMFB_WRITEBACK_SET_MIRRORING_HINT _IOW(MSMFB_IOCTL_MAGIC, 167, unsigned int) 64 #define MSMFB_ASYNC_BLIT _IOW(MSMFB_IOCTL_MAGIC, 168, unsigned int) 65 #define MSMFB_OVERLAY_PREPARE _IOWR(MSMFB_IOCTL_MAGIC, 169, struct mdp_overlay_list) 66 #define MSMFB_LPM_ENABLE _IOWR(MSMFB_IOCTL_MAGIC, 170, unsigned int) 67 #define MSMFB_MDP_PP_GET_FEATURE_VERSION _IOWR(MSMFB_IOCTL_MAGIC, 171, struct mdp_pp_feature_version) 68 #define FB_TYPE_3D_PANEL 0x10101010 69 #define MDP_IMGTYPE2_START 0x10000 70 #define MSMFB_DRIVER_VERSION 0xF9E8D701 71 #define MDP_IMGTYPE_END 0x100 72 #define MDSS_GET_MAJOR(rev) ((rev) >> 28) 73 #define MDSS_GET_MINOR(rev) (((rev) >> 16) & 0xFFF) 74 #define MDSS_GET_STEP(rev) ((rev) & 0xFFFF) 75 #define MDSS_GET_MAJOR_MINOR(rev) ((rev) >> 16) 76 #define IS_MDSS_MAJOR_MINOR_SAME(rev1,rev2) (MDSS_GET_MAJOR_MINOR((rev1)) == MDSS_GET_MAJOR_MINOR((rev2))) 77 #define MDSS_MDP_REV(major,minor,step) ((((major) & 0x000F) << 28) | (((minor) & 0x0FFF) << 16) | ((step) & 0xFFFF)) 78 #define MDSS_MDP_HW_REV_100 MDSS_MDP_REV(1, 0, 0) 79 #define MDSS_MDP_HW_REV_101 MDSS_MDP_REV(1, 1, 0) 80 #define MDSS_MDP_HW_REV_101_1 MDSS_MDP_REV(1, 1, 1) 81 #define MDSS_MDP_HW_REV_101_2 MDSS_MDP_REV(1, 1, 2) 82 #define MDSS_MDP_HW_REV_102 MDSS_MDP_REV(1, 2, 0) 83 #define MDSS_MDP_HW_REV_102_1 MDSS_MDP_REV(1, 2, 1) 84 #define MDSS_MDP_HW_REV_103 MDSS_MDP_REV(1, 3, 0) 85 #define MDSS_MDP_HW_REV_103_1 MDSS_MDP_REV(1, 3, 1) 86 #define MDSS_MDP_HW_REV_105 MDSS_MDP_REV(1, 5, 0) 87 #define MDSS_MDP_HW_REV_106 MDSS_MDP_REV(1, 6, 0) 88 #define MDSS_MDP_HW_REV_107 MDSS_MDP_REV(1, 7, 0) 89 #define MDSS_MDP_HW_REV_107_1 MDSS_MDP_REV(1, 7, 1) 90 #define MDSS_MDP_HW_REV_107_2 MDSS_MDP_REV(1, 7, 2) 91 #define MDSS_MDP_HW_REV_108 MDSS_MDP_REV(1, 8, 0) 92 #define MDSS_MDP_HW_REV_109 MDSS_MDP_REV(1, 9, 0) 93 #define MDSS_MDP_HW_REV_110 MDSS_MDP_REV(1, 10, 0) 94 #define MDSS_MDP_HW_REV_200 MDSS_MDP_REV(2, 0, 0) 95 #define MDSS_MDP_HW_REV_112 MDSS_MDP_REV(1, 12, 0) 96 #define MDSS_MDP_HW_REV_114 MDSS_MDP_REV(1, 14, 0) 97 #define MDSS_MDP_HW_REV_115 MDSS_MDP_REV(1, 15, 0) 98 #define MDSS_MDP_HW_REV_116 MDSS_MDP_REV(1, 16, 0) 99 #define MDSS_MDP_HW_REV_300 MDSS_MDP_REV(3, 0, 0) 100 #define MDSS_MDP_HW_REV_301 MDSS_MDP_REV(3, 0, 1) 101 enum { 102 NOTIFY_UPDATE_INIT, 103 NOTIFY_UPDATE_DEINIT, 104 NOTIFY_UPDATE_START, 105 NOTIFY_UPDATE_STOP, 106 NOTIFY_UPDATE_POWER_OFF, 107 }; 108 enum { 109 NOTIFY_TYPE_NO_UPDATE, 110 NOTIFY_TYPE_SUSPEND, 111 NOTIFY_TYPE_UPDATE, 112 NOTIFY_TYPE_BL_UPDATE, 113 NOTIFY_TYPE_BL_AD_ATTEN_UPDATE, 114 }; 115 enum { 116 MDP_RGB_565, 117 MDP_XRGB_8888, 118 MDP_Y_CBCR_H2V2, 119 MDP_Y_CBCR_H2V2_ADRENO, 120 MDP_ARGB_8888, 121 MDP_RGB_888, 122 MDP_Y_CRCB_H2V2, 123 MDP_YCRYCB_H2V1, 124 MDP_CBYCRY_H2V1, 125 MDP_Y_CRCB_H2V1, 126 MDP_Y_CBCR_H2V1, 127 MDP_Y_CRCB_H1V2, 128 MDP_Y_CBCR_H1V2, 129 MDP_RGBA_8888, 130 MDP_BGRA_8888, 131 MDP_RGBX_8888, 132 MDP_Y_CRCB_H2V2_TILE, 133 MDP_Y_CBCR_H2V2_TILE, 134 MDP_Y_CR_CB_H2V2, 135 MDP_Y_CR_CB_GH2V2, 136 MDP_Y_CB_CR_H2V2, 137 MDP_Y_CRCB_H1V1, 138 MDP_Y_CBCR_H1V1, 139 MDP_YCRCB_H1V1, 140 MDP_YCBCR_H1V1, 141 MDP_BGR_565, 142 MDP_BGR_888, 143 MDP_Y_CBCR_H2V2_VENUS, 144 MDP_BGRX_8888, 145 MDP_RGBA_8888_TILE, 146 MDP_ARGB_8888_TILE, 147 MDP_ABGR_8888_TILE, 148 MDP_BGRA_8888_TILE, 149 MDP_RGBX_8888_TILE, 150 MDP_XRGB_8888_TILE, 151 MDP_XBGR_8888_TILE, 152 MDP_BGRX_8888_TILE, 153 MDP_YCBYCR_H2V1, 154 MDP_RGB_565_TILE, 155 MDP_BGR_565_TILE, 156 MDP_ARGB_1555, 157 MDP_RGBA_5551, 158 MDP_ARGB_4444, 159 MDP_RGBA_4444, 160 MDP_RGB_565_UBWC, 161 MDP_RGBA_8888_UBWC, 162 MDP_Y_CBCR_H2V2_UBWC, 163 MDP_RGBX_8888_UBWC, 164 MDP_Y_CRCB_H2V2_VENUS, 165 MDP_IMGTYPE_LIMIT, 166 MDP_RGB_BORDERFILL, 167 MDP_XRGB_1555, 168 MDP_RGBX_5551, 169 MDP_XRGB_4444, 170 MDP_RGBX_4444, 171 MDP_ABGR_1555, 172 MDP_BGRA_5551, 173 MDP_XBGR_1555, 174 MDP_BGRX_5551, 175 MDP_ABGR_4444, 176 MDP_BGRA_4444, 177 MDP_XBGR_4444, 178 MDP_BGRX_4444, 179 MDP_ABGR_8888, 180 MDP_XBGR_8888, 181 MDP_RGBA_1010102, 182 MDP_ARGB_2101010, 183 MDP_RGBX_1010102, 184 MDP_XRGB_2101010, 185 MDP_BGRA_1010102, 186 MDP_ABGR_2101010, 187 MDP_BGRX_1010102, 188 MDP_XBGR_2101010, 189 MDP_RGBA_1010102_UBWC, 190 MDP_RGBX_1010102_UBWC, 191 MDP_Y_CBCR_H2V2_P010, 192 MDP_Y_CBCR_H2V2_TP10_UBWC, 193 MDP_CRYCBY_H2V1, 194 MDP_IMGTYPE_LIMIT1 = MDP_IMGTYPE_END, 195 MDP_FB_FORMAT = MDP_IMGTYPE2_START, 196 MDP_IMGTYPE_LIMIT2 197 }; 198 #define MDP_CRYCBY_H2V1 MDP_CRYCBY_H2V1 199 enum { 200 PMEM_IMG, 201 FB_IMG, 202 }; 203 enum { 204 HSIC_HUE = 0, 205 HSIC_SAT, 206 HSIC_INT, 207 HSIC_CON, 208 NUM_HSIC_PARAM, 209 }; 210 enum mdss_mdp_max_bw_mode { 211 MDSS_MAX_BW_LIMIT_DEFAULT = 0x1, 212 MDSS_MAX_BW_LIMIT_CAMERA = 0x2, 213 MDSS_MAX_BW_LIMIT_HFLIP = 0x4, 214 MDSS_MAX_BW_LIMIT_VFLIP = 0x8, 215 }; 216 #define MDSS_MDP_ROT_ONLY 0x80 217 #define MDSS_MDP_RIGHT_MIXER 0x100 218 #define MDSS_MDP_DUAL_PIPE 0x200 219 #define MDP_ROT_NOP 0 220 #define MDP_FLIP_LR 0x1 221 #define MDP_FLIP_UD 0x2 222 #define MDP_ROT_90 0x4 223 #define MDP_ROT_180 (MDP_FLIP_UD | MDP_FLIP_LR) 224 #define MDP_ROT_270 (MDP_ROT_90 | MDP_FLIP_UD | MDP_FLIP_LR) 225 #define MDP_DITHER 0x8 226 #define MDP_BLUR 0x10 227 #define MDP_BLEND_FG_PREMULT 0x20000 228 #define MDP_IS_FG 0x40000 229 #define MDP_SOLID_FILL 0x00000020 230 #define MDP_VPU_PIPE 0x00000040 231 #define MDP_DEINTERLACE 0x80000000 232 #define MDP_SHARPENING 0x40000000 233 #define MDP_NO_DMA_BARRIER_START 0x20000000 234 #define MDP_NO_DMA_BARRIER_END 0x10000000 235 #define MDP_NO_BLIT 0x08000000 236 #define MDP_BLIT_WITH_DMA_BARRIERS 0x000 237 #define MDP_BLIT_WITH_NO_DMA_BARRIERS (MDP_NO_DMA_BARRIER_START | MDP_NO_DMA_BARRIER_END) 238 #define MDP_BLIT_SRC_GEM 0x04000000 239 #define MDP_BLIT_DST_GEM 0x02000000 240 #define MDP_BLIT_NON_CACHED 0x01000000 241 #define MDP_OV_PIPE_SHARE 0x00800000 242 #define MDP_DEINTERLACE_ODD 0x00400000 243 #define MDP_OV_PLAY_NOWAIT 0x00200000 244 #define MDP_SOURCE_ROTATED_90 0x00100000 245 #define MDP_OVERLAY_PP_CFG_EN 0x00080000 246 #define MDP_BACKEND_COMPOSITION 0x00040000 247 #define MDP_BORDERFILL_SUPPORTED 0x00010000 248 #define MDP_SECURE_OVERLAY_SESSION 0x00008000 249 #define MDP_SECURE_DISPLAY_OVERLAY_SESSION 0x00002000 250 #define MDP_OV_PIPE_FORCE_DMA 0x00004000 251 #define MDP_MEMORY_ID_TYPE_FB 0x00001000 252 #define MDP_BWC_EN 0x00000400 253 #define MDP_DECIMATION_EN 0x00000800 254 #define MDP_SMP_FORCE_ALLOC 0x00200000 255 #define MDP_TRANSP_NOP 0xffffffff 256 #define MDP_ALPHA_NOP 0xff 257 #define MDP_FB_PAGE_PROTECTION_NONCACHED (0) 258 #define MDP_FB_PAGE_PROTECTION_WRITECOMBINE (1) 259 #define MDP_FB_PAGE_PROTECTION_WRITETHROUGHCACHE (2) 260 #define MDP_FB_PAGE_PROTECTION_WRITEBACKCACHE (3) 261 #define MDP_FB_PAGE_PROTECTION_WRITEBACKWACACHE (4) 262 #define MDP_FB_PAGE_PROTECTION_INVALID (5) 263 #define MDP_NUM_FB_PAGE_PROTECTION_VALUES (5) 264 struct mdp_rect { 265 uint32_t x; 266 uint32_t y; 267 uint32_t w; 268 uint32_t h; 269 }; 270 struct mdp_img { 271 uint32_t width; 272 uint32_t height; 273 uint32_t format; 274 uint32_t offset; 275 int memory_id; 276 uint32_t priv; 277 }; 278 struct mult_factor { 279 uint32_t numer; 280 uint32_t denom; 281 }; 282 #define MDP_CCS_RGB2YUV 0 283 #define MDP_CCS_YUV2RGB 1 284 #define MDP_CCS_SIZE 9 285 #define MDP_BV_SIZE 3 286 struct mdp_ccs { 287 int direction; 288 uint16_t ccs[MDP_CCS_SIZE]; 289 uint16_t bv[MDP_BV_SIZE]; 290 }; 291 struct mdp_csc { 292 int id; 293 uint32_t csc_mv[9]; 294 uint32_t csc_pre_bv[3]; 295 uint32_t csc_post_bv[3]; 296 uint32_t csc_pre_lv[6]; 297 uint32_t csc_post_lv[6]; 298 }; 299 #define MDP_BLIT_REQ_VERSION 3 300 struct color { 301 uint32_t r; 302 uint32_t g; 303 uint32_t b; 304 uint32_t alpha; 305 }; 306 struct mdp_blit_req { 307 struct mdp_img src; 308 struct mdp_img dst; 309 struct mdp_rect src_rect; 310 struct mdp_rect dst_rect; 311 struct color const_color; 312 uint32_t alpha; 313 uint32_t transp_mask; 314 uint32_t flags; 315 int sharpening_strength; 316 uint8_t color_space; 317 uint32_t fps; 318 }; 319 struct mdp_blit_req_list { 320 uint32_t count; 321 struct mdp_blit_req req[]; 322 }; 323 #define MSMFB_DATA_VERSION 2 324 struct msmfb_data { 325 uint32_t offset; 326 int memory_id; 327 int id; 328 uint32_t flags; 329 uint32_t priv; 330 uint32_t iova; 331 }; 332 #define MSMFB_NEW_REQUEST - 1 333 struct msmfb_overlay_data { 334 uint32_t id; 335 struct msmfb_data data; 336 uint32_t version_key; 337 struct msmfb_data plane1_data; 338 struct msmfb_data plane2_data; 339 struct msmfb_data dst_data; 340 }; 341 struct msmfb_img { 342 uint32_t width; 343 uint32_t height; 344 uint32_t format; 345 }; 346 #define MSMFB_WRITEBACK_DEQUEUE_BLOCKING 0x1 347 struct msmfb_writeback_data { 348 struct msmfb_data buf_info; 349 struct msmfb_img img; 350 }; 351 #define MDP_PP_OPS_ENABLE 0x1 352 #define MDP_PP_OPS_READ 0x2 353 #define MDP_PP_OPS_WRITE 0x4 354 #define MDP_PP_OPS_DISABLE 0x8 355 #define MDP_PP_IGC_FLAG_ROM0 0x10 356 #define MDP_PP_IGC_FLAG_ROM1 0x20 357 #define MDSS_PP_DSPP_CFG 0x000 358 #define MDSS_PP_SSPP_CFG 0x100 359 #define MDSS_PP_LM_CFG 0x200 360 #define MDSS_PP_WB_CFG 0x300 361 #define MDSS_PP_ARG_MASK 0x3C00 362 #define MDSS_PP_ARG_NUM 4 363 #define MDSS_PP_ARG_SHIFT 10 364 #define MDSS_PP_LOCATION_MASK 0x0300 365 #define MDSS_PP_LOGICAL_MASK 0x00FF 366 #define MDSS_PP_ADD_ARG(var,arg) ((var) | (0x1 << (MDSS_PP_ARG_SHIFT + (arg)))) 367 #define PP_ARG(x,var) ((var) & (0x1 << (MDSS_PP_ARG_SHIFT + (x)))) 368 #define PP_LOCAT(var) ((var) & MDSS_PP_LOCATION_MASK) 369 #define PP_BLOCK(var) ((var) & MDSS_PP_LOGICAL_MASK) 370 struct mdp_qseed_cfg { 371 uint32_t table_num; 372 uint32_t ops; 373 uint32_t len; 374 uint32_t * data; 375 }; 376 struct mdp_sharp_cfg { 377 uint32_t flags; 378 uint32_t strength; 379 uint32_t edge_thr; 380 uint32_t smooth_thr; 381 uint32_t noise_thr; 382 }; 383 struct mdp_qseed_cfg_data { 384 uint32_t block; 385 struct mdp_qseed_cfg qseed_data; 386 }; 387 #define MDP_OVERLAY_PP_CSC_CFG 0x1 388 #define MDP_OVERLAY_PP_QSEED_CFG 0x2 389 #define MDP_OVERLAY_PP_PA_CFG 0x4 390 #define MDP_OVERLAY_PP_IGC_CFG 0x8 391 #define MDP_OVERLAY_PP_SHARP_CFG 0x10 392 #define MDP_OVERLAY_PP_HIST_CFG 0x20 393 #define MDP_OVERLAY_PP_HIST_LUT_CFG 0x40 394 #define MDP_OVERLAY_PP_PA_V2_CFG 0x80 395 #define MDP_OVERLAY_PP_PCC_CFG 0x100 396 #define MDP_CSC_FLAG_ENABLE 0x1 397 #define MDP_CSC_FLAG_YUV_IN 0x2 398 #define MDP_CSC_FLAG_YUV_OUT 0x4 399 #define MDP_CSC_MATRIX_COEFF_SIZE 9 400 #define MDP_CSC_CLAMP_SIZE 6 401 #define MDP_CSC_BIAS_SIZE 3 402 struct mdp_csc_cfg { 403 uint32_t flags; 404 uint32_t csc_mv[MDP_CSC_MATRIX_COEFF_SIZE]; 405 uint32_t csc_pre_bv[MDP_CSC_BIAS_SIZE]; 406 uint32_t csc_post_bv[MDP_CSC_BIAS_SIZE]; 407 uint32_t csc_pre_lv[MDP_CSC_CLAMP_SIZE]; 408 uint32_t csc_post_lv[MDP_CSC_CLAMP_SIZE]; 409 }; 410 struct mdp_csc_cfg_data { 411 uint32_t block; 412 struct mdp_csc_cfg csc_data; 413 }; 414 struct mdp_pa_cfg { 415 uint32_t flags; 416 uint32_t hue_adj; 417 uint32_t sat_adj; 418 uint32_t val_adj; 419 uint32_t cont_adj; 420 }; 421 struct mdp_pa_mem_col_cfg { 422 uint32_t color_adjust_p0; 423 uint32_t color_adjust_p1; 424 uint32_t hue_region; 425 uint32_t sat_region; 426 uint32_t val_region; 427 }; 428 #define MDP_SIX_ZONE_LUT_SIZE 384 429 #define MDP_PP_PA_HUE_ENABLE 0x10 430 #define MDP_PP_PA_SAT_ENABLE 0x20 431 #define MDP_PP_PA_VAL_ENABLE 0x40 432 #define MDP_PP_PA_CONT_ENABLE 0x80 433 #define MDP_PP_PA_SIX_ZONE_ENABLE 0x100 434 #define MDP_PP_PA_SKIN_ENABLE 0x200 435 #define MDP_PP_PA_SKY_ENABLE 0x400 436 #define MDP_PP_PA_FOL_ENABLE 0x800 437 #define MDP_PP_PA_MEM_PROT_HUE_EN 0x1 438 #define MDP_PP_PA_MEM_PROT_SAT_EN 0x2 439 #define MDP_PP_PA_MEM_PROT_VAL_EN 0x4 440 #define MDP_PP_PA_MEM_PROT_CONT_EN 0x8 441 #define MDP_PP_PA_MEM_PROT_SIX_EN 0x10 442 #define MDP_PP_PA_MEM_PROT_BLEND_EN 0x20 443 #define MDP_PP_PA_HUE_MASK 0x1000 444 #define MDP_PP_PA_SAT_MASK 0x2000 445 #define MDP_PP_PA_VAL_MASK 0x4000 446 #define MDP_PP_PA_CONT_MASK 0x8000 447 #define MDP_PP_PA_SIX_ZONE_HUE_MASK 0x10000 448 #define MDP_PP_PA_SIX_ZONE_SAT_MASK 0x20000 449 #define MDP_PP_PA_SIX_ZONE_VAL_MASK 0x40000 450 #define MDP_PP_PA_MEM_COL_SKIN_MASK 0x80000 451 #define MDP_PP_PA_MEM_COL_SKY_MASK 0x100000 452 #define MDP_PP_PA_MEM_COL_FOL_MASK 0x200000 453 #define MDP_PP_PA_MEM_PROTECT_EN 0x400000 454 #define MDP_PP_PA_SAT_ZERO_EXP_EN 0x800000 455 #define MDP_PP_PA_LEFT_HOLD 0x1 456 #define MDP_PP_PA_RIGHT_HOLD 0x2 457 struct mdp_pa_v2_data { 458 uint32_t flags; 459 uint32_t global_hue_adj; 460 uint32_t global_sat_adj; 461 uint32_t global_val_adj; 462 uint32_t global_cont_adj; 463 struct mdp_pa_mem_col_cfg skin_cfg; 464 struct mdp_pa_mem_col_cfg sky_cfg; 465 struct mdp_pa_mem_col_cfg fol_cfg; 466 uint32_t six_zone_len; 467 uint32_t six_zone_thresh; 468 uint32_t * six_zone_curve_p0; 469 uint32_t * six_zone_curve_p1; 470 }; 471 struct mdp_pa_mem_col_data_v1_7 { 472 uint32_t color_adjust_p0; 473 uint32_t color_adjust_p1; 474 uint32_t color_adjust_p2; 475 uint32_t blend_gain; 476 uint8_t sat_hold; 477 uint8_t val_hold; 478 uint32_t hue_region; 479 uint32_t sat_region; 480 uint32_t val_region; 481 }; 482 struct mdp_pa_data_v1_7 { 483 uint32_t mode; 484 uint32_t global_hue_adj; 485 uint32_t global_sat_adj; 486 uint32_t global_val_adj; 487 uint32_t global_cont_adj; 488 struct mdp_pa_mem_col_data_v1_7 skin_cfg; 489 struct mdp_pa_mem_col_data_v1_7 sky_cfg; 490 struct mdp_pa_mem_col_data_v1_7 fol_cfg; 491 uint32_t six_zone_thresh; 492 uint32_t six_zone_adj_p0; 493 uint32_t six_zone_adj_p1; 494 uint8_t six_zone_sat_hold; 495 uint8_t six_zone_val_hold; 496 uint32_t six_zone_len; 497 uint32_t * six_zone_curve_p0; 498 uint32_t * six_zone_curve_p1; 499 }; 500 struct mdp_pa_v2_cfg_data { 501 uint32_t version; 502 uint32_t block; 503 uint32_t flags; 504 struct mdp_pa_v2_data pa_v2_data; 505 void * cfg_payload; 506 }; 507 enum { 508 mdp_igc_rec601 = 1, 509 mdp_igc_rec709, 510 mdp_igc_srgb, 511 mdp_igc_custom, 512 mdp_igc_rec_max, 513 }; 514 struct mdp_igc_lut_data { 515 uint32_t block; 516 uint32_t version; 517 uint32_t len, ops; 518 uint32_t * c0_c1_data; 519 uint32_t * c2_data; 520 void * cfg_payload; 521 }; 522 struct mdp_igc_lut_data_v1_7 { 523 uint32_t table_fmt; 524 uint32_t len; 525 uint32_t * c0_c1_data; 526 uint32_t * c2_data; 527 }; 528 struct mdp_histogram_cfg { 529 uint32_t ops; 530 uint32_t block; 531 uint8_t frame_cnt; 532 uint8_t bit_mask; 533 uint16_t num_bins; 534 }; 535 struct mdp_hist_lut_data_v1_7 { 536 uint32_t len; 537 uint32_t * data; 538 }; 539 struct mdp_hist_lut_data { 540 uint32_t block; 541 uint32_t version; 542 uint32_t hist_lut_first; 543 uint32_t ops; 544 uint32_t len; 545 uint32_t * data; 546 void * cfg_payload; 547 }; 548 struct mdp_pcc_coeff { 549 uint32_t c, r, g, b, rr, gg, bb, rg, gb, rb, rgb_0, rgb_1; 550 }; 551 struct mdp_pcc_coeff_v1_7 { 552 uint32_t c, r, g, b, rg, gb, rb, rgb; 553 }; 554 struct mdp_pcc_data_v1_7 { 555 struct mdp_pcc_coeff_v1_7 r, g, b; 556 }; 557 struct mdp_pcc_cfg_data { 558 uint32_t version; 559 uint32_t block; 560 uint32_t ops; 561 struct mdp_pcc_coeff r, g, b; 562 void * cfg_payload; 563 }; 564 enum { 565 mdp_lut_igc, 566 mdp_lut_pgc, 567 mdp_lut_hist, 568 mdp_lut_rgb, 569 mdp_lut_max, 570 }; 571 struct mdp_overlay_pp_params { 572 uint32_t config_ops; 573 struct mdp_csc_cfg csc_cfg; 574 struct mdp_qseed_cfg qseed_cfg[2]; 575 struct mdp_pa_cfg pa_cfg; 576 struct mdp_pa_v2_data pa_v2_cfg; 577 struct mdp_igc_lut_data igc_cfg; 578 struct mdp_sharp_cfg sharp_cfg; 579 struct mdp_histogram_cfg hist_cfg; 580 struct mdp_hist_lut_data hist_lut_cfg; 581 struct mdp_pa_v2_cfg_data pa_v2_cfg_data; 582 struct mdp_pcc_cfg_data pcc_cfg_data; 583 }; 584 enum mdss_mdp_blend_op { 585 BLEND_OP_NOT_DEFINED = 0, 586 BLEND_OP_OPAQUE, 587 BLEND_OP_PREMULTIPLIED, 588 BLEND_OP_COVERAGE, 589 BLEND_OP_MAX, 590 }; 591 #define DECIMATED_DIMENSION(dim,deci) (((dim) + ((1 << (deci)) - 1)) >> (deci)) 592 #define MAX_PLANES 4 593 struct mdp_scale_data { 594 uint8_t enable_pxl_ext; 595 int init_phase_x[MAX_PLANES]; 596 int phase_step_x[MAX_PLANES]; 597 int init_phase_y[MAX_PLANES]; 598 int phase_step_y[MAX_PLANES]; 599 int num_ext_pxls_left[MAX_PLANES]; 600 int num_ext_pxls_right[MAX_PLANES]; 601 int num_ext_pxls_top[MAX_PLANES]; 602 int num_ext_pxls_btm[MAX_PLANES]; 603 int left_ftch[MAX_PLANES]; 604 int left_rpt[MAX_PLANES]; 605 int right_ftch[MAX_PLANES]; 606 int right_rpt[MAX_PLANES]; 607 int top_rpt[MAX_PLANES]; 608 int btm_rpt[MAX_PLANES]; 609 int top_ftch[MAX_PLANES]; 610 int btm_ftch[MAX_PLANES]; 611 uint32_t roi_w[MAX_PLANES]; 612 }; 613 enum mdp_overlay_pipe_type { 614 PIPE_TYPE_AUTO = 0, 615 PIPE_TYPE_VIG, 616 PIPE_TYPE_RGB, 617 PIPE_TYPE_DMA, 618 PIPE_TYPE_CURSOR, 619 PIPE_TYPE_MAX, 620 }; 621 struct mdp_overlay { 622 struct msmfb_img src; 623 struct mdp_rect src_rect; 624 struct mdp_rect dst_rect; 625 uint32_t z_order; 626 uint32_t is_fg; 627 uint32_t alpha; 628 uint32_t blend_op; 629 uint32_t transp_mask; 630 uint32_t flags; 631 uint32_t pipe_type; 632 uint32_t id; 633 uint8_t priority; 634 uint32_t user_data[6]; 635 uint32_t bg_color; 636 uint8_t horz_deci; 637 uint8_t vert_deci; 638 struct mdp_overlay_pp_params overlay_pp_cfg; 639 struct mdp_scale_data scale; 640 uint8_t color_space; 641 uint32_t frame_rate; 642 }; 643 struct msmfb_overlay_3d { 644 uint32_t is_3d; 645 uint32_t width; 646 uint32_t height; 647 }; 648 struct msmfb_overlay_blt { 649 uint32_t enable; 650 uint32_t offset; 651 uint32_t width; 652 uint32_t height; 653 uint32_t bpp; 654 }; 655 struct mdp_histogram { 656 uint32_t frame_cnt; 657 uint32_t bin_cnt; 658 uint32_t * r; 659 uint32_t * g; 660 uint32_t * b; 661 }; 662 #define MISR_CRC_BATCH_SIZE 32 663 enum { 664 DISPLAY_MISR_EDP, 665 DISPLAY_MISR_DSI0, 666 DISPLAY_MISR_DSI1, 667 DISPLAY_MISR_HDMI, 668 DISPLAY_MISR_LCDC, 669 DISPLAY_MISR_MDP, 670 DISPLAY_MISR_ATV, 671 DISPLAY_MISR_DSI_CMD, 672 DISPLAY_MISR_MAX 673 }; 674 enum { 675 MISR_OP_NONE, 676 MISR_OP_SFM, 677 MISR_OP_MFM, 678 MISR_OP_BM, 679 MISR_OP_MAX 680 }; 681 struct mdp_misr { 682 uint32_t block_id; 683 uint32_t frame_count; 684 uint32_t crc_op_mode; 685 uint32_t crc_value[MISR_CRC_BATCH_SIZE]; 686 }; 687 enum { 688 MDP_BLOCK_RESERVED = 0, 689 MDP_BLOCK_OVERLAY_0, 690 MDP_BLOCK_OVERLAY_1, 691 MDP_BLOCK_VG_1, 692 MDP_BLOCK_VG_2, 693 MDP_BLOCK_RGB_1, 694 MDP_BLOCK_RGB_2, 695 MDP_BLOCK_DMA_P, 696 MDP_BLOCK_DMA_S, 697 MDP_BLOCK_DMA_E, 698 MDP_BLOCK_OVERLAY_2, 699 MDP_LOGICAL_BLOCK_DISP_0 = 0x10, 700 MDP_LOGICAL_BLOCK_DISP_1, 701 MDP_LOGICAL_BLOCK_DISP_2, 702 MDP_BLOCK_MAX, 703 }; 704 struct mdp_histogram_start_req { 705 uint32_t block; 706 uint8_t frame_cnt; 707 uint8_t bit_mask; 708 uint16_t num_bins; 709 }; 710 struct mdp_histogram_data { 711 uint32_t block; 712 uint32_t bin_cnt; 713 uint32_t * c0; 714 uint32_t * c1; 715 uint32_t * c2; 716 uint32_t * extra_info; 717 }; 718 #define GC_LUT_ENTRIES_V1_7 512 719 struct mdp_ar_gc_lut_data { 720 uint32_t x_start; 721 uint32_t slope; 722 uint32_t offset; 723 }; 724 #define MDP_PP_PGC_ROUNDING_ENABLE 0x10 725 struct mdp_pgc_lut_data { 726 uint32_t version; 727 uint32_t block; 728 uint32_t flags; 729 uint8_t num_r_stages; 730 uint8_t num_g_stages; 731 uint8_t num_b_stages; 732 struct mdp_ar_gc_lut_data * r_data; 733 struct mdp_ar_gc_lut_data * g_data; 734 struct mdp_ar_gc_lut_data * b_data; 735 void * cfg_payload; 736 }; 737 #define PGC_LUT_ENTRIES 1024 738 struct mdp_pgc_lut_data_v1_7 { 739 uint32_t len; 740 uint32_t * c0_data; 741 uint32_t * c1_data; 742 uint32_t * c2_data; 743 }; 744 struct mdp_rgb_lut_data { 745 uint32_t flags; 746 uint32_t lut_type; 747 struct fb_cmap cmap; 748 }; 749 enum { 750 mdp_rgb_lut_gc, 751 mdp_rgb_lut_hist, 752 }; 753 struct mdp_lut_cfg_data { 754 uint32_t lut_type; 755 union { 756 struct mdp_igc_lut_data igc_lut_data; 757 struct mdp_pgc_lut_data pgc_lut_data; 758 struct mdp_hist_lut_data hist_lut_data; 759 struct mdp_rgb_lut_data rgb_lut_data; 760 } data; 761 }; 762 struct mdp_bl_scale_data { 763 uint32_t min_lvl; 764 uint32_t scale; 765 }; 766 struct mdp_pa_cfg_data { 767 uint32_t block; 768 struct mdp_pa_cfg pa_data; 769 }; 770 #define MDP_DITHER_DATA_V1_7_SZ 16 771 struct mdp_dither_data_v1_7 { 772 uint32_t g_y_depth; 773 uint32_t r_cr_depth; 774 uint32_t b_cb_depth; 775 uint32_t len; 776 uint32_t data[MDP_DITHER_DATA_V1_7_SZ]; 777 uint32_t temporal_en; 778 }; 779 struct mdp_dither_cfg_data { 780 uint32_t version; 781 uint32_t block; 782 uint32_t flags; 783 uint32_t mode; 784 uint32_t g_y_depth; 785 uint32_t r_cr_depth; 786 uint32_t b_cb_depth; 787 void * cfg_payload; 788 }; 789 #define MDP_GAMUT_TABLE_NUM 8 790 #define MDP_GAMUT_TABLE_NUM_V1_7 4 791 #define MDP_GAMUT_SCALE_OFF_TABLE_NUM 3 792 #define MDP_GAMUT_TABLE_V1_7_SZ 1229 793 #define MDP_GAMUT_SCALE_OFF_SZ 16 794 #define MDP_GAMUT_TABLE_V1_7_COARSE_SZ 32 795 struct mdp_gamut_cfg_data { 796 uint32_t block; 797 uint32_t flags; 798 uint32_t version; 799 uint32_t gamut_first; 800 uint32_t tbl_size[MDP_GAMUT_TABLE_NUM]; 801 uint16_t * r_tbl[MDP_GAMUT_TABLE_NUM]; 802 uint16_t * g_tbl[MDP_GAMUT_TABLE_NUM]; 803 uint16_t * b_tbl[MDP_GAMUT_TABLE_NUM]; 804 void * cfg_payload; 805 }; 806 enum { 807 mdp_gamut_fine_mode = 0x1, 808 mdp_gamut_coarse_mode, 809 }; 810 struct mdp_gamut_data_v1_7 { 811 uint32_t mode; 812 uint32_t map_en; 813 uint32_t tbl_size[MDP_GAMUT_TABLE_NUM_V1_7]; 814 uint32_t * c0_data[MDP_GAMUT_TABLE_NUM_V1_7]; 815 uint32_t * c1_c2_data[MDP_GAMUT_TABLE_NUM_V1_7]; 816 uint32_t tbl_scale_off_sz[MDP_GAMUT_SCALE_OFF_TABLE_NUM]; 817 uint32_t * scale_off_data[MDP_GAMUT_SCALE_OFF_TABLE_NUM]; 818 }; 819 struct mdp_calib_config_data { 820 uint32_t ops; 821 uint32_t addr; 822 uint32_t data; 823 }; 824 struct mdp_calib_config_buffer { 825 uint32_t ops; 826 uint32_t size; 827 uint32_t * buffer; 828 }; 829 struct mdp_calib_dcm_state { 830 uint32_t ops; 831 uint32_t dcm_state; 832 }; 833 enum { 834 DCM_UNINIT, 835 DCM_UNBLANK, 836 DCM_ENTER, 837 DCM_EXIT, 838 DCM_BLANK, 839 DTM_ENTER, 840 DTM_EXIT, 841 }; 842 #define MDSS_PP_SPLIT_LEFT_ONLY 0x10000000 843 #define MDSS_PP_SPLIT_RIGHT_ONLY 0x20000000 844 #define MDSS_PP_SPLIT_MASK 0x30000000 845 #define MDSS_MAX_BL_BRIGHTNESS 255 846 #define AD_BL_LIN_LEN 256 847 #define AD_BL_ATT_LUT_LEN 33 848 #define MDSS_AD_MODE_AUTO_BL 0x0 849 #define MDSS_AD_MODE_AUTO_STR 0x1 850 #define MDSS_AD_MODE_TARG_STR 0x3 851 #define MDSS_AD_MODE_MAN_STR 0x7 852 #define MDSS_AD_MODE_CALIB 0xF 853 #define MDP_PP_AD_INIT 0x10 854 #define MDP_PP_AD_CFG 0x20 855 struct mdss_ad_init { 856 uint32_t asym_lut[33]; 857 uint32_t color_corr_lut[33]; 858 uint8_t i_control[2]; 859 uint16_t black_lvl; 860 uint16_t white_lvl; 861 uint8_t var; 862 uint8_t limit_ampl; 863 uint8_t i_dither; 864 uint8_t slope_max; 865 uint8_t slope_min; 866 uint8_t dither_ctl; 867 uint8_t format; 868 uint8_t auto_size; 869 uint16_t frame_w; 870 uint16_t frame_h; 871 uint8_t logo_v; 872 uint8_t logo_h; 873 uint32_t alpha; 874 uint32_t alpha_base; 875 uint32_t al_thresh; 876 uint32_t bl_lin_len; 877 uint32_t bl_att_len; 878 uint32_t * bl_lin; 879 uint32_t * bl_lin_inv; 880 uint32_t * bl_att_lut; 881 }; 882 #define MDSS_AD_BL_CTRL_MODE_EN 1 883 #define MDSS_AD_BL_CTRL_MODE_DIS 0 884 struct mdss_ad_cfg { 885 uint32_t mode; 886 uint32_t al_calib_lut[33]; 887 uint16_t backlight_min; 888 uint16_t backlight_max; 889 uint16_t backlight_scale; 890 uint16_t amb_light_min; 891 uint16_t filter[2]; 892 uint16_t calib[4]; 893 uint8_t strength_limit; 894 uint8_t t_filter_recursion; 895 uint16_t stab_itr; 896 uint32_t bl_ctrl_mode; 897 }; 898 struct mdss_ad_init_cfg { 899 uint32_t ops; 900 union { 901 struct mdss_ad_init init; 902 struct mdss_ad_cfg cfg; 903 } params; 904 }; 905 struct mdss_ad_input { 906 uint32_t mode; 907 union { 908 uint32_t amb_light; 909 uint32_t strength; 910 uint32_t calib_bl; 911 } in; 912 uint32_t output; 913 }; 914 #define MDSS_CALIB_MODE_BL 0x1 915 struct mdss_calib_cfg { 916 uint32_t ops; 917 uint32_t calib_mask; 918 }; 919 enum { 920 mdp_op_pcc_cfg, 921 mdp_op_csc_cfg, 922 mdp_op_lut_cfg, 923 mdp_op_qseed_cfg, 924 mdp_bl_scale_cfg, 925 mdp_op_pa_cfg, 926 mdp_op_pa_v2_cfg, 927 mdp_op_dither_cfg, 928 mdp_op_gamut_cfg, 929 mdp_op_calib_cfg, 930 mdp_op_ad_cfg, 931 mdp_op_ad_input, 932 mdp_op_calib_mode, 933 mdp_op_calib_buffer, 934 mdp_op_calib_dcm_state, 935 mdp_op_max, 936 }; 937 enum { 938 WB_FORMAT_NV12, 939 WB_FORMAT_RGB_565, 940 WB_FORMAT_RGB_888, 941 WB_FORMAT_xRGB_8888, 942 WB_FORMAT_ARGB_8888, 943 WB_FORMAT_BGRA_8888, 944 WB_FORMAT_BGRX_8888, 945 WB_FORMAT_ARGB_8888_INPUT_ALPHA 946 }; 947 struct msmfb_mdp_pp { 948 uint32_t op; 949 union { 950 struct mdp_pcc_cfg_data pcc_cfg_data; 951 struct mdp_csc_cfg_data csc_cfg_data; 952 struct mdp_lut_cfg_data lut_cfg_data; 953 struct mdp_qseed_cfg_data qseed_cfg_data; 954 struct mdp_bl_scale_data bl_scale_data; 955 struct mdp_pa_cfg_data pa_cfg_data; 956 struct mdp_pa_v2_cfg_data pa_v2_cfg_data; 957 struct mdp_dither_cfg_data dither_cfg_data; 958 struct mdp_gamut_cfg_data gamut_cfg_data; 959 struct mdp_calib_config_data calib_cfg; 960 struct mdss_ad_init_cfg ad_init_cfg; 961 struct mdss_calib_cfg mdss_calib_cfg; 962 struct mdss_ad_input ad_input; 963 struct mdp_calib_config_buffer calib_buffer; 964 struct mdp_calib_dcm_state calib_dcm; 965 } data; 966 }; 967 #define FB_METADATA_VIDEO_INFO_CODE_SUPPORT 1 968 enum { 969 metadata_op_none, 970 metadata_op_base_blend, 971 metadata_op_frame_rate, 972 metadata_op_vic, 973 metadata_op_wb_format, 974 metadata_op_wb_secure, 975 metadata_op_get_caps, 976 metadata_op_crc, 977 metadata_op_get_ion_fd, 978 metadata_op_max 979 }; 980 struct mdp_blend_cfg { 981 uint32_t is_premultiplied; 982 }; 983 struct mdp_mixer_cfg { 984 uint32_t writeback_format; 985 uint32_t alpha; 986 }; 987 struct mdss_hw_caps { 988 uint32_t mdp_rev; 989 uint8_t rgb_pipes; 990 uint8_t vig_pipes; 991 uint8_t dma_pipes; 992 uint8_t max_smp_cnt; 993 uint8_t smp_per_pipe; 994 uint32_t features; 995 }; 996 struct msmfb_metadata { 997 uint32_t op; 998 uint32_t flags; 999 union { 1000 struct mdp_misr misr_request; 1001 struct mdp_blend_cfg blend_cfg; 1002 struct mdp_mixer_cfg mixer_cfg; 1003 uint32_t panel_frame_rate; 1004 uint32_t video_info_code; 1005 struct mdss_hw_caps caps; 1006 uint8_t secure_en; 1007 int fbmem_ionfd; 1008 } data; 1009 }; 1010 #define MDP_MAX_FENCE_FD 32 1011 #define MDP_BUF_SYNC_FLAG_WAIT 1 1012 #define MDP_BUF_SYNC_FLAG_RETIRE_FENCE 0x10 1013 struct mdp_buf_sync { 1014 uint32_t flags; 1015 uint32_t acq_fen_fd_cnt; 1016 uint32_t session_id; 1017 int * acq_fen_fd; 1018 int * rel_fen_fd; 1019 int * retire_fen_fd; 1020 }; 1021 struct mdp_async_blit_req_list { 1022 struct mdp_buf_sync sync; 1023 uint32_t count; 1024 struct mdp_blit_req req[]; 1025 }; 1026 #define MDP_DISPLAY_COMMIT_OVERLAY 1 1027 struct mdp_display_commit { 1028 uint32_t flags; 1029 uint32_t wait_for_finish; 1030 struct fb_var_screeninfo var; 1031 struct mdp_rect l_roi; 1032 struct mdp_rect r_roi; 1033 }; 1034 struct mdp_overlay_list { 1035 uint32_t num_overlays; 1036 struct mdp_overlay * * overlay_list; 1037 uint32_t flags; 1038 uint32_t processed_overlays; 1039 }; 1040 struct mdp_page_protection { 1041 uint32_t page_protection; 1042 }; 1043 struct mdp_mixer_info { 1044 int pndx; 1045 int pnum; 1046 int ptype; 1047 int mixer_num; 1048 int z_order; 1049 }; 1050 #define MAX_PIPE_PER_MIXER 7 1051 struct msmfb_mixer_info_req { 1052 int mixer_num; 1053 int cnt; 1054 struct mdp_mixer_info info[MAX_PIPE_PER_MIXER]; 1055 }; 1056 enum { 1057 DISPLAY_SUBSYSTEM_ID, 1058 ROTATOR_SUBSYSTEM_ID, 1059 }; 1060 enum { 1061 MDP_IOMMU_DOMAIN_CP, 1062 MDP_IOMMU_DOMAIN_NS, 1063 }; 1064 enum { 1065 MDP_WRITEBACK_MIRROR_OFF, 1066 MDP_WRITEBACK_MIRROR_ON, 1067 MDP_WRITEBACK_MIRROR_PAUSE, 1068 MDP_WRITEBACK_MIRROR_RESUME, 1069 }; 1070 enum mdp_color_space { 1071 MDP_CSC_ITU_R_601, 1072 MDP_CSC_ITU_R_601_FR, 1073 MDP_CSC_ITU_R_709, 1074 }; 1075 #define MDP_CSC_ITU_R_2020 (MDP_CSC_ITU_R_709 + 1) 1076 #define MDP_CSC_ITU_R_2020_FR (MDP_CSC_ITU_R_2020 + 1) 1077 enum { 1078 mdp_igc_v1_7 = 1, 1079 mdp_igc_vmax, 1080 mdp_hist_lut_v1_7, 1081 mdp_hist_lut_vmax, 1082 mdp_pgc_v1_7, 1083 mdp_pgc_vmax, 1084 mdp_dither_v1_7, 1085 mdp_dither_vmax, 1086 mdp_gamut_v1_7, 1087 mdp_gamut_vmax, 1088 mdp_pa_v1_7, 1089 mdp_pa_vmax, 1090 mdp_pcc_v1_7, 1091 mdp_pcc_vmax, 1092 mdp_pp_legacy, 1093 }; 1094 enum { 1095 IGC = 1, 1096 PCC, 1097 GC, 1098 PA, 1099 GAMUT, 1100 DITHER, 1101 QSEED, 1102 HIST_LUT, 1103 HIST, 1104 PP_FEATURE_MAX, 1105 }; 1106 struct mdp_pp_feature_version { 1107 uint32_t pp_feature; 1108 uint32_t version_info; 1109 }; 1110 #endif 1111 1112
