1 #ifndef _UAPI_MSM_MDP_H_ 2 #define _UAPI_MSM_MDP_H_ 3 4 #include <linux/types.h> 5 #include <linux/fb.h> 6 7 #define MSMFB_IOCTL_MAGIC 'm' 8 #define MSMFB_GRP_DISP _IOW(MSMFB_IOCTL_MAGIC, 1, unsigned int) 9 #define MSMFB_BLIT _IOW(MSMFB_IOCTL_MAGIC, 2, unsigned int) 10 #define MSMFB_SUSPEND_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 128, unsigned int) 11 #define MSMFB_RESUME_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 129, unsigned int) 12 #define MSMFB_CURSOR _IOW(MSMFB_IOCTL_MAGIC, 130, struct fb_cursor) 13 #define MSMFB_SET_LUT _IOW(MSMFB_IOCTL_MAGIC, 131, struct fb_cmap) 14 #define MSMFB_HISTOGRAM _IOWR(MSMFB_IOCTL_MAGIC, 132, struct mdp_histogram_data) 15 /* new ioctls's for set/get ccs matrix */ 16 #define MSMFB_GET_CCS_MATRIX _IOWR(MSMFB_IOCTL_MAGIC, 133, struct mdp_ccs) 17 #define MSMFB_SET_CCS_MATRIX _IOW(MSMFB_IOCTL_MAGIC, 134, struct mdp_ccs) 18 #define MSMFB_OVERLAY_SET _IOWR(MSMFB_IOCTL_MAGIC, 135, \ 19 struct mdp_overlay) 20 #define MSMFB_OVERLAY_UNSET _IOW(MSMFB_IOCTL_MAGIC, 136, unsigned int) 21 22 #define MSMFB_OVERLAY_PLAY _IOW(MSMFB_IOCTL_MAGIC, 137, \ 23 struct msmfb_overlay_data) 24 #define MSMFB_OVERLAY_QUEUE MSMFB_OVERLAY_PLAY 25 26 #define MSMFB_GET_PAGE_PROTECTION _IOR(MSMFB_IOCTL_MAGIC, 138, \ 27 struct mdp_page_protection) 28 #define MSMFB_SET_PAGE_PROTECTION _IOW(MSMFB_IOCTL_MAGIC, 139, \ 29 struct mdp_page_protection) 30 #define MSMFB_OVERLAY_GET _IOR(MSMFB_IOCTL_MAGIC, 140, \ 31 struct mdp_overlay) 32 #define MSMFB_OVERLAY_PLAY_ENABLE _IOW(MSMFB_IOCTL_MAGIC, 141, unsigned int) 33 #define MSMFB_OVERLAY_BLT _IOWR(MSMFB_IOCTL_MAGIC, 142, \ 34 struct msmfb_overlay_blt) 35 #define MSMFB_OVERLAY_BLT_OFFSET _IOW(MSMFB_IOCTL_MAGIC, 143, unsigned int) 36 #define MSMFB_HISTOGRAM_START _IOR(MSMFB_IOCTL_MAGIC, 144, \ 37 struct mdp_histogram_start_req) 38 #define MSMFB_HISTOGRAM_STOP _IOR(MSMFB_IOCTL_MAGIC, 145, unsigned int) 39 #define MSMFB_NOTIFY_UPDATE _IOWR(MSMFB_IOCTL_MAGIC, 146, unsigned int) 40 41 #define MSMFB_OVERLAY_3D _IOWR(MSMFB_IOCTL_MAGIC, 147, \ 42 struct msmfb_overlay_3d) 43 44 #define MSMFB_MIXER_INFO _IOWR(MSMFB_IOCTL_MAGIC, 148, \ 45 struct msmfb_mixer_info_req) 46 #define MSMFB_OVERLAY_PLAY_WAIT _IOWR(MSMFB_IOCTL_MAGIC, 149, \ 47 struct msmfb_overlay_data) 48 #define MSMFB_WRITEBACK_INIT _IO(MSMFB_IOCTL_MAGIC, 150) 49 #define MSMFB_WRITEBACK_START _IO(MSMFB_IOCTL_MAGIC, 151) 50 #define MSMFB_WRITEBACK_STOP _IO(MSMFB_IOCTL_MAGIC, 152) 51 #define MSMFB_WRITEBACK_QUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 153, \ 52 struct msmfb_data) 53 #define MSMFB_WRITEBACK_DEQUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 154, \ 54 struct msmfb_data) 55 #define MSMFB_WRITEBACK_TERMINATE _IO(MSMFB_IOCTL_MAGIC, 155) 56 #define MSMFB_MDP_PP _IOWR(MSMFB_IOCTL_MAGIC, 156, struct msmfb_mdp_pp) 57 #define MSMFB_OVERLAY_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 160, unsigned int) 58 #define MSMFB_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 161, unsigned int) 59 #define MSMFB_BUFFER_SYNC _IOW(MSMFB_IOCTL_MAGIC, 162, struct mdp_buf_sync) 60 #define MSMFB_OVERLAY_COMMIT _IO(MSMFB_IOCTL_MAGIC, 163) 61 #define MSMFB_DISPLAY_COMMIT _IOW(MSMFB_IOCTL_MAGIC, 164, \ 62 struct mdp_display_commit) 63 #define MSMFB_METADATA_SET _IOW(MSMFB_IOCTL_MAGIC, 165, struct msmfb_metadata) 64 #define MSMFB_METADATA_GET _IOW(MSMFB_IOCTL_MAGIC, 166, struct msmfb_metadata) 65 #define MSMFB_WRITEBACK_SET_MIRRORING_HINT _IOW(MSMFB_IOCTL_MAGIC, 167, \ 66 unsigned int) 67 #define MSMFB_ASYNC_BLIT _IOW(MSMFB_IOCTL_MAGIC, 168, unsigned int) 68 #define MSMFB_OVERLAY_PREPARE _IOWR(MSMFB_IOCTL_MAGIC, 169, \ 69 struct mdp_overlay_list) 70 #define MSMFB_LPM_ENABLE _IOWR(MSMFB_IOCTL_MAGIC, 170, unsigned int) 71 #define MSMFB_MDP_PP_GET_FEATURE_VERSION _IOWR(MSMFB_IOCTL_MAGIC, 171, \ 72 struct mdp_pp_feature_version) 73 74 #define FB_TYPE_3D_PANEL 0x10101010 75 #define MDP_IMGTYPE2_START 0x10000 76 #define MSMFB_DRIVER_VERSION 0xF9E8D701 77 /* Maximum number of formats supported by MDP*/ 78 #define MDP_IMGTYPE_END 0x100 79 80 /* HW Revisions for different MDSS targets */ 81 #define MDSS_GET_MAJOR(rev) ((rev) >> 28) 82 #define MDSS_GET_MINOR(rev) (((rev) >> 16) & 0xFFF) 83 #define MDSS_GET_STEP(rev) ((rev) & 0xFFFF) 84 #define MDSS_GET_MAJOR_MINOR(rev) ((rev) >> 16) 85 86 #define IS_MDSS_MAJOR_MINOR_SAME(rev1, rev2) \ 87 (MDSS_GET_MAJOR_MINOR((rev1)) == MDSS_GET_MAJOR_MINOR((rev2))) 88 89 #define MDSS_MDP_REV(major, minor, step) \ 90 ((((major) & 0x000F) << 28) | \ 91 (((minor) & 0x0FFF) << 16) | \ 92 ((step) & 0xFFFF)) 93 94 #define MDSS_MDP_HW_REV_100 MDSS_MDP_REV(1, 0, 0) /* 8974 v1.0 */ 95 #define MDSS_MDP_HW_REV_101 MDSS_MDP_REV(1, 1, 0) /* 8x26 v1.0 */ 96 #define MDSS_MDP_HW_REV_101_1 MDSS_MDP_REV(1, 1, 1) /* 8x26 v2.0, 8926 v1.0 */ 97 #define MDSS_MDP_HW_REV_101_2 MDSS_MDP_REV(1, 1, 2) /* 8926 v2.0 */ 98 #define MDSS_MDP_HW_REV_102 MDSS_MDP_REV(1, 2, 0) /* 8974 v2.0 */ 99 #define MDSS_MDP_HW_REV_102_1 MDSS_MDP_REV(1, 2, 1) /* 8974 v3.0 (Pro) */ 100 #define MDSS_MDP_HW_REV_103 MDSS_MDP_REV(1, 3, 0) /* 8084 v1.0 */ 101 #define MDSS_MDP_HW_REV_103_1 MDSS_MDP_REV(1, 3, 1) /* 8084 v1.1 */ 102 #define MDSS_MDP_HW_REV_105 MDSS_MDP_REV(1, 5, 0) /* 8994 v1.0 */ 103 #define MDSS_MDP_HW_REV_106 MDSS_MDP_REV(1, 6, 0) /* 8916 v1.0 */ 104 #define MDSS_MDP_HW_REV_107 MDSS_MDP_REV(1, 7, 0) /* 8996 v1 */ 105 #define MDSS_MDP_HW_REV_107_1 MDSS_MDP_REV(1, 7, 1) /* 8996 v2 */ 106 #define MDSS_MDP_HW_REV_107_2 MDSS_MDP_REV(1, 7, 2) /* 8996 v3 */ 107 #define MDSS_MDP_HW_REV_108 MDSS_MDP_REV(1, 8, 0) /* 8939 v1.0 */ 108 #define MDSS_MDP_HW_REV_109 MDSS_MDP_REV(1, 9, 0) /* 8994 v2.0 */ 109 #define MDSS_MDP_HW_REV_110 MDSS_MDP_REV(1, 10, 0) /* 8992 v1.0 */ 110 #define MDSS_MDP_HW_REV_200 MDSS_MDP_REV(2, 0, 0) /* 8092 v1.0 */ 111 #define MDSS_MDP_HW_REV_112 MDSS_MDP_REV(1, 12, 0) /* 8952 v1.0 */ 112 #define MDSS_MDP_HW_REV_114 MDSS_MDP_REV(1, 14, 0) /* 8937 v1.0 */ 113 #define MDSS_MDP_HW_REV_115 MDSS_MDP_REV(1, 15, 0) /* msm8917 */ 114 #define MDSS_MDP_HW_REV_116 MDSS_MDP_REV(1, 16, 0) /* msm8953 */ 115 #define MDSS_MDP_HW_REV_300 MDSS_MDP_REV(3, 0, 0) /* msmcobalt */ 116 #define MDSS_MDP_HW_REV_301 MDSS_MDP_REV(3, 0, 1) /* msmcobalt v1.0 */ 117 118 enum { 119 NOTIFY_UPDATE_INIT, 120 NOTIFY_UPDATE_DEINIT, 121 NOTIFY_UPDATE_START, 122 NOTIFY_UPDATE_STOP, 123 NOTIFY_UPDATE_POWER_OFF, 124 }; 125 126 enum { 127 NOTIFY_TYPE_NO_UPDATE, 128 NOTIFY_TYPE_SUSPEND, 129 NOTIFY_TYPE_UPDATE, 130 NOTIFY_TYPE_BL_UPDATE, 131 NOTIFY_TYPE_BL_AD_ATTEN_UPDATE, 132 }; 133 134 enum { 135 MDP_RGB_565, /* RGB 565 planer */ 136 MDP_XRGB_8888, /* RGB 888 padded */ 137 MDP_Y_CBCR_H2V2, /* Y and CbCr, pseudo planer w/ Cb is in MSB */ 138 MDP_Y_CBCR_H2V2_ADRENO, 139 MDP_ARGB_8888, /* ARGB 888 */ 140 MDP_RGB_888, /* RGB 888 planer */ 141 MDP_Y_CRCB_H2V2, /* Y and CrCb, pseudo planer w/ Cr is in MSB */ 142 MDP_YCRYCB_H2V1, /* YCrYCb interleave */ 143 MDP_CBYCRY_H2V1, /* CbYCrY interleave */ 144 MDP_Y_CRCB_H2V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */ 145 MDP_Y_CBCR_H2V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */ 146 MDP_Y_CRCB_H1V2, 147 MDP_Y_CBCR_H1V2, 148 MDP_RGBA_8888, /* ARGB 888 */ 149 MDP_BGRA_8888, /* ABGR 888 */ 150 MDP_RGBX_8888, /* RGBX 888 */ 151 MDP_Y_CRCB_H2V2_TILE, /* Y and CrCb, pseudo planer tile */ 152 MDP_Y_CBCR_H2V2_TILE, /* Y and CbCr, pseudo planer tile */ 153 MDP_Y_CR_CB_H2V2, /* Y, Cr and Cb, planar */ 154 MDP_Y_CR_CB_GH2V2, /* Y, Cr and Cb, planar aligned to Android YV12 */ 155 MDP_Y_CB_CR_H2V2, /* Y, Cb and Cr, planar */ 156 MDP_Y_CRCB_H1V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */ 157 MDP_Y_CBCR_H1V1, /* Y and CbCr, pseduo planer w/ Cb is in MSB */ 158 MDP_YCRCB_H1V1, /* YCrCb interleave */ 159 MDP_YCBCR_H1V1, /* YCbCr interleave */ 160 MDP_BGR_565, /* BGR 565 planer */ 161 MDP_BGR_888, /* BGR 888 */ 162 MDP_Y_CBCR_H2V2_VENUS, 163 MDP_BGRX_8888, /* BGRX 8888 */ 164 MDP_RGBA_8888_TILE, /* RGBA 8888 in tile format */ 165 MDP_ARGB_8888_TILE, /* ARGB 8888 in tile format */ 166 MDP_ABGR_8888_TILE, /* ABGR 8888 in tile format */ 167 MDP_BGRA_8888_TILE, /* BGRA 8888 in tile format */ 168 MDP_RGBX_8888_TILE, /* RGBX 8888 in tile format */ 169 MDP_XRGB_8888_TILE, /* XRGB 8888 in tile format */ 170 MDP_XBGR_8888_TILE, /* XBGR 8888 in tile format */ 171 MDP_BGRX_8888_TILE, /* BGRX 8888 in tile format */ 172 MDP_YCBYCR_H2V1, /* YCbYCr interleave */ 173 MDP_RGB_565_TILE, /* RGB 565 in tile format */ 174 MDP_BGR_565_TILE, /* BGR 565 in tile format */ 175 MDP_ARGB_1555, /*ARGB 1555*/ 176 MDP_RGBA_5551, /*RGBA 5551*/ 177 MDP_ARGB_4444, /*ARGB 4444*/ 178 MDP_RGBA_4444, /*RGBA 4444*/ 179 MDP_RGB_565_UBWC, 180 MDP_RGBA_8888_UBWC, 181 MDP_Y_CBCR_H2V2_UBWC, 182 MDP_RGBX_8888_UBWC, 183 MDP_Y_CRCB_H2V2_VENUS, 184 MDP_IMGTYPE_LIMIT, 185 MDP_RGB_BORDERFILL, /* border fill pipe */ 186 MDP_XRGB_1555, 187 MDP_RGBX_5551, 188 MDP_XRGB_4444, 189 MDP_RGBX_4444, 190 MDP_ABGR_1555, 191 MDP_BGRA_5551, 192 MDP_XBGR_1555, 193 MDP_BGRX_5551, 194 MDP_ABGR_4444, 195 MDP_BGRA_4444, 196 MDP_XBGR_4444, 197 MDP_BGRX_4444, 198 MDP_ABGR_8888, 199 MDP_XBGR_8888, 200 MDP_RGBA_1010102, 201 MDP_ARGB_2101010, 202 MDP_RGBX_1010102, 203 MDP_XRGB_2101010, 204 MDP_BGRA_1010102, 205 MDP_ABGR_2101010, 206 MDP_BGRX_1010102, 207 MDP_XBGR_2101010, 208 MDP_RGBA_1010102_UBWC, 209 MDP_RGBX_1010102_UBWC, 210 MDP_Y_CBCR_H2V2_P010, 211 MDP_Y_CBCR_H2V2_TP10_UBWC, 212 MDP_CRYCBY_H2V1, /* CrYCbY interleave */ 213 MDP_IMGTYPE_LIMIT1 = MDP_IMGTYPE_END, 214 MDP_FB_FORMAT = MDP_IMGTYPE2_START, /* framebuffer format */ 215 MDP_IMGTYPE_LIMIT2 /* Non valid image type after this enum */ 216 }; 217 218 #define MDP_CRYCBY_H2V1 MDP_CRYCBY_H2V1 219 220 enum { 221 PMEM_IMG, 222 FB_IMG, 223 }; 224 225 enum { 226 HSIC_HUE = 0, 227 HSIC_SAT, 228 HSIC_INT, 229 HSIC_CON, 230 NUM_HSIC_PARAM, 231 }; 232 233 enum mdss_mdp_max_bw_mode { 234 MDSS_MAX_BW_LIMIT_DEFAULT = 0x1, 235 MDSS_MAX_BW_LIMIT_CAMERA = 0x2, 236 MDSS_MAX_BW_LIMIT_HFLIP = 0x4, 237 MDSS_MAX_BW_LIMIT_VFLIP = 0x8, 238 }; 239 240 #define MDSS_MDP_ROT_ONLY 0x80 241 #define MDSS_MDP_RIGHT_MIXER 0x100 242 #define MDSS_MDP_DUAL_PIPE 0x200 243 244 /* mdp_blit_req flag values */ 245 #define MDP_ROT_NOP 0 246 #define MDP_FLIP_LR 0x1 247 #define MDP_FLIP_UD 0x2 248 #define MDP_ROT_90 0x4 249 #define MDP_ROT_180 (MDP_FLIP_UD|MDP_FLIP_LR) 250 #define MDP_ROT_270 (MDP_ROT_90|MDP_FLIP_UD|MDP_FLIP_LR) 251 #define MDP_DITHER 0x8 252 #define MDP_BLUR 0x10 253 #define MDP_BLEND_FG_PREMULT 0x20000 254 #define MDP_IS_FG 0x40000 255 #define MDP_SOLID_FILL 0x00000020 256 #define MDP_VPU_PIPE 0x00000040 257 #define MDP_DEINTERLACE 0x80000000 258 #define MDP_SHARPENING 0x40000000 259 #define MDP_NO_DMA_BARRIER_START 0x20000000 260 #define MDP_NO_DMA_BARRIER_END 0x10000000 261 #define MDP_NO_BLIT 0x08000000 262 #define MDP_BLIT_WITH_DMA_BARRIERS 0x000 263 #define MDP_BLIT_WITH_NO_DMA_BARRIERS \ 264 (MDP_NO_DMA_BARRIER_START | MDP_NO_DMA_BARRIER_END) 265 #define MDP_BLIT_SRC_GEM 0x04000000 266 #define MDP_BLIT_DST_GEM 0x02000000 267 #define MDP_BLIT_NON_CACHED 0x01000000 268 #define MDP_OV_PIPE_SHARE 0x00800000 269 #define MDP_DEINTERLACE_ODD 0x00400000 270 #define MDP_OV_PLAY_NOWAIT 0x00200000 271 #define MDP_SOURCE_ROTATED_90 0x00100000 272 #define MDP_OVERLAY_PP_CFG_EN 0x00080000 273 #define MDP_BACKEND_COMPOSITION 0x00040000 274 #define MDP_BORDERFILL_SUPPORTED 0x00010000 275 #define MDP_SECURE_OVERLAY_SESSION 0x00008000 276 #define MDP_SECURE_DISPLAY_OVERLAY_SESSION 0x00002000 277 #define MDP_OV_PIPE_FORCE_DMA 0x00004000 278 #define MDP_MEMORY_ID_TYPE_FB 0x00001000 279 #define MDP_BWC_EN 0x00000400 280 #define MDP_DECIMATION_EN 0x00000800 281 #define MDP_SMP_FORCE_ALLOC 0x00200000 282 #define MDP_TRANSP_NOP 0xffffffff 283 #define MDP_ALPHA_NOP 0xff 284 285 #define MDP_FB_PAGE_PROTECTION_NONCACHED (0) 286 #define MDP_FB_PAGE_PROTECTION_WRITECOMBINE (1) 287 #define MDP_FB_PAGE_PROTECTION_WRITETHROUGHCACHE (2) 288 #define MDP_FB_PAGE_PROTECTION_WRITEBACKCACHE (3) 289 #define MDP_FB_PAGE_PROTECTION_WRITEBACKWACACHE (4) 290 /* Sentinel: Don't use! */ 291 #define MDP_FB_PAGE_PROTECTION_INVALID (5) 292 /* Count of the number of MDP_FB_PAGE_PROTECTION_... values. */ 293 #define MDP_NUM_FB_PAGE_PROTECTION_VALUES (5) 294 295 struct mdp_rect { 296 uint32_t x; 297 uint32_t y; 298 uint32_t w; 299 uint32_t h; 300 }; 301 302 struct mdp_img { 303 uint32_t width; 304 uint32_t height; 305 uint32_t format; 306 uint32_t offset; 307 int memory_id; /* the file descriptor */ 308 uint32_t priv; 309 }; 310 311 struct mult_factor { 312 uint32_t numer; 313 uint32_t denom; 314 }; 315 316 /* 317 * {3x3} + {3} ccs matrix 318 */ 319 320 #define MDP_CCS_RGB2YUV 0 321 #define MDP_CCS_YUV2RGB 1 322 323 #define MDP_CCS_SIZE 9 324 #define MDP_BV_SIZE 3 325 326 struct mdp_ccs { 327 int direction; /* MDP_CCS_RGB2YUV or YUV2RGB */ 328 uint16_t ccs[MDP_CCS_SIZE]; /* 3x3 color coefficients */ 329 uint16_t bv[MDP_BV_SIZE]; /* 1x3 bias vector */ 330 }; 331 332 struct mdp_csc { 333 int id; 334 uint32_t csc_mv[9]; 335 uint32_t csc_pre_bv[3]; 336 uint32_t csc_post_bv[3]; 337 uint32_t csc_pre_lv[6]; 338 uint32_t csc_post_lv[6]; 339 }; 340 341 /* The version of the mdp_blit_req structure so that 342 * user applications can selectively decide which functionality 343 * to include 344 */ 345 346 #define MDP_BLIT_REQ_VERSION 3 347 348 struct color { 349 uint32_t r; 350 uint32_t g; 351 uint32_t b; 352 uint32_t alpha; 353 }; 354 355 struct mdp_blit_req { 356 struct mdp_img src; 357 struct mdp_img dst; 358 struct mdp_rect src_rect; 359 struct mdp_rect dst_rect; 360 struct color const_color; 361 uint32_t alpha; 362 uint32_t transp_mask; 363 uint32_t flags; 364 int sharpening_strength; /* -127 <--> 127, default 64 */ 365 uint8_t color_space; 366 uint32_t fps; 367 }; 368 369 struct mdp_blit_req_list { 370 uint32_t count; 371 struct mdp_blit_req req[]; 372 }; 373 374 #define MSMFB_DATA_VERSION 2 375 376 struct msmfb_data { 377 uint32_t offset; 378 int memory_id; 379 int id; 380 uint32_t flags; 381 uint32_t priv; 382 uint32_t iova; 383 }; 384 385 #define MSMFB_NEW_REQUEST -1 386 387 struct msmfb_overlay_data { 388 uint32_t id; 389 struct msmfb_data data; 390 uint32_t version_key; 391 struct msmfb_data plane1_data; 392 struct msmfb_data plane2_data; 393 struct msmfb_data dst_data; 394 }; 395 396 struct msmfb_img { 397 uint32_t width; 398 uint32_t height; 399 uint32_t format; 400 }; 401 402 #define MSMFB_WRITEBACK_DEQUEUE_BLOCKING 0x1 403 struct msmfb_writeback_data { 404 struct msmfb_data buf_info; 405 struct msmfb_img img; 406 }; 407 408 #define MDP_PP_OPS_ENABLE 0x1 409 #define MDP_PP_OPS_READ 0x2 410 #define MDP_PP_OPS_WRITE 0x4 411 #define MDP_PP_OPS_DISABLE 0x8 412 #define MDP_PP_IGC_FLAG_ROM0 0x10 413 #define MDP_PP_IGC_FLAG_ROM1 0x20 414 415 416 #define MDSS_PP_DSPP_CFG 0x000 417 #define MDSS_PP_SSPP_CFG 0x100 418 #define MDSS_PP_LM_CFG 0x200 419 #define MDSS_PP_WB_CFG 0x300 420 421 #define MDSS_PP_ARG_MASK 0x3C00 422 #define MDSS_PP_ARG_NUM 4 423 #define MDSS_PP_ARG_SHIFT 10 424 #define MDSS_PP_LOCATION_MASK 0x0300 425 #define MDSS_PP_LOGICAL_MASK 0x00FF 426 427 #define MDSS_PP_ADD_ARG(var, arg) ((var) | (0x1 << (MDSS_PP_ARG_SHIFT + (arg)))) 428 #define PP_ARG(x, var) ((var) & (0x1 << (MDSS_PP_ARG_SHIFT + (x)))) 429 #define PP_LOCAT(var) ((var) & MDSS_PP_LOCATION_MASK) 430 #define PP_BLOCK(var) ((var) & MDSS_PP_LOGICAL_MASK) 431 432 433 struct mdp_qseed_cfg { 434 uint32_t table_num; 435 uint32_t ops; 436 uint32_t len; 437 uint32_t *data; 438 }; 439 440 struct mdp_sharp_cfg { 441 uint32_t flags; 442 uint32_t strength; 443 uint32_t edge_thr; 444 uint32_t smooth_thr; 445 uint32_t noise_thr; 446 }; 447 448 struct mdp_qseed_cfg_data { 449 uint32_t block; 450 struct mdp_qseed_cfg qseed_data; 451 }; 452 453 #define MDP_OVERLAY_PP_CSC_CFG 0x1 454 #define MDP_OVERLAY_PP_QSEED_CFG 0x2 455 #define MDP_OVERLAY_PP_PA_CFG 0x4 456 #define MDP_OVERLAY_PP_IGC_CFG 0x8 457 #define MDP_OVERLAY_PP_SHARP_CFG 0x10 458 #define MDP_OVERLAY_PP_HIST_CFG 0x20 459 #define MDP_OVERLAY_PP_HIST_LUT_CFG 0x40 460 #define MDP_OVERLAY_PP_PA_V2_CFG 0x80 461 #define MDP_OVERLAY_PP_PCC_CFG 0x100 462 463 #define MDP_CSC_FLAG_ENABLE 0x1 464 #define MDP_CSC_FLAG_YUV_IN 0x2 465 #define MDP_CSC_FLAG_YUV_OUT 0x4 466 467 #define MDP_CSC_MATRIX_COEFF_SIZE 9 468 #define MDP_CSC_CLAMP_SIZE 6 469 #define MDP_CSC_BIAS_SIZE 3 470 471 struct mdp_csc_cfg { 472 /* flags for enable CSC, toggling RGB,YUV input/output */ 473 uint32_t flags; 474 uint32_t csc_mv[MDP_CSC_MATRIX_COEFF_SIZE]; 475 uint32_t csc_pre_bv[MDP_CSC_BIAS_SIZE]; 476 uint32_t csc_post_bv[MDP_CSC_BIAS_SIZE]; 477 uint32_t csc_pre_lv[MDP_CSC_CLAMP_SIZE]; 478 uint32_t csc_post_lv[MDP_CSC_CLAMP_SIZE]; 479 }; 480 481 struct mdp_csc_cfg_data { 482 uint32_t block; 483 struct mdp_csc_cfg csc_data; 484 }; 485 486 struct mdp_pa_cfg { 487 uint32_t flags; 488 uint32_t hue_adj; 489 uint32_t sat_adj; 490 uint32_t val_adj; 491 uint32_t cont_adj; 492 }; 493 494 struct mdp_pa_mem_col_cfg { 495 uint32_t color_adjust_p0; 496 uint32_t color_adjust_p1; 497 uint32_t hue_region; 498 uint32_t sat_region; 499 uint32_t val_region; 500 }; 501 502 #define MDP_SIX_ZONE_LUT_SIZE 384 503 504 /* PA Write/Read extension flags */ 505 #define MDP_PP_PA_HUE_ENABLE 0x10 506 #define MDP_PP_PA_SAT_ENABLE 0x20 507 #define MDP_PP_PA_VAL_ENABLE 0x40 508 #define MDP_PP_PA_CONT_ENABLE 0x80 509 #define MDP_PP_PA_SIX_ZONE_ENABLE 0x100 510 #define MDP_PP_PA_SKIN_ENABLE 0x200 511 #define MDP_PP_PA_SKY_ENABLE 0x400 512 #define MDP_PP_PA_FOL_ENABLE 0x800 513 514 /* PA masks */ 515 /* Masks used in PA v1_7 only */ 516 #define MDP_PP_PA_MEM_PROT_HUE_EN 0x1 517 #define MDP_PP_PA_MEM_PROT_SAT_EN 0x2 518 #define MDP_PP_PA_MEM_PROT_VAL_EN 0x4 519 #define MDP_PP_PA_MEM_PROT_CONT_EN 0x8 520 #define MDP_PP_PA_MEM_PROT_SIX_EN 0x10 521 #define MDP_PP_PA_MEM_PROT_BLEND_EN 0x20 522 /* Masks used in all PAv2 versions */ 523 #define MDP_PP_PA_HUE_MASK 0x1000 524 #define MDP_PP_PA_SAT_MASK 0x2000 525 #define MDP_PP_PA_VAL_MASK 0x4000 526 #define MDP_PP_PA_CONT_MASK 0x8000 527 #define MDP_PP_PA_SIX_ZONE_HUE_MASK 0x10000 528 #define MDP_PP_PA_SIX_ZONE_SAT_MASK 0x20000 529 #define MDP_PP_PA_SIX_ZONE_VAL_MASK 0x40000 530 #define MDP_PP_PA_MEM_COL_SKIN_MASK 0x80000 531 #define MDP_PP_PA_MEM_COL_SKY_MASK 0x100000 532 #define MDP_PP_PA_MEM_COL_FOL_MASK 0x200000 533 #define MDP_PP_PA_MEM_PROTECT_EN 0x400000 534 #define MDP_PP_PA_SAT_ZERO_EXP_EN 0x800000 535 536 /* Flags for setting PA saturation and value hold */ 537 #define MDP_PP_PA_LEFT_HOLD 0x1 538 #define MDP_PP_PA_RIGHT_HOLD 0x2 539 540 struct mdp_pa_v2_data { 541 /* Mask bits for PA features */ 542 uint32_t flags; 543 uint32_t global_hue_adj; 544 uint32_t global_sat_adj; 545 uint32_t global_val_adj; 546 uint32_t global_cont_adj; 547 struct mdp_pa_mem_col_cfg skin_cfg; 548 struct mdp_pa_mem_col_cfg sky_cfg; 549 struct mdp_pa_mem_col_cfg fol_cfg; 550 uint32_t six_zone_len; 551 uint32_t six_zone_thresh; 552 uint32_t *six_zone_curve_p0; 553 uint32_t *six_zone_curve_p1; 554 }; 555 556 struct mdp_pa_mem_col_data_v1_7 { 557 uint32_t color_adjust_p0; 558 uint32_t color_adjust_p1; 559 uint32_t color_adjust_p2; 560 uint32_t blend_gain; 561 uint8_t sat_hold; 562 uint8_t val_hold; 563 uint32_t hue_region; 564 uint32_t sat_region; 565 uint32_t val_region; 566 }; 567 568 struct mdp_pa_data_v1_7 { 569 uint32_t mode; 570 uint32_t global_hue_adj; 571 uint32_t global_sat_adj; 572 uint32_t global_val_adj; 573 uint32_t global_cont_adj; 574 struct mdp_pa_mem_col_data_v1_7 skin_cfg; 575 struct mdp_pa_mem_col_data_v1_7 sky_cfg; 576 struct mdp_pa_mem_col_data_v1_7 fol_cfg; 577 uint32_t six_zone_thresh; 578 uint32_t six_zone_adj_p0; 579 uint32_t six_zone_adj_p1; 580 uint8_t six_zone_sat_hold; 581 uint8_t six_zone_val_hold; 582 uint32_t six_zone_len; 583 uint32_t *six_zone_curve_p0; 584 uint32_t *six_zone_curve_p1; 585 }; 586 587 588 struct mdp_pa_v2_cfg_data { 589 uint32_t version; 590 uint32_t block; 591 uint32_t flags; 592 struct mdp_pa_v2_data pa_v2_data; 593 void *cfg_payload; 594 }; 595 596 597 enum { 598 mdp_igc_rec601 = 1, 599 mdp_igc_rec709, 600 mdp_igc_srgb, 601 mdp_igc_custom, 602 mdp_igc_rec_max, 603 }; 604 605 struct mdp_igc_lut_data { 606 uint32_t block; 607 uint32_t version; 608 uint32_t len, ops; 609 uint32_t *c0_c1_data; 610 uint32_t *c2_data; 611 void *cfg_payload; 612 }; 613 614 struct mdp_igc_lut_data_v1_7 { 615 uint32_t table_fmt; 616 uint32_t len; 617 uint32_t *c0_c1_data; 618 uint32_t *c2_data; 619 }; 620 621 struct mdp_histogram_cfg { 622 uint32_t ops; 623 uint32_t block; 624 uint8_t frame_cnt; 625 uint8_t bit_mask; 626 uint16_t num_bins; 627 }; 628 629 struct mdp_hist_lut_data_v1_7 { 630 uint32_t len; 631 uint32_t *data; 632 }; 633 634 struct mdp_hist_lut_data { 635 uint32_t block; 636 uint32_t version; 637 uint32_t hist_lut_first; 638 uint32_t ops; 639 uint32_t len; 640 uint32_t *data; 641 void *cfg_payload; 642 }; 643 644 struct mdp_pcc_coeff { 645 uint32_t c, r, g, b, rr, gg, bb, rg, gb, rb, rgb_0, rgb_1; 646 }; 647 648 struct mdp_pcc_coeff_v1_7 { 649 uint32_t c, r, g, b, rg, gb, rb, rgb; 650 }; 651 652 struct mdp_pcc_data_v1_7 { 653 struct mdp_pcc_coeff_v1_7 r, g, b; 654 }; 655 656 struct mdp_pcc_cfg_data { 657 uint32_t version; 658 uint32_t block; 659 uint32_t ops; 660 struct mdp_pcc_coeff r, g, b; 661 void *cfg_payload; 662 }; 663 664 enum { 665 mdp_lut_igc, 666 mdp_lut_pgc, 667 mdp_lut_hist, 668 mdp_lut_rgb, 669 mdp_lut_max, 670 }; 671 struct mdp_overlay_pp_params { 672 uint32_t config_ops; 673 struct mdp_csc_cfg csc_cfg; 674 struct mdp_qseed_cfg qseed_cfg[2]; 675 struct mdp_pa_cfg pa_cfg; 676 struct mdp_pa_v2_data pa_v2_cfg; 677 struct mdp_igc_lut_data igc_cfg; 678 struct mdp_sharp_cfg sharp_cfg; 679 struct mdp_histogram_cfg hist_cfg; 680 struct mdp_hist_lut_data hist_lut_cfg; 681 /* PAv2 cfg data for PA 2.x versions */ 682 struct mdp_pa_v2_cfg_data pa_v2_cfg_data; 683 struct mdp_pcc_cfg_data pcc_cfg_data; 684 }; 685 686 /** 687 * enum mdss_mdp_blend_op - Different blend operations set by userspace 688 * 689 * @BLEND_OP_NOT_DEFINED: No blend operation defined for the layer. 690 * @BLEND_OP_OPAQUE: Apply a constant blend operation. The layer 691 * would appear opaque in case fg plane alpha is 692 * 0xff. 693 * @BLEND_OP_PREMULTIPLIED: Apply source over blend rule. Layer already has 694 * alpha pre-multiplication done. If fg plane alpha 695 * is less than 0xff, apply modulation as well. This 696 * operation is intended on layers having alpha 697 * channel. 698 * @BLEND_OP_COVERAGE: Apply source over blend rule. Layer is not alpha 699 * pre-multiplied. Apply pre-multiplication. If fg 700 * plane alpha is less than 0xff, apply modulation as 701 * well. 702 * @BLEND_OP_MAX: Used to track maximum blend operation possible by 703 * mdp. 704 */ 705 enum mdss_mdp_blend_op { 706 BLEND_OP_NOT_DEFINED = 0, 707 BLEND_OP_OPAQUE, 708 BLEND_OP_PREMULTIPLIED, 709 BLEND_OP_COVERAGE, 710 BLEND_OP_MAX, 711 }; 712 713 #define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci)) 714 #define MAX_PLANES 4 715 struct mdp_scale_data { 716 uint8_t enable_pxl_ext; 717 718 int init_phase_x[MAX_PLANES]; 719 int phase_step_x[MAX_PLANES]; 720 int init_phase_y[MAX_PLANES]; 721 int phase_step_y[MAX_PLANES]; 722 723 int num_ext_pxls_left[MAX_PLANES]; 724 int num_ext_pxls_right[MAX_PLANES]; 725 int num_ext_pxls_top[MAX_PLANES]; 726 int num_ext_pxls_btm[MAX_PLANES]; 727 728 int left_ftch[MAX_PLANES]; 729 int left_rpt[MAX_PLANES]; 730 int right_ftch[MAX_PLANES]; 731 int right_rpt[MAX_PLANES]; 732 733 int top_rpt[MAX_PLANES]; 734 int btm_rpt[MAX_PLANES]; 735 int top_ftch[MAX_PLANES]; 736 int btm_ftch[MAX_PLANES]; 737 738 uint32_t roi_w[MAX_PLANES]; 739 }; 740 741 /** 742 * enum mdp_overlay_pipe_type - Different pipe type set by userspace 743 * 744 * @PIPE_TYPE_AUTO: Not specified, pipe will be selected according to flags. 745 * @PIPE_TYPE_VIG: VIG pipe. 746 * @PIPE_TYPE_RGB: RGB pipe. 747 * @PIPE_TYPE_DMA: DMA pipe. 748 * @PIPE_TYPE_CURSOR: CURSOR pipe. 749 * @PIPE_TYPE_MAX: Used to track maximum number of pipe type. 750 */ 751 enum mdp_overlay_pipe_type { 752 PIPE_TYPE_AUTO = 0, 753 PIPE_TYPE_VIG, 754 PIPE_TYPE_RGB, 755 PIPE_TYPE_DMA, 756 PIPE_TYPE_CURSOR, 757 PIPE_TYPE_MAX, 758 }; 759 760 /** 761 * struct mdp_overlay - overlay surface structure 762 * @src: Source image information (width, height, format). 763 * @src_rect: Source crop rectangle, portion of image that will be fetched. 764 * This should always be within boundaries of source image. 765 * @dst_rect: Destination rectangle, the position and size of image on screen. 766 * This should always be within panel boundaries. 767 * @z_order: Blending stage to occupy in display, if multiple layers are 768 * present, highest z_order usually means the top most visible 769 * layer. The range acceptable is from 0-3 to support blending 770 * up to 4 layers. 771 * @is_fg: This flag is used to disable blending of any layers with z_order 772 * less than this overlay. It means that any layers with z_order 773 * less than this layer will not be blended and will be replaced 774 * by the background border color. 775 * @alpha: Used to set plane opacity. The range can be from 0-255, where 776 * 0 means completely transparent and 255 means fully opaque. 777 * @transp_mask: Color used as color key for transparency. Any pixel in fetched 778 * image matching this color will be transparent when blending. 779 * The color should be in same format as the source image format. 780 * @flags: This is used to customize operation of overlay. See MDP flags 781 * for more information. 782 * @pipe_type: Used to specify the type of overlay pipe. 783 * @user_data: DEPRECATED* Used to store user application specific information. 784 * @bg_color: Solid color used to fill the overlay surface when no source 785 * buffer is provided. 786 * @horz_deci: Horizontal decimation value, this indicates the amount of pixels 787 * dropped for each pixel that is fetched from a line. The value 788 * given should be power of two of decimation amount. 789 * 0: no decimation 790 * 1: decimate by 2 (drop 1 pixel for each pixel fetched) 791 * 2: decimate by 4 (drop 3 pixels for each pixel fetched) 792 * 3: decimate by 8 (drop 7 pixels for each pixel fetched) 793 * 4: decimate by 16 (drop 15 pixels for each pixel fetched) 794 * @vert_deci: Vertical decimation value, this indicates the amount of lines 795 * dropped for each line that is fetched from overlay. The value 796 * given should be power of two of decimation amount. 797 * 0: no decimation 798 * 1: decimation by 2 (drop 1 line for each line fetched) 799 * 2: decimation by 4 (drop 3 lines for each line fetched) 800 * 3: decimation by 8 (drop 7 lines for each line fetched) 801 * 4: decimation by 16 (drop 15 lines for each line fetched) 802 * @overlay_pp_cfg: Overlay post processing configuration, for more information 803 * see struct mdp_overlay_pp_params. 804 * @priority: Priority is returned by the driver when overlay is set for the 805 * first time. It indicates the priority of the underlying pipe 806 * serving the overlay. This priority can be used by user-space 807 * in source split when pipes are re-used and shuffled around to 808 * reduce fallbacks. 809 */ 810 struct mdp_overlay { 811 struct msmfb_img src; 812 struct mdp_rect src_rect; 813 struct mdp_rect dst_rect; 814 uint32_t z_order; /* stage number */ 815 uint32_t is_fg; /* control alpha & transp */ 816 uint32_t alpha; 817 uint32_t blend_op; 818 uint32_t transp_mask; 819 uint32_t flags; 820 uint32_t pipe_type; 821 uint32_t id; 822 uint8_t priority; 823 uint32_t user_data[6]; 824 uint32_t bg_color; 825 uint8_t horz_deci; 826 uint8_t vert_deci; 827 struct mdp_overlay_pp_params overlay_pp_cfg; 828 struct mdp_scale_data scale; 829 uint8_t color_space; 830 uint32_t frame_rate; 831 }; 832 833 struct msmfb_overlay_3d { 834 uint32_t is_3d; 835 uint32_t width; 836 uint32_t height; 837 }; 838 839 840 struct msmfb_overlay_blt { 841 uint32_t enable; 842 uint32_t offset; 843 uint32_t width; 844 uint32_t height; 845 uint32_t bpp; 846 }; 847 848 struct mdp_histogram { 849 uint32_t frame_cnt; 850 uint32_t bin_cnt; 851 uint32_t *r; 852 uint32_t *g; 853 uint32_t *b; 854 }; 855 856 #define MISR_CRC_BATCH_SIZE 32 857 enum { 858 DISPLAY_MISR_EDP, 859 DISPLAY_MISR_DSI0, 860 DISPLAY_MISR_DSI1, 861 DISPLAY_MISR_HDMI, 862 DISPLAY_MISR_LCDC, 863 DISPLAY_MISR_MDP, 864 DISPLAY_MISR_ATV, 865 DISPLAY_MISR_DSI_CMD, 866 DISPLAY_MISR_MAX 867 }; 868 869 enum { 870 MISR_OP_NONE, 871 MISR_OP_SFM, 872 MISR_OP_MFM, 873 MISR_OP_BM, 874 MISR_OP_MAX 875 }; 876 877 struct mdp_misr { 878 uint32_t block_id; 879 uint32_t frame_count; 880 uint32_t crc_op_mode; 881 uint32_t crc_value[MISR_CRC_BATCH_SIZE]; 882 }; 883 884 /* 885 886 mdp_block_type defines the identifiers for pipes in MDP 4.3 and up 887 888 MDP_BLOCK_RESERVED is provided for backward compatibility and is 889 deprecated. It corresponds to DMA_P. So MDP_BLOCK_DMA_P should be used 890 instead. 891 892 MDP_LOGICAL_BLOCK_DISP_0 identifies the display pipe which fb0 uses, 893 same for others. 894 895 */ 896 897 enum { 898 MDP_BLOCK_RESERVED = 0, 899 MDP_BLOCK_OVERLAY_0, 900 MDP_BLOCK_OVERLAY_1, 901 MDP_BLOCK_VG_1, 902 MDP_BLOCK_VG_2, 903 MDP_BLOCK_RGB_1, 904 MDP_BLOCK_RGB_2, 905 MDP_BLOCK_DMA_P, 906 MDP_BLOCK_DMA_S, 907 MDP_BLOCK_DMA_E, 908 MDP_BLOCK_OVERLAY_2, 909 MDP_LOGICAL_BLOCK_DISP_0 = 0x10, 910 MDP_LOGICAL_BLOCK_DISP_1, 911 MDP_LOGICAL_BLOCK_DISP_2, 912 MDP_BLOCK_MAX, 913 }; 914 915 /* 916 * mdp_histogram_start_req is used to provide the parameters for 917 * histogram start request 918 */ 919 920 struct mdp_histogram_start_req { 921 uint32_t block; 922 uint8_t frame_cnt; 923 uint8_t bit_mask; 924 uint16_t num_bins; 925 }; 926 927 /* 928 * mdp_histogram_data is used to return the histogram data, once 929 * the histogram is done/stopped/cance 930 */ 931 932 struct mdp_histogram_data { 933 uint32_t block; 934 uint32_t bin_cnt; 935 uint32_t *c0; 936 uint32_t *c1; 937 uint32_t *c2; 938 uint32_t *extra_info; 939 }; 940 941 942 #define GC_LUT_ENTRIES_V1_7 512 943 944 struct mdp_ar_gc_lut_data { 945 uint32_t x_start; 946 uint32_t slope; 947 uint32_t offset; 948 }; 949 950 #define MDP_PP_PGC_ROUNDING_ENABLE 0x10 951 struct mdp_pgc_lut_data { 952 uint32_t version; 953 uint32_t block; 954 uint32_t flags; 955 uint8_t num_r_stages; 956 uint8_t num_g_stages; 957 uint8_t num_b_stages; 958 struct mdp_ar_gc_lut_data *r_data; 959 struct mdp_ar_gc_lut_data *g_data; 960 struct mdp_ar_gc_lut_data *b_data; 961 void *cfg_payload; 962 }; 963 964 #define PGC_LUT_ENTRIES 1024 965 struct mdp_pgc_lut_data_v1_7 { 966 uint32_t len; 967 uint32_t *c0_data; 968 uint32_t *c1_data; 969 uint32_t *c2_data; 970 }; 971 972 /* 973 * mdp_rgb_lut_data is used to provide parameters for configuring the 974 * generic RGB lut in case of gamma correction or other LUT updation usecases 975 */ 976 struct mdp_rgb_lut_data { 977 uint32_t flags; 978 uint32_t lut_type; 979 struct fb_cmap cmap; 980 }; 981 982 enum { 983 mdp_rgb_lut_gc, 984 mdp_rgb_lut_hist, 985 }; 986 987 struct mdp_lut_cfg_data { 988 uint32_t lut_type; 989 union { 990 struct mdp_igc_lut_data igc_lut_data; 991 struct mdp_pgc_lut_data pgc_lut_data; 992 struct mdp_hist_lut_data hist_lut_data; 993 struct mdp_rgb_lut_data rgb_lut_data; 994 } data; 995 }; 996 997 struct mdp_bl_scale_data { 998 uint32_t min_lvl; 999 uint32_t scale; 1000 }; 1001 1002 struct mdp_pa_cfg_data { 1003 uint32_t block; 1004 struct mdp_pa_cfg pa_data; 1005 }; 1006 1007 #define MDP_DITHER_DATA_V1_7_SZ 16 1008 1009 struct mdp_dither_data_v1_7 { 1010 uint32_t g_y_depth; 1011 uint32_t r_cr_depth; 1012 uint32_t b_cb_depth; 1013 uint32_t len; 1014 uint32_t data[MDP_DITHER_DATA_V1_7_SZ]; 1015 uint32_t temporal_en; 1016 }; 1017 1018 struct mdp_dither_cfg_data { 1019 uint32_t version; 1020 uint32_t block; 1021 uint32_t flags; 1022 uint32_t mode; 1023 uint32_t g_y_depth; 1024 uint32_t r_cr_depth; 1025 uint32_t b_cb_depth; 1026 void *cfg_payload; 1027 }; 1028 1029 #define MDP_GAMUT_TABLE_NUM 8 1030 #define MDP_GAMUT_TABLE_NUM_V1_7 4 1031 #define MDP_GAMUT_SCALE_OFF_TABLE_NUM 3 1032 #define MDP_GAMUT_TABLE_V1_7_SZ 1229 1033 #define MDP_GAMUT_SCALE_OFF_SZ 16 1034 #define MDP_GAMUT_TABLE_V1_7_COARSE_SZ 32 1035 1036 struct mdp_gamut_cfg_data { 1037 uint32_t block; 1038 uint32_t flags; 1039 uint32_t version; 1040 /* v1 version specific params */ 1041 uint32_t gamut_first; 1042 uint32_t tbl_size[MDP_GAMUT_TABLE_NUM]; 1043 uint16_t *r_tbl[MDP_GAMUT_TABLE_NUM]; 1044 uint16_t *g_tbl[MDP_GAMUT_TABLE_NUM]; 1045 uint16_t *b_tbl[MDP_GAMUT_TABLE_NUM]; 1046 /* params for newer versions of gamut */ 1047 void *cfg_payload; 1048 }; 1049 1050 enum { 1051 mdp_gamut_fine_mode = 0x1, 1052 mdp_gamut_coarse_mode, 1053 }; 1054 1055 struct mdp_gamut_data_v1_7 { 1056 uint32_t mode; 1057 uint32_t map_en; 1058 uint32_t tbl_size[MDP_GAMUT_TABLE_NUM_V1_7]; 1059 uint32_t *c0_data[MDP_GAMUT_TABLE_NUM_V1_7]; 1060 uint32_t *c1_c2_data[MDP_GAMUT_TABLE_NUM_V1_7]; 1061 uint32_t tbl_scale_off_sz[MDP_GAMUT_SCALE_OFF_TABLE_NUM]; 1062 uint32_t *scale_off_data[MDP_GAMUT_SCALE_OFF_TABLE_NUM]; 1063 }; 1064 1065 struct mdp_calib_config_data { 1066 uint32_t ops; 1067 uint32_t addr; 1068 uint32_t data; 1069 }; 1070 1071 struct mdp_calib_config_buffer { 1072 uint32_t ops; 1073 uint32_t size; 1074 uint32_t *buffer; 1075 }; 1076 1077 struct mdp_calib_dcm_state { 1078 uint32_t ops; 1079 uint32_t dcm_state; 1080 }; 1081 1082 enum { 1083 DCM_UNINIT, 1084 DCM_UNBLANK, 1085 DCM_ENTER, 1086 DCM_EXIT, 1087 DCM_BLANK, 1088 DTM_ENTER, 1089 DTM_EXIT, 1090 }; 1091 1092 #define MDSS_PP_SPLIT_LEFT_ONLY 0x10000000 1093 #define MDSS_PP_SPLIT_RIGHT_ONLY 0x20000000 1094 #define MDSS_PP_SPLIT_MASK 0x30000000 1095 1096 #define MDSS_MAX_BL_BRIGHTNESS 255 1097 #define AD_BL_LIN_LEN 256 1098 #define AD_BL_ATT_LUT_LEN 33 1099 1100 #define MDSS_AD_MODE_AUTO_BL 0x0 1101 #define MDSS_AD_MODE_AUTO_STR 0x1 1102 #define MDSS_AD_MODE_TARG_STR 0x3 1103 #define MDSS_AD_MODE_MAN_STR 0x7 1104 #define MDSS_AD_MODE_CALIB 0xF 1105 1106 #define MDP_PP_AD_INIT 0x10 1107 #define MDP_PP_AD_CFG 0x20 1108 1109 struct mdss_ad_init { 1110 uint32_t asym_lut[33]; 1111 uint32_t color_corr_lut[33]; 1112 uint8_t i_control[2]; 1113 uint16_t black_lvl; 1114 uint16_t white_lvl; 1115 uint8_t var; 1116 uint8_t limit_ampl; 1117 uint8_t i_dither; 1118 uint8_t slope_max; 1119 uint8_t slope_min; 1120 uint8_t dither_ctl; 1121 uint8_t format; 1122 uint8_t auto_size; 1123 uint16_t frame_w; 1124 uint16_t frame_h; 1125 uint8_t logo_v; 1126 uint8_t logo_h; 1127 uint32_t alpha; 1128 uint32_t alpha_base; 1129 uint32_t al_thresh; 1130 uint32_t bl_lin_len; 1131 uint32_t bl_att_len; 1132 uint32_t *bl_lin; 1133 uint32_t *bl_lin_inv; 1134 uint32_t *bl_att_lut; 1135 }; 1136 1137 #define MDSS_AD_BL_CTRL_MODE_EN 1 1138 #define MDSS_AD_BL_CTRL_MODE_DIS 0 1139 struct mdss_ad_cfg { 1140 uint32_t mode; 1141 uint32_t al_calib_lut[33]; 1142 uint16_t backlight_min; 1143 uint16_t backlight_max; 1144 uint16_t backlight_scale; 1145 uint16_t amb_light_min; 1146 uint16_t filter[2]; 1147 uint16_t calib[4]; 1148 uint8_t strength_limit; 1149 uint8_t t_filter_recursion; 1150 uint16_t stab_itr; 1151 uint32_t bl_ctrl_mode; 1152 }; 1153 1154 /* ops uses standard MDP_PP_* flags */ 1155 struct mdss_ad_init_cfg { 1156 uint32_t ops; 1157 union { 1158 struct mdss_ad_init init; 1159 struct mdss_ad_cfg cfg; 1160 } params; 1161 }; 1162 1163 /* mode uses MDSS_AD_MODE_* flags */ 1164 struct mdss_ad_input { 1165 uint32_t mode; 1166 union { 1167 uint32_t amb_light; 1168 uint32_t strength; 1169 uint32_t calib_bl; 1170 } in; 1171 uint32_t output; 1172 }; 1173 1174 #define MDSS_CALIB_MODE_BL 0x1 1175 struct mdss_calib_cfg { 1176 uint32_t ops; 1177 uint32_t calib_mask; 1178 }; 1179 1180 enum { 1181 mdp_op_pcc_cfg, 1182 mdp_op_csc_cfg, 1183 mdp_op_lut_cfg, 1184 mdp_op_qseed_cfg, 1185 mdp_bl_scale_cfg, 1186 mdp_op_pa_cfg, 1187 mdp_op_pa_v2_cfg, 1188 mdp_op_dither_cfg, 1189 mdp_op_gamut_cfg, 1190 mdp_op_calib_cfg, 1191 mdp_op_ad_cfg, 1192 mdp_op_ad_input, 1193 mdp_op_calib_mode, 1194 mdp_op_calib_buffer, 1195 mdp_op_calib_dcm_state, 1196 mdp_op_max, 1197 }; 1198 1199 enum { 1200 WB_FORMAT_NV12, 1201 WB_FORMAT_RGB_565, 1202 WB_FORMAT_RGB_888, 1203 WB_FORMAT_xRGB_8888, 1204 WB_FORMAT_ARGB_8888, 1205 WB_FORMAT_BGRA_8888, 1206 WB_FORMAT_BGRX_8888, 1207 WB_FORMAT_ARGB_8888_INPUT_ALPHA /* Need to support */ 1208 }; 1209 1210 struct msmfb_mdp_pp { 1211 uint32_t op; 1212 union { 1213 struct mdp_pcc_cfg_data pcc_cfg_data; 1214 struct mdp_csc_cfg_data csc_cfg_data; 1215 struct mdp_lut_cfg_data lut_cfg_data; 1216 struct mdp_qseed_cfg_data qseed_cfg_data; 1217 struct mdp_bl_scale_data bl_scale_data; 1218 struct mdp_pa_cfg_data pa_cfg_data; 1219 struct mdp_pa_v2_cfg_data pa_v2_cfg_data; 1220 struct mdp_dither_cfg_data dither_cfg_data; 1221 struct mdp_gamut_cfg_data gamut_cfg_data; 1222 struct mdp_calib_config_data calib_cfg; 1223 struct mdss_ad_init_cfg ad_init_cfg; 1224 struct mdss_calib_cfg mdss_calib_cfg; 1225 struct mdss_ad_input ad_input; 1226 struct mdp_calib_config_buffer calib_buffer; 1227 struct mdp_calib_dcm_state calib_dcm; 1228 } data; 1229 }; 1230 1231 #define FB_METADATA_VIDEO_INFO_CODE_SUPPORT 1 1232 enum { 1233 metadata_op_none, 1234 metadata_op_base_blend, 1235 metadata_op_frame_rate, 1236 metadata_op_vic, 1237 metadata_op_wb_format, 1238 metadata_op_wb_secure, 1239 metadata_op_get_caps, 1240 metadata_op_crc, 1241 metadata_op_get_ion_fd, 1242 metadata_op_max 1243 }; 1244 1245 struct mdp_blend_cfg { 1246 uint32_t is_premultiplied; 1247 }; 1248 1249 struct mdp_mixer_cfg { 1250 uint32_t writeback_format; 1251 uint32_t alpha; 1252 }; 1253 1254 struct mdss_hw_caps { 1255 uint32_t mdp_rev; 1256 uint8_t rgb_pipes; 1257 uint8_t vig_pipes; 1258 uint8_t dma_pipes; 1259 uint8_t max_smp_cnt; 1260 uint8_t smp_per_pipe; 1261 uint32_t features; 1262 }; 1263 1264 struct msmfb_metadata { 1265 uint32_t op; 1266 uint32_t flags; 1267 union { 1268 struct mdp_misr misr_request; 1269 struct mdp_blend_cfg blend_cfg; 1270 struct mdp_mixer_cfg mixer_cfg; 1271 uint32_t panel_frame_rate; 1272 uint32_t video_info_code; 1273 struct mdss_hw_caps caps; 1274 uint8_t secure_en; 1275 int fbmem_ionfd; 1276 } data; 1277 }; 1278 1279 #define MDP_MAX_FENCE_FD 32 1280 #define MDP_BUF_SYNC_FLAG_WAIT 1 1281 #define MDP_BUF_SYNC_FLAG_RETIRE_FENCE 0x10 1282 1283 struct mdp_buf_sync { 1284 uint32_t flags; 1285 uint32_t acq_fen_fd_cnt; 1286 uint32_t session_id; 1287 int *acq_fen_fd; 1288 int *rel_fen_fd; 1289 int *retire_fen_fd; 1290 }; 1291 1292 struct mdp_async_blit_req_list { 1293 struct mdp_buf_sync sync; 1294 uint32_t count; 1295 struct mdp_blit_req req[]; 1296 }; 1297 1298 #define MDP_DISPLAY_COMMIT_OVERLAY 1 1299 1300 struct mdp_display_commit { 1301 uint32_t flags; 1302 uint32_t wait_for_finish; 1303 struct fb_var_screeninfo var; 1304 /* 1305 * user needs to follow guidelines as per below rules 1306 * 1. source split is enabled: l_roi = roi and r_roi = 0 1307 * 2. source split is disabled: 1308 * 2.1 split display: l_roi = l_roi and r_roi = r_roi 1309 * 2.2 non split display: l_roi = roi and r_roi = 0 1310 */ 1311 struct mdp_rect l_roi; 1312 struct mdp_rect r_roi; 1313 }; 1314 1315 /** 1316 * struct mdp_overlay_list - argument for ioctl MSMFB_OVERLAY_PREPARE 1317 * @num_overlays: Number of overlay layers as part of the frame. 1318 * @overlay_list: Pointer to a list of overlay structures identifying 1319 * the layers as part of the frame 1320 * @flags: Flags can be used to extend behavior. 1321 * @processed_overlays: Output parameter indicating how many pipes were 1322 * successful. If there are no errors this number should 1323 * match num_overlays. Otherwise it will indicate the last 1324 * successful index for overlay that couldn't be set. 1325 */ 1326 struct mdp_overlay_list { 1327 uint32_t num_overlays; 1328 struct mdp_overlay **overlay_list; 1329 uint32_t flags; 1330 uint32_t processed_overlays; 1331 }; 1332 1333 struct mdp_page_protection { 1334 uint32_t page_protection; 1335 }; 1336 1337 1338 struct mdp_mixer_info { 1339 int pndx; 1340 int pnum; 1341 int ptype; 1342 int mixer_num; 1343 int z_order; 1344 }; 1345 1346 #define MAX_PIPE_PER_MIXER 7 1347 1348 struct msmfb_mixer_info_req { 1349 int mixer_num; 1350 int cnt; 1351 struct mdp_mixer_info info[MAX_PIPE_PER_MIXER]; 1352 }; 1353 1354 enum { 1355 DISPLAY_SUBSYSTEM_ID, 1356 ROTATOR_SUBSYSTEM_ID, 1357 }; 1358 1359 enum { 1360 MDP_IOMMU_DOMAIN_CP, 1361 MDP_IOMMU_DOMAIN_NS, 1362 }; 1363 1364 enum { 1365 MDP_WRITEBACK_MIRROR_OFF, 1366 MDP_WRITEBACK_MIRROR_ON, 1367 MDP_WRITEBACK_MIRROR_PAUSE, 1368 MDP_WRITEBACK_MIRROR_RESUME, 1369 }; 1370 1371 /* 1372 * The enum values are continued below as preprocessor macro definitions 1373 */ 1374 enum mdp_color_space { 1375 MDP_CSC_ITU_R_601, 1376 MDP_CSC_ITU_R_601_FR, 1377 MDP_CSC_ITU_R_709, 1378 }; 1379 1380 /* 1381 * These definitions are a continuation of the mdp_color_space enum above 1382 */ 1383 #define MDP_CSC_ITU_R_2020 (MDP_CSC_ITU_R_709 + 1) 1384 #define MDP_CSC_ITU_R_2020_FR (MDP_CSC_ITU_R_2020 + 1) 1385 1386 enum { 1387 mdp_igc_v1_7 = 1, 1388 mdp_igc_vmax, 1389 mdp_hist_lut_v1_7, 1390 mdp_hist_lut_vmax, 1391 mdp_pgc_v1_7, 1392 mdp_pgc_vmax, 1393 mdp_dither_v1_7, 1394 mdp_dither_vmax, 1395 mdp_gamut_v1_7, 1396 mdp_gamut_vmax, 1397 mdp_pa_v1_7, 1398 mdp_pa_vmax, 1399 mdp_pcc_v1_7, 1400 mdp_pcc_vmax, 1401 mdp_pp_legacy, 1402 }; 1403 1404 /* PP Features */ 1405 enum { 1406 IGC = 1, 1407 PCC, 1408 GC, 1409 PA, 1410 GAMUT, 1411 DITHER, 1412 QSEED, 1413 HIST_LUT, 1414 HIST, 1415 PP_FEATURE_MAX, 1416 }; 1417 1418 struct mdp_pp_feature_version { 1419 uint32_t pp_feature; 1420 uint32_t version_info; 1421 }; 1422 #endif /*_UAPI_MSM_MDP_H_*/ 1423
