1 //===-- llvm/Target/TargetOpcodes.def - Target Indep Opcodes ------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the target independent instruction opcodes. 11 // 12 //===----------------------------------------------------------------------===// 13 14 // NOTE: NO INCLUDE GUARD DESIRED! 15 16 /// HANDLE_TARGET_OPCODE defines an opcode and its associated enum value. 17 /// 18 #ifndef HANDLE_TARGET_OPCODE 19 #define HANDLE_TARGET_OPCODE(OPC, NUM) 20 #endif 21 22 /// HANDLE_TARGET_OPCODE_MARKER defines an alternative identifier for an opcode. 23 /// 24 #ifndef HANDLE_TARGET_OPCODE_MARKER 25 #define HANDLE_TARGET_OPCODE_MARKER(IDENT, OPC) 26 #endif 27 28 /// Every instruction defined here must also appear in Target.td. 29 /// 30 HANDLE_TARGET_OPCODE(PHI) 31 HANDLE_TARGET_OPCODE(INLINEASM) 32 HANDLE_TARGET_OPCODE(CFI_INSTRUCTION) 33 HANDLE_TARGET_OPCODE(EH_LABEL) 34 HANDLE_TARGET_OPCODE(GC_LABEL) 35 36 /// KILL - This instruction is a noop that is used only to adjust the 37 /// liveness of registers. This can be useful when dealing with 38 /// sub-registers. 39 HANDLE_TARGET_OPCODE(KILL) 40 41 /// EXTRACT_SUBREG - This instruction takes two operands: a register 42 /// that has subregisters, and a subregister index. It returns the 43 /// extracted subregister value. This is commonly used to implement 44 /// truncation operations on target architectures which support it. 45 HANDLE_TARGET_OPCODE(EXTRACT_SUBREG) 46 47 /// INSERT_SUBREG - This instruction takes three operands: a register that 48 /// has subregisters, a register providing an insert value, and a 49 /// subregister index. It returns the value of the first register with the 50 /// value of the second register inserted. The first register is often 51 /// defined by an IMPLICIT_DEF, because it is commonly used to implement 52 /// anyext operations on target architectures which support it. 53 HANDLE_TARGET_OPCODE(INSERT_SUBREG) 54 55 /// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef. 56 HANDLE_TARGET_OPCODE(IMPLICIT_DEF) 57 58 /// SUBREG_TO_REG - Assert the value of bits in a super register. 59 /// The result of this instruction is the value of the second operand inserted 60 /// into the subregister specified by the third operand. All other bits are 61 /// assumed to be equal to the bits in the immediate integer constant in the 62 /// first operand. This instruction just communicates information; No code 63 /// should be generated. 64 /// This is typically used after an instruction where the write to a subregister 65 /// implicitly cleared the bits in the super registers. 66 HANDLE_TARGET_OPCODE(SUBREG_TO_REG) 67 68 /// COPY_TO_REGCLASS - This instruction is a placeholder for a plain 69 /// register-to-register copy into a specific register class. This is only 70 /// used between instruction selection and MachineInstr creation, before 71 /// virtual registers have been created for all the instructions, and it's 72 /// only needed in cases where the register classes implied by the 73 /// instructions are insufficient. It is emitted as a COPY MachineInstr. 74 HANDLE_TARGET_OPCODE(COPY_TO_REGCLASS) 75 76 /// DBG_VALUE - a mapping of the llvm.dbg.value intrinsic 77 HANDLE_TARGET_OPCODE(DBG_VALUE) 78 79 /// REG_SEQUENCE - This variadic instruction is used to form a register that 80 /// represents a consecutive sequence of sub-registers. It's used as a 81 /// register coalescing / allocation aid and must be eliminated before code 82 /// emission. 83 // In SDNode form, the first operand encodes the register class created by 84 // the REG_SEQUENCE, while each subsequent pair names a vreg + subreg index 85 // pair. Once it has been lowered to a MachineInstr, the regclass operand 86 // is no longer present. 87 /// e.g. v1027 = REG_SEQUENCE v1024, 3, v1025, 4, v1026, 5 88 /// After register coalescing references of v1024 should be replace with 89 /// v1027:3, v1025 with v1027:4, etc. 90 HANDLE_TARGET_OPCODE(REG_SEQUENCE) 91 92 /// COPY - Target-independent register copy. This instruction can also be 93 /// used to copy between subregisters of virtual registers. 94 HANDLE_TARGET_OPCODE(COPY) 95 96 /// BUNDLE - This instruction represents an instruction bundle. Instructions 97 /// which immediately follow a BUNDLE instruction which are marked with 98 /// 'InsideBundle' flag are inside the bundle. 99 HANDLE_TARGET_OPCODE(BUNDLE) 100 101 /// Lifetime markers. 102 HANDLE_TARGET_OPCODE(LIFETIME_START) 103 HANDLE_TARGET_OPCODE(LIFETIME_END) 104 105 /// A Stackmap instruction captures the location of live variables at its 106 /// position in the instruction stream. It is followed by a shadow of bytes 107 /// that must lie within the function and not contain another stackmap. 108 HANDLE_TARGET_OPCODE(STACKMAP) 109 110 /// FEntry all - This is a marker instruction which gets translated into a raw fentry call. 111 HANDLE_TARGET_OPCODE(FENTRY_CALL) 112 113 /// Patchable call instruction - this instruction represents a call to a 114 /// constant address, followed by a series of NOPs. It is intended to 115 /// support optimizations for dynamic languages (such as javascript) that 116 /// rewrite calls to runtimes with more efficient code sequences. 117 /// This also implies a stack map. 118 HANDLE_TARGET_OPCODE(PATCHPOINT) 119 120 /// This pseudo-instruction loads the stack guard value. Targets which need 121 /// to prevent the stack guard value or address from being spilled to the 122 /// stack should override TargetLowering::emitLoadStackGuardNode and 123 /// additionally expand this pseudo after register allocation. 124 HANDLE_TARGET_OPCODE(LOAD_STACK_GUARD) 125 126 /// Call instruction with associated vm state for deoptimization and list 127 /// of live pointers for relocation by the garbage collector. It is 128 /// intended to support garbage collection with fully precise relocating 129 /// collectors and deoptimizations in either the callee or caller. 130 HANDLE_TARGET_OPCODE(STATEPOINT) 131 132 /// Instruction that records the offset of a local stack allocation passed to 133 /// llvm.localescape. It has two arguments: the symbol for the label and the 134 /// frame index of the local stack allocation. 135 HANDLE_TARGET_OPCODE(LOCAL_ESCAPE) 136 137 /// Wraps a machine instruction which can fault, bundled with associated 138 /// information on how to handle such a fault. 139 /// For example loading instruction that may page fault, bundled with associated 140 /// information on how to handle such a page fault. It is intended to support 141 /// "zero cost" null checks in managed languages by allowing LLVM to fold 142 /// comparisons into existing memory operations. 143 HANDLE_TARGET_OPCODE(FAULTING_OP) 144 145 /// Wraps a machine instruction to add patchability constraints. An 146 /// instruction wrapped in PATCHABLE_OP has to either have a minimum 147 /// size or be preceded with a nop of that size. The first operand is 148 /// an immediate denoting the minimum size of the instruction, the 149 /// second operand is an immediate denoting the opcode of the original 150 /// instruction. The rest of the operands are the operands of the 151 /// original instruction. 152 HANDLE_TARGET_OPCODE(PATCHABLE_OP) 153 154 /// This is a marker instruction which gets translated into a nop sled, useful 155 /// for inserting instrumentation instructions at runtime. 156 HANDLE_TARGET_OPCODE(PATCHABLE_FUNCTION_ENTER) 157 158 /// Wraps a return instruction and its operands to enable adding nop sleds 159 /// either before or after the return. The nop sleds are useful for inserting 160 /// instrumentation instructions at runtime. 161 /// The patch here replaces the return instruction. 162 HANDLE_TARGET_OPCODE(PATCHABLE_RET) 163 164 /// This is a marker instruction which gets translated into a nop sled, useful 165 /// for inserting instrumentation instructions at runtime. 166 /// The patch here prepends the return instruction. 167 /// The same thing as in x86_64 is not possible for ARM because it has multiple 168 /// return instructions. Furthermore, CPU allows parametrized and even 169 /// conditional return instructions. In the current ARM implementation we are 170 /// making use of the fact that currently LLVM doesn't seem to generate 171 /// conditional return instructions. 172 /// On ARM, the same instruction can be used for popping multiple registers 173 /// from the stack and returning (it just pops pc register too), and LLVM 174 /// generates it sometimes. So we can't insert the sled between this stack 175 /// adjustment and the return without splitting the original instruction into 2 176 /// instructions. So on ARM, rather than jumping into the exit trampoline, we 177 /// call it, it does the tracing, preserves the stack and returns. 178 HANDLE_TARGET_OPCODE(PATCHABLE_FUNCTION_EXIT) 179 180 /// Wraps a tail call instruction and its operands to enable adding nop sleds 181 /// either before or after the tail exit. We use this as a disambiguation from 182 /// PATCHABLE_RET which specifically only works for return instructions. 183 HANDLE_TARGET_OPCODE(PATCHABLE_TAIL_CALL) 184 185 /// Wraps a logging call and its arguments with nop sleds. At runtime, this can be 186 /// patched to insert instrumentation instructions. 187 HANDLE_TARGET_OPCODE(PATCHABLE_EVENT_CALL) 188 189 /// The following generic opcodes are not supposed to appear after ISel. 190 /// This is something we might want to relax, but for now, this is convenient 191 /// to produce diagnostics. 192 193 /// Generic ADD instruction. This is an integer add. 194 HANDLE_TARGET_OPCODE(G_ADD) 195 HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPCODE_START, G_ADD) 196 197 /// Generic SUB instruction. This is an integer sub. 198 HANDLE_TARGET_OPCODE(G_SUB) 199 200 // Generic multiply instruction. 201 HANDLE_TARGET_OPCODE(G_MUL) 202 203 // Generic signed division instruction. 204 HANDLE_TARGET_OPCODE(G_SDIV) 205 206 // Generic unsigned division instruction. 207 HANDLE_TARGET_OPCODE(G_UDIV) 208 209 // Generic signed remainder instruction. 210 HANDLE_TARGET_OPCODE(G_SREM) 211 212 // Generic unsigned remainder instruction. 213 HANDLE_TARGET_OPCODE(G_UREM) 214 215 /// Generic bitwise and instruction. 216 HANDLE_TARGET_OPCODE(G_AND) 217 218 /// Generic bitwise or instruction. 219 HANDLE_TARGET_OPCODE(G_OR) 220 221 /// Generic bitwise exclusive-or instruction. 222 HANDLE_TARGET_OPCODE(G_XOR) 223 224 225 /// Generic instruction to materialize the address of an alloca or other 226 /// stack-based object. 227 HANDLE_TARGET_OPCODE(G_FRAME_INDEX) 228 229 /// Generic reference to global value. 230 HANDLE_TARGET_OPCODE(G_GLOBAL_VALUE) 231 232 /// Generic instruction to extract blocks of bits from the register given 233 /// (typically a sub-register COPY after instruction selection). 234 HANDLE_TARGET_OPCODE(G_EXTRACT) 235 236 HANDLE_TARGET_OPCODE(G_UNMERGE_VALUES) 237 238 /// Generic instruction to insert blocks of bits from the registers given into 239 /// the source. 240 HANDLE_TARGET_OPCODE(G_INSERT) 241 242 /// Generic instruction to paste a variable number of components together into a 243 /// larger register. 244 HANDLE_TARGET_OPCODE(G_SEQUENCE) 245 246 HANDLE_TARGET_OPCODE(G_MERGE_VALUES) 247 248 /// Generic pointer to int conversion. 249 HANDLE_TARGET_OPCODE(G_PTRTOINT) 250 251 /// Generic int to pointer conversion. 252 HANDLE_TARGET_OPCODE(G_INTTOPTR) 253 254 /// Generic bitcast. The source and destination types must be different, or a 255 /// COPY is the relevant instruction. 256 HANDLE_TARGET_OPCODE(G_BITCAST) 257 258 /// Generic load. 259 HANDLE_TARGET_OPCODE(G_LOAD) 260 261 /// Generic store. 262 HANDLE_TARGET_OPCODE(G_STORE) 263 264 /// Generic conditional branch instruction. 265 HANDLE_TARGET_OPCODE(G_BRCOND) 266 267 /// Generic indirect branch instruction. 268 HANDLE_TARGET_OPCODE(G_BRINDIRECT) 269 270 /// Generic intrinsic use (without side effects). 271 HANDLE_TARGET_OPCODE(G_INTRINSIC) 272 273 /// Generic intrinsic use (with side effects). 274 HANDLE_TARGET_OPCODE(G_INTRINSIC_W_SIDE_EFFECTS) 275 276 /// Generic extension allowing rubbish in high bits. 277 HANDLE_TARGET_OPCODE(G_ANYEXT) 278 279 /// Generic instruction to discard the high bits of a register. This differs 280 /// from (G_EXTRACT val, 0) on its action on vectors: G_TRUNC will truncate 281 /// each element individually, G_EXTRACT will typically discard the high 282 /// elements of the vector. 283 HANDLE_TARGET_OPCODE(G_TRUNC) 284 285 /// Generic integer constant. 286 HANDLE_TARGET_OPCODE(G_CONSTANT) 287 288 /// Generic floating constant. 289 HANDLE_TARGET_OPCODE(G_FCONSTANT) 290 291 /// Generic va_start instruction. Stores to its one pointer operand. 292 HANDLE_TARGET_OPCODE(G_VASTART) 293 294 /// Generic va_start instruction. Stores to its one pointer operand. 295 HANDLE_TARGET_OPCODE(G_VAARG) 296 297 // Generic sign extend 298 HANDLE_TARGET_OPCODE(G_SEXT) 299 300 // Generic zero extend 301 HANDLE_TARGET_OPCODE(G_ZEXT) 302 303 // Generic left-shift 304 HANDLE_TARGET_OPCODE(G_SHL) 305 306 // Generic logical right-shift 307 HANDLE_TARGET_OPCODE(G_LSHR) 308 309 // Generic arithmetic right-shift 310 HANDLE_TARGET_OPCODE(G_ASHR) 311 312 /// Generic integer-base comparison, also applicable to vectors of integers. 313 HANDLE_TARGET_OPCODE(G_ICMP) 314 315 /// Generic floating-point comparison, also applicable to vectors. 316 HANDLE_TARGET_OPCODE(G_FCMP) 317 318 /// Generic select. 319 HANDLE_TARGET_OPCODE(G_SELECT) 320 321 /// Generic unsigned add instruction, consuming the normal operands plus a carry 322 /// flag, and similarly producing the result and a carry flag. 323 HANDLE_TARGET_OPCODE(G_UADDE) 324 325 /// Generic unsigned subtract instruction, consuming the normal operands plus a 326 /// carry flag, and similarly producing the result and a carry flag. 327 HANDLE_TARGET_OPCODE(G_USUBE) 328 329 /// Generic signed add instruction, producing the result and a signed overflow 330 /// flag. 331 HANDLE_TARGET_OPCODE(G_SADDO) 332 333 /// Generic signed subtract instruction, producing the result and a signed 334 /// overflow flag. 335 HANDLE_TARGET_OPCODE(G_SSUBO) 336 337 /// Generic unsigned multiply instruction, producing the result and a signed 338 /// overflow flag. 339 HANDLE_TARGET_OPCODE(G_UMULO) 340 341 /// Generic signed multiply instruction, producing the result and a signed 342 /// overflow flag. 343 HANDLE_TARGET_OPCODE(G_SMULO) 344 345 // Multiply two numbers at twice the incoming bit width (unsigned) and return 346 // the high half of the result. 347 HANDLE_TARGET_OPCODE(G_UMULH) 348 349 // Multiply two numbers at twice the incoming bit width (signed) and return 350 // the high half of the result. 351 HANDLE_TARGET_OPCODE(G_SMULH) 352 353 /// Generic FP addition. 354 HANDLE_TARGET_OPCODE(G_FADD) 355 356 /// Generic FP subtraction. 357 HANDLE_TARGET_OPCODE(G_FSUB) 358 359 /// Generic FP multiplication. 360 HANDLE_TARGET_OPCODE(G_FMUL) 361 362 /// Generic FP division. 363 HANDLE_TARGET_OPCODE(G_FDIV) 364 365 /// Generic FP remainder. 366 HANDLE_TARGET_OPCODE(G_FREM) 367 368 /// Generic FP exponentiation. 369 HANDLE_TARGET_OPCODE(G_FPOW) 370 371 /// Generic FP negation. 372 HANDLE_TARGET_OPCODE(G_FNEG) 373 374 /// Generic FP extension. 375 HANDLE_TARGET_OPCODE(G_FPEXT) 376 377 /// Generic float to signed-int conversion 378 HANDLE_TARGET_OPCODE(G_FPTRUNC) 379 380 /// Generic float to signed-int conversion 381 HANDLE_TARGET_OPCODE(G_FPTOSI) 382 383 /// Generic float to unsigned-int conversion 384 HANDLE_TARGET_OPCODE(G_FPTOUI) 385 386 /// Generic signed-int to float conversion 387 HANDLE_TARGET_OPCODE(G_SITOFP) 388 389 /// Generic unsigned-int to float conversion 390 HANDLE_TARGET_OPCODE(G_UITOFP) 391 392 /// Generic pointer offset 393 HANDLE_TARGET_OPCODE(G_GEP) 394 395 /// Clear the specified number of low bits in a pointer. This rounds the value 396 /// *down* to the given alignment. 397 HANDLE_TARGET_OPCODE(G_PTR_MASK) 398 399 /// Generic BRANCH instruction. This is an unconditional branch. 400 HANDLE_TARGET_OPCODE(G_BR) 401 402 /// Generic insertelement. 403 HANDLE_TARGET_OPCODE(G_INSERT_VECTOR_ELT) 404 405 /// Generic extractelement. 406 HANDLE_TARGET_OPCODE(G_EXTRACT_VECTOR_ELT) 407 408 /// Generic shufflevector. 409 HANDLE_TARGET_OPCODE(G_SHUFFLE_VECTOR) 410 411 // TODO: Add more generic opcodes as we move along. 412 413 /// Marker for the end of the generic opcode. 414 /// This is used to check if an opcode is in the range of the 415 /// generic opcodes. 416 HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPCODE_END, G_SHUFFLE_VECTOR) 417 418 /// BUILTIN_OP_END - This must be the last enum value in this list. 419 /// The target-specific post-isel opcode values start here. 420 HANDLE_TARGET_OPCODE_MARKER(GENERIC_OP_END, PRE_ISEL_GENERIC_OPCODE_END) 421
