1 //===--- AMDGPUKernelDescriptor.h -------------------------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 /// \file 11 /// \brief AMDGPU kernel descriptor definitions. For more information, visit 12 /// https://llvm.org/docs/AMDGPUUsage.html#kernel-descriptor-for-gfx6-gfx9 13 // 14 //===----------------------------------------------------------------------===// 15 16 #ifndef LLVM_SUPPORT_AMDGPUKERNELDESCRIPTOR_H 17 #define LLVM_SUPPORT_AMDGPUKERNELDESCRIPTOR_H 18 19 #include <cstdint> 20 21 // Creates enumeration entries used for packing bits into integers. Enumeration 22 // entries include bit shift amount, bit width, and bit mask. 23 #define AMDGPU_BITS_ENUM_ENTRY(name, shift, width) \ 24 name ## _SHIFT = (shift), \ 25 name ## _WIDTH = (width), \ 26 name = (((1 << (width)) - 1) << (shift)) \ 27 28 // Gets bits for specified bit mask from specified source. 29 #define AMDGPU_BITS_GET(src, mask) \ 30 ((src & mask) >> mask ## _SHIFT) \ 31 32 // Sets bits for specified bit mask in specified destination. 33 #define AMDGPU_BITS_SET(dst, mask, val) \ 34 dst &= (~(1 << mask ## _SHIFT) & ~mask); \ 35 dst |= (((val) << mask ## _SHIFT) & mask) \ 36 37 namespace llvm { 38 namespace AMDGPU { 39 namespace HSAKD { 40 41 /// \brief Floating point rounding modes. 42 enum : uint8_t { 43 AMDGPU_FLOAT_ROUND_MODE_NEAR_EVEN = 0, 44 AMDGPU_FLOAT_ROUND_MODE_PLUS_INFINITY = 1, 45 AMDGPU_FLOAT_ROUND_MODE_MINUS_INFINITY = 2, 46 AMDGPU_FLOAT_ROUND_MODE_ZERO = 3, 47 }; 48 49 /// \brief Floating point denorm modes. 50 enum : uint8_t { 51 AMDGPU_FLOAT_DENORM_MODE_FLUSH_SRC_DST = 0, 52 AMDGPU_FLOAT_DENORM_MODE_FLUSH_DST = 1, 53 AMDGPU_FLOAT_DENORM_MODE_FLUSH_SRC = 2, 54 AMDGPU_FLOAT_DENORM_MODE_FLUSH_NONE = 3, 55 }; 56 57 /// \brief System VGPR workitem IDs. 58 enum : uint8_t { 59 AMDGPU_SYSTEM_VGPR_WORKITEM_ID_X = 0, 60 AMDGPU_SYSTEM_VGPR_WORKITEM_ID_X_Y = 1, 61 AMDGPU_SYSTEM_VGPR_WORKITEM_ID_X_Y_Z = 2, 62 AMDGPU_SYSTEM_VGPR_WORKITEM_ID_UNDEFINED = 3, 63 }; 64 65 /// \brief Compute program resource register one layout. 66 enum ComputePgmRsrc1 { 67 AMDGPU_BITS_ENUM_ENTRY(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6), 68 AMDGPU_BITS_ENUM_ENTRY(GRANULATED_WAVEFRONT_SGPR_COUNT, 6, 4), 69 AMDGPU_BITS_ENUM_ENTRY(PRIORITY, 10, 2), 70 AMDGPU_BITS_ENUM_ENTRY(FLOAT_ROUND_MODE_32, 12, 2), 71 AMDGPU_BITS_ENUM_ENTRY(FLOAT_ROUND_MODE_16_64, 14, 2), 72 AMDGPU_BITS_ENUM_ENTRY(FLOAT_DENORM_MODE_32, 16, 2), 73 AMDGPU_BITS_ENUM_ENTRY(FLOAT_DENORM_MODE_16_64, 18, 2), 74 AMDGPU_BITS_ENUM_ENTRY(PRIV, 20, 1), 75 AMDGPU_BITS_ENUM_ENTRY(ENABLE_DX10_CLAMP, 21, 1), 76 AMDGPU_BITS_ENUM_ENTRY(DEBUG_MODE, 22, 1), 77 AMDGPU_BITS_ENUM_ENTRY(ENABLE_IEEE_MODE, 23, 1), 78 AMDGPU_BITS_ENUM_ENTRY(BULKY, 24, 1), 79 AMDGPU_BITS_ENUM_ENTRY(CDBG_USER, 25, 1), 80 AMDGPU_BITS_ENUM_ENTRY(FP16_OVFL, 26, 1), 81 AMDGPU_BITS_ENUM_ENTRY(RESERVED0, 27, 5), 82 }; 83 84 /// \brief Compute program resource register two layout. 85 enum ComputePgmRsrc2 { 86 AMDGPU_BITS_ENUM_ENTRY(ENABLE_SGPR_PRIVATE_SEGMENT_WAVE_OFFSET, 0, 1), 87 AMDGPU_BITS_ENUM_ENTRY(USER_SGPR_COUNT, 1, 5), 88 AMDGPU_BITS_ENUM_ENTRY(ENABLE_TRAP_HANDLER, 6, 1), 89 AMDGPU_BITS_ENUM_ENTRY(ENABLE_SGPR_WORKGROUP_ID_X, 7, 1), 90 AMDGPU_BITS_ENUM_ENTRY(ENABLE_SGPR_WORKGROUP_ID_Y, 8, 1), 91 AMDGPU_BITS_ENUM_ENTRY(ENABLE_SGPR_WORKGROUP_ID_Z, 9, 1), 92 AMDGPU_BITS_ENUM_ENTRY(ENABLE_SGPR_WORKGROUP_INFO, 10, 1), 93 AMDGPU_BITS_ENUM_ENTRY(ENABLE_VGPR_WORKITEM_ID, 11, 2), 94 AMDGPU_BITS_ENUM_ENTRY(ENABLE_EXCEPTION_ADDRESS_WATCH, 13, 1), 95 AMDGPU_BITS_ENUM_ENTRY(ENABLE_EXCEPTION_MEMORY, 14, 1), 96 AMDGPU_BITS_ENUM_ENTRY(GRANULATED_LDS_SIZE, 15, 9), 97 AMDGPU_BITS_ENUM_ENTRY(ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION, 24, 1), 98 AMDGPU_BITS_ENUM_ENTRY(ENABLE_EXCEPTION_FP_DENORMAL_SOURCE, 25, 1), 99 AMDGPU_BITS_ENUM_ENTRY(ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO, 26, 1), 100 AMDGPU_BITS_ENUM_ENTRY(ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW, 27, 1), 101 AMDGPU_BITS_ENUM_ENTRY(ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW, 28, 1), 102 AMDGPU_BITS_ENUM_ENTRY(ENABLE_EXCEPTION_IEEE_754_FP_INEXACT, 29, 1), 103 AMDGPU_BITS_ENUM_ENTRY(ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO, 30, 1), 104 AMDGPU_BITS_ENUM_ENTRY(RESERVED1, 31, 1), 105 }; 106 107 /// \brief Kernel descriptor layout. This layout should be kept backwards 108 /// compatible as it is consumed by the command processor. 109 struct KernelDescriptor final { 110 uint32_t GroupSegmentFixedSize; 111 uint32_t PrivateSegmentFixedSize; 112 uint32_t MaxFlatWorkGroupSize; 113 uint64_t IsDynamicCallStack : 1; 114 uint64_t IsXNACKEnabled : 1; 115 uint64_t Reserved0 : 30; 116 int64_t KernelCodeEntryByteOffset; 117 uint64_t Reserved1[3]; 118 uint32_t ComputePgmRsrc1; 119 uint32_t ComputePgmRsrc2; 120 uint64_t EnableSGPRPrivateSegmentBuffer : 1; 121 uint64_t EnableSGPRDispatchPtr : 1; 122 uint64_t EnableSGPRQueuePtr : 1; 123 uint64_t EnableSGPRKernargSegmentPtr : 1; 124 uint64_t EnableSGPRDispatchID : 1; 125 uint64_t EnableSGPRFlatScratchInit : 1; 126 uint64_t EnableSGPRPrivateSegmentSize : 1; 127 uint64_t EnableSGPRGridWorkgroupCountX : 1; 128 uint64_t EnableSGPRGridWorkgroupCountY : 1; 129 uint64_t EnableSGPRGridWorkgroupCountZ : 1; 130 uint64_t Reserved2 : 54; 131 132 KernelDescriptor() = default; 133 }; 134 135 } // end namespace HSAKD 136 } // end namespace AMDGPU 137 } // end namespace llvm 138 139 #endif // LLVM_SUPPORT_AMDGPUKERNELDESCRIPTOR_H 140
