1 //===- TargetSelectionDAG.td - Common code for DAG isels ---*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the target-independent interfaces used by SelectionDAG 11 // instruction selection generators. 12 // 13 //===----------------------------------------------------------------------===// 14 15 //===----------------------------------------------------------------------===// 16 // Selection DAG Type Constraint definitions. 17 // 18 // Note that the semantics of these constraints are hard coded into tblgen. To 19 // modify or add constraints, you have to hack tblgen. 20 // 21 22 class SDTypeConstraint<int opnum> { 23 int OperandNum = opnum; 24 } 25 26 // SDTCisVT - The specified operand has exactly this VT. 27 class SDTCisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> { 28 ValueType VT = vt; 29 } 30 31 class SDTCisPtrTy<int OpNum> : SDTypeConstraint<OpNum>; 32 33 // SDTCisInt - The specified operand has integer type. 34 class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>; 35 36 // SDTCisFP - The specified operand has floating-point type. 37 class SDTCisFP<int OpNum> : SDTypeConstraint<OpNum>; 38 39 // SDTCisVec - The specified operand has a vector type. 40 class SDTCisVec<int OpNum> : SDTypeConstraint<OpNum>; 41 42 // SDTCisSameAs - The two specified operands have identical types. 43 class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> { 44 int OtherOperandNum = OtherOp; 45 } 46 47 // SDTCisVTSmallerThanOp - The specified operand is a VT SDNode, and its type is 48 // smaller than the 'Other' operand. 49 class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> { 50 int OtherOperandNum = OtherOp; 51 } 52 53 class SDTCisOpSmallerThanOp<int SmallOp, int BigOp> : SDTypeConstraint<SmallOp>{ 54 int BigOperandNum = BigOp; 55 } 56 57 /// SDTCisEltOfVec - This indicates that ThisOp is a scalar type of the same 58 /// type as the element type of OtherOp, which is a vector type. 59 class SDTCisEltOfVec<int ThisOp, int OtherOp> 60 : SDTypeConstraint<ThisOp> { 61 int OtherOpNum = OtherOp; 62 } 63 64 /// SDTCisSubVecOfVec - This indicates that ThisOp is a vector type 65 /// with length less that of OtherOp, which is a vector type. 66 class SDTCisSubVecOfVec<int ThisOp, int OtherOp> 67 : SDTypeConstraint<ThisOp> { 68 int OtherOpNum = OtherOp; 69 } 70 71 // SDTCVecEltisVT - The specified operand is vector type with element type 72 // of VT. 73 class SDTCVecEltisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> { 74 ValueType VT = vt; 75 } 76 77 // SDTCisSameNumEltsAs - The two specified operands have identical number 78 // of elements. 79 class SDTCisSameNumEltsAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> { 80 int OtherOperandNum = OtherOp; 81 } 82 83 // SDTCisSameSizeAs - The two specified operands have identical size. 84 class SDTCisSameSizeAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> { 85 int OtherOperandNum = OtherOp; 86 } 87 88 //===----------------------------------------------------------------------===// 89 // Selection DAG Type Profile definitions. 90 // 91 // These use the constraints defined above to describe the type requirements of 92 // the various nodes. These are not hard coded into tblgen, allowing targets to 93 // add their own if needed. 94 // 95 96 // SDTypeProfile - This profile describes the type requirements of a Selection 97 // DAG node. 98 class SDTypeProfile<int numresults, int numoperands, 99 list<SDTypeConstraint> constraints> { 100 int NumResults = numresults; 101 int NumOperands = numoperands; 102 list<SDTypeConstraint> Constraints = constraints; 103 } 104 105 // Builtin profiles. 106 def SDTIntLeaf: SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'. 107 def SDTFPLeaf : SDTypeProfile<1, 0, [SDTCisFP<0>]>; // for 'fpimm'. 108 def SDTPtrLeaf: SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; // for '&g'. 109 def SDTOther : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'. 110 def SDTUNDEF : SDTypeProfile<1, 0, []>; // for 'undef'. 111 def SDTUnaryOp : SDTypeProfile<1, 1, []>; // for bitconvert. 112 113 def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc. 114 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0> 115 ]>; 116 def SDTIntShiftOp : SDTypeProfile<1, 2, [ // shl, sra, srl 117 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2> 118 ]>; 119 def SDTIntSatNoShOp : SDTypeProfile<1, 2, [ // ssat with no shift 120 SDTCisSameAs<0, 1>, SDTCisInt<2> 121 ]>; 122 def SDTIntBinHiLoOp : SDTypeProfile<2, 2, [ // mulhi, mullo, sdivrem, udivrem 123 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,SDTCisInt<0> 124 ]>; 125 126 def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc. 127 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0> 128 ]>; 129 def SDTFPSignOp : SDTypeProfile<1, 2, [ // fcopysign. 130 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisFP<2> 131 ]>; 132 def SDTFPTernaryOp : SDTypeProfile<1, 3, [ // fmadd, fnmsub, etc. 133 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisFP<0> 134 ]>; 135 def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz, cttz 136 SDTCisSameAs<0, 1>, SDTCisInt<0> 137 ]>; 138 def SDTIntExtendOp : SDTypeProfile<1, 1, [ // sext, zext, anyext 139 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0>, SDTCisSameNumEltsAs<0, 1> 140 ]>; 141 def SDTIntTruncOp : SDTypeProfile<1, 1, [ // trunc 142 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<0, 1>, SDTCisSameNumEltsAs<0, 1> 143 ]>; 144 def SDTFPUnaryOp : SDTypeProfile<1, 1, [ // fneg, fsqrt, etc 145 SDTCisSameAs<0, 1>, SDTCisFP<0> 146 ]>; 147 def SDTFPRoundOp : SDTypeProfile<1, 1, [ // fround 148 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1>, SDTCisSameNumEltsAs<0, 1> 149 ]>; 150 def SDTFPExtendOp : SDTypeProfile<1, 1, [ // fextend 151 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0>, SDTCisSameNumEltsAs<0, 1> 152 ]>; 153 def SDTIntToFPOp : SDTypeProfile<1, 1, [ // [su]int_to_fp 154 SDTCisFP<0>, SDTCisInt<1>, SDTCisSameNumEltsAs<0, 1> 155 ]>; 156 def SDTFPToIntOp : SDTypeProfile<1, 1, [ // fp_to_[su]int 157 SDTCisInt<0>, SDTCisFP<1>, SDTCisSameNumEltsAs<0, 1> 158 ]>; 159 def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg 160 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>, 161 SDTCisVTSmallerThanOp<2, 1> 162 ]>; 163 def SDTExtInvec : SDTypeProfile<1, 1, [ // sext_invec 164 SDTCisInt<0>, SDTCisVec<0>, SDTCisInt<1>, SDTCisVec<1>, 165 SDTCisOpSmallerThanOp<1, 0>, SDTCisSameSizeAs<0,1> 166 ]>; 167 168 def SDTSetCC : SDTypeProfile<1, 3, [ // setcc 169 SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT> 170 ]>; 171 172 def SDTSelect : SDTypeProfile<1, 3, [ // select 173 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3> 174 ]>; 175 176 def SDTVSelect : SDTypeProfile<1, 3, [ // vselect 177 SDTCisVec<0>, SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>, SDTCisSameNumEltsAs<0, 1> 178 ]>; 179 180 def SDTSelectCC : SDTypeProfile<1, 5, [ // select_cc 181 SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisSameAs<0, 3>, 182 SDTCisVT<5, OtherVT> 183 ]>; 184 185 def SDTBr : SDTypeProfile<0, 1, [ // br 186 SDTCisVT<0, OtherVT> 187 ]>; 188 189 def SDTBrCC : SDTypeProfile<0, 4, [ // brcc 190 SDTCisVT<0, OtherVT>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT> 191 ]>; 192 193 def SDTBrcond : SDTypeProfile<0, 2, [ // brcond 194 SDTCisInt<0>, SDTCisVT<1, OtherVT> 195 ]>; 196 197 def SDTBrind : SDTypeProfile<0, 1, [ // brind 198 SDTCisPtrTy<0> 199 ]>; 200 201 def SDTCatchret : SDTypeProfile<0, 2, [ // catchret 202 SDTCisVT<0, OtherVT>, SDTCisVT<1, OtherVT> 203 ]>; 204 205 def SDTNone : SDTypeProfile<0, 0, []>; // ret, trap 206 207 def SDTLoad : SDTypeProfile<1, 1, [ // load 208 SDTCisPtrTy<1> 209 ]>; 210 211 def SDTStore : SDTypeProfile<0, 2, [ // store 212 SDTCisPtrTy<1> 213 ]>; 214 215 def SDTIStore : SDTypeProfile<1, 3, [ // indexed store 216 SDTCisSameAs<0, 2>, SDTCisPtrTy<0>, SDTCisPtrTy<3> 217 ]>; 218 219 def SDTMaskedStore: SDTypeProfile<0, 3, [ // masked store 220 SDTCisPtrTy<0>, SDTCisVec<1>, SDTCisVec<2>, SDTCisSameNumEltsAs<1, 2> 221 ]>; 222 223 def SDTMaskedLoad: SDTypeProfile<1, 3, [ // masked load 224 SDTCisVec<0>, SDTCisPtrTy<1>, SDTCisVec<2>, SDTCisSameAs<0, 3>, 225 SDTCisSameNumEltsAs<0, 2> 226 ]>; 227 228 def SDTMaskedGather: SDTypeProfile<2, 3, [ // masked gather 229 SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<1, 3>, 230 SDTCisPtrTy<4>, SDTCVecEltisVT<1, i1>, SDTCisSameNumEltsAs<0, 1> 231 ]>; 232 233 def SDTMaskedScatter: SDTypeProfile<1, 3, [ // masked scatter 234 SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<0, 2>, SDTCisSameNumEltsAs<0, 1>, 235 SDTCVecEltisVT<0, i1>, SDTCisPtrTy<3> 236 ]>; 237 238 def SDTVecShuffle : SDTypeProfile<1, 2, [ 239 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2> 240 ]>; 241 def SDTVecExtract : SDTypeProfile<1, 2, [ // vector extract 242 SDTCisEltOfVec<0, 1>, SDTCisPtrTy<2> 243 ]>; 244 def SDTVecInsert : SDTypeProfile<1, 3, [ // vector insert 245 SDTCisEltOfVec<2, 1>, SDTCisSameAs<0, 1>, SDTCisPtrTy<3> 246 ]>; 247 248 def SDTSubVecExtract : SDTypeProfile<1, 2, [// subvector extract 249 SDTCisSubVecOfVec<0,1>, SDTCisInt<2> 250 ]>; 251 def SDTSubVecInsert : SDTypeProfile<1, 3, [ // subvector insert 252 SDTCisSubVecOfVec<2, 1>, SDTCisSameAs<0,1>, SDTCisInt<3> 253 ]>; 254 255 def SDTPrefetch : SDTypeProfile<0, 4, [ // prefetch 256 SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, SDTCisSameAs<1, 3>, SDTCisInt<1> 257 ]>; 258 259 def SDTMemBarrier : SDTypeProfile<0, 5, [ // memory barrier 260 SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisSameAs<0,4>, 261 SDTCisInt<0> 262 ]>; 263 def SDTAtomicFence : SDTypeProfile<0, 2, [ 264 SDTCisSameAs<0,1>, SDTCisPtrTy<0> 265 ]>; 266 def SDTAtomic3 : SDTypeProfile<1, 3, [ 267 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisInt<0>, SDTCisPtrTy<1> 268 ]>; 269 def SDTAtomic2 : SDTypeProfile<1, 2, [ 270 SDTCisSameAs<0,2>, SDTCisInt<0>, SDTCisPtrTy<1> 271 ]>; 272 def SDTAtomicStore : SDTypeProfile<0, 2, [ 273 SDTCisPtrTy<0>, SDTCisInt<1> 274 ]>; 275 def SDTAtomicLoad : SDTypeProfile<1, 1, [ 276 SDTCisInt<0>, SDTCisPtrTy<1> 277 ]>; 278 279 def SDTConvertOp : SDTypeProfile<1, 5, [ //cvtss, su, us, uu, ff, fs, fu, sf, su 280 SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>, SDTCisPtrTy<4>, SDTCisPtrTy<5> 281 ]>; 282 283 class SDCallSeqStart<list<SDTypeConstraint> constraints> : 284 SDTypeProfile<0, 2, constraints>; 285 class SDCallSeqEnd<list<SDTypeConstraint> constraints> : 286 SDTypeProfile<0, 2, constraints>; 287 288 //===----------------------------------------------------------------------===// 289 // Selection DAG Node Properties. 290 // 291 // Note: These are hard coded into tblgen. 292 // 293 class SDNodeProperty; 294 def SDNPCommutative : SDNodeProperty; // X op Y == Y op X 295 def SDNPAssociative : SDNodeProperty; // (X op Y) op Z == X op (Y op Z) 296 def SDNPHasChain : SDNodeProperty; // R/W chain operand and result 297 def SDNPOutGlue : SDNodeProperty; // Write a flag result 298 def SDNPInGlue : SDNodeProperty; // Read a flag operand 299 def SDNPOptInGlue : SDNodeProperty; // Optionally read a flag operand 300 def SDNPMayStore : SDNodeProperty; // May write to memory, sets 'mayStore'. 301 def SDNPMayLoad : SDNodeProperty; // May read memory, sets 'mayLoad'. 302 def SDNPSideEffect : SDNodeProperty; // Sets 'HasUnmodelledSideEffects'. 303 def SDNPMemOperand : SDNodeProperty; // Touches memory, has assoc MemOperand 304 def SDNPVariadic : SDNodeProperty; // Node has variable arguments. 305 def SDNPWantRoot : SDNodeProperty; // ComplexPattern gets the root of match 306 def SDNPWantParent : SDNodeProperty; // ComplexPattern gets the parent 307 308 //===----------------------------------------------------------------------===// 309 // Selection DAG Pattern Operations 310 class SDPatternOperator { 311 list<SDNodeProperty> Properties = []; 312 } 313 314 //===----------------------------------------------------------------------===// 315 // Selection DAG Node definitions. 316 // 317 class SDNode<string opcode, SDTypeProfile typeprof, 318 list<SDNodeProperty> props = [], string sdclass = "SDNode"> 319 : SDPatternOperator { 320 string Opcode = opcode; 321 string SDClass = sdclass; 322 let Properties = props; 323 SDTypeProfile TypeProfile = typeprof; 324 } 325 326 // Special TableGen-recognized dag nodes 327 def set; 328 def implicit; 329 def node; 330 def srcvalue; 331 332 def imm : SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">; 333 def timm : SDNode<"ISD::TargetConstant",SDTIntLeaf, [], "ConstantSDNode">; 334 def fpimm : SDNode<"ISD::ConstantFP", SDTFPLeaf , [], "ConstantFPSDNode">; 335 def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">; 336 def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">; 337 def cond : SDNode<"ISD::CONDCODE" , SDTOther , [], "CondCodeSDNode">; 338 def undef : SDNode<"ISD::UNDEF" , SDTUNDEF , []>; 339 def globaladdr : SDNode<"ISD::GlobalAddress", SDTPtrLeaf, [], 340 "GlobalAddressSDNode">; 341 def tglobaladdr : SDNode<"ISD::TargetGlobalAddress", SDTPtrLeaf, [], 342 "GlobalAddressSDNode">; 343 def globaltlsaddr : SDNode<"ISD::GlobalTLSAddress", SDTPtrLeaf, [], 344 "GlobalAddressSDNode">; 345 def tglobaltlsaddr : SDNode<"ISD::TargetGlobalTLSAddress", SDTPtrLeaf, [], 346 "GlobalAddressSDNode">; 347 def constpool : SDNode<"ISD::ConstantPool", SDTPtrLeaf, [], 348 "ConstantPoolSDNode">; 349 def tconstpool : SDNode<"ISD::TargetConstantPool", SDTPtrLeaf, [], 350 "ConstantPoolSDNode">; 351 def jumptable : SDNode<"ISD::JumpTable", SDTPtrLeaf, [], 352 "JumpTableSDNode">; 353 def tjumptable : SDNode<"ISD::TargetJumpTable", SDTPtrLeaf, [], 354 "JumpTableSDNode">; 355 def frameindex : SDNode<"ISD::FrameIndex", SDTPtrLeaf, [], 356 "FrameIndexSDNode">; 357 def tframeindex : SDNode<"ISD::TargetFrameIndex", SDTPtrLeaf, [], 358 "FrameIndexSDNode">; 359 def externalsym : SDNode<"ISD::ExternalSymbol", SDTPtrLeaf, [], 360 "ExternalSymbolSDNode">; 361 def texternalsym: SDNode<"ISD::TargetExternalSymbol", SDTPtrLeaf, [], 362 "ExternalSymbolSDNode">; 363 def mcsym: SDNode<"ISD::MCSymbol", SDTPtrLeaf, [], "MCSymbolSDNode">; 364 def blockaddress : SDNode<"ISD::BlockAddress", SDTPtrLeaf, [], 365 "BlockAddressSDNode">; 366 def tblockaddress: SDNode<"ISD::TargetBlockAddress", SDTPtrLeaf, [], 367 "BlockAddressSDNode">; 368 369 def add : SDNode<"ISD::ADD" , SDTIntBinOp , 370 [SDNPCommutative, SDNPAssociative]>; 371 def sub : SDNode<"ISD::SUB" , SDTIntBinOp>; 372 def mul : SDNode<"ISD::MUL" , SDTIntBinOp, 373 [SDNPCommutative, SDNPAssociative]>; 374 def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>; 375 def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>; 376 def smullohi : SDNode<"ISD::SMUL_LOHI" , SDTIntBinHiLoOp, [SDNPCommutative]>; 377 def umullohi : SDNode<"ISD::UMUL_LOHI" , SDTIntBinHiLoOp, [SDNPCommutative]>; 378 def sdiv : SDNode<"ISD::SDIV" , SDTIntBinOp>; 379 def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>; 380 def srem : SDNode<"ISD::SREM" , SDTIntBinOp>; 381 def urem : SDNode<"ISD::UREM" , SDTIntBinOp>; 382 def sdivrem : SDNode<"ISD::SDIVREM" , SDTIntBinHiLoOp>; 383 def udivrem : SDNode<"ISD::UDIVREM" , SDTIntBinHiLoOp>; 384 def srl : SDNode<"ISD::SRL" , SDTIntShiftOp>; 385 def sra : SDNode<"ISD::SRA" , SDTIntShiftOp>; 386 def shl : SDNode<"ISD::SHL" , SDTIntShiftOp>; 387 def rotl : SDNode<"ISD::ROTL" , SDTIntShiftOp>; 388 def rotr : SDNode<"ISD::ROTR" , SDTIntShiftOp>; 389 def and : SDNode<"ISD::AND" , SDTIntBinOp, 390 [SDNPCommutative, SDNPAssociative]>; 391 def or : SDNode<"ISD::OR" , SDTIntBinOp, 392 [SDNPCommutative, SDNPAssociative]>; 393 def xor : SDNode<"ISD::XOR" , SDTIntBinOp, 394 [SDNPCommutative, SDNPAssociative]>; 395 def addc : SDNode<"ISD::ADDC" , SDTIntBinOp, 396 [SDNPCommutative, SDNPOutGlue]>; 397 def adde : SDNode<"ISD::ADDE" , SDTIntBinOp, 398 [SDNPCommutative, SDNPOutGlue, SDNPInGlue]>; 399 def subc : SDNode<"ISD::SUBC" , SDTIntBinOp, 400 [SDNPOutGlue]>; 401 def sube : SDNode<"ISD::SUBE" , SDTIntBinOp, 402 [SDNPOutGlue, SDNPInGlue]>; 403 def smin : SDNode<"ISD::SMIN" , SDTIntBinOp, 404 [SDNPCommutative, SDNPAssociative]>; 405 def smax : SDNode<"ISD::SMAX" , SDTIntBinOp, 406 [SDNPCommutative, SDNPAssociative]>; 407 def umin : SDNode<"ISD::UMIN" , SDTIntBinOp, 408 [SDNPCommutative, SDNPAssociative]>; 409 def umax : SDNode<"ISD::UMAX" , SDTIntBinOp, 410 [SDNPCommutative, SDNPAssociative]>; 411 412 def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>; 413 def sext_invec : SDNode<"ISD::SIGN_EXTEND_VECTOR_INREG", SDTExtInvec>; 414 def zext_invec : SDNode<"ISD::ZERO_EXTEND_VECTOR_INREG", SDTExtInvec>; 415 416 def abs : SDNode<"ISD::ABS" , SDTIntUnaryOp>; 417 def bitreverse : SDNode<"ISD::BITREVERSE" , SDTIntUnaryOp>; 418 def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>; 419 def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>; 420 def cttz : SDNode<"ISD::CTTZ" , SDTIntUnaryOp>; 421 def ctpop : SDNode<"ISD::CTPOP" , SDTIntUnaryOp>; 422 def ctlz_zero_undef : SDNode<"ISD::CTLZ_ZERO_UNDEF", SDTIntUnaryOp>; 423 def cttz_zero_undef : SDNode<"ISD::CTTZ_ZERO_UNDEF", SDTIntUnaryOp>; 424 def sext : SDNode<"ISD::SIGN_EXTEND", SDTIntExtendOp>; 425 def zext : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>; 426 def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>; 427 def trunc : SDNode<"ISD::TRUNCATE" , SDTIntTruncOp>; 428 def bitconvert : SDNode<"ISD::BITCAST" , SDTUnaryOp>; 429 def addrspacecast : SDNode<"ISD::ADDRSPACECAST", SDTUnaryOp>; 430 def extractelt : SDNode<"ISD::EXTRACT_VECTOR_ELT", SDTVecExtract>; 431 def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>; 432 433 def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>; 434 def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>; 435 def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>; 436 def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>; 437 def frem : SDNode<"ISD::FREM" , SDTFPBinOp>; 438 def fma : SDNode<"ISD::FMA" , SDTFPTernaryOp>; 439 def fmad : SDNode<"ISD::FMAD" , SDTFPTernaryOp>; 440 def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>; 441 def fminnum : SDNode<"ISD::FMINNUM" , SDTFPBinOp, 442 [SDNPCommutative, SDNPAssociative]>; 443 def fmaxnum : SDNode<"ISD::FMAXNUM" , SDTFPBinOp, 444 [SDNPCommutative, SDNPAssociative]>; 445 def fminnan : SDNode<"ISD::FMINNAN" , SDTFPBinOp>; 446 def fmaxnan : SDNode<"ISD::FMAXNAN" , SDTFPBinOp>; 447 def fgetsign : SDNode<"ISD::FGETSIGN" , SDTFPToIntOp>; 448 def fcanonicalize : SDNode<"ISD::FCANONICALIZE", SDTFPUnaryOp>; 449 def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>; 450 def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>; 451 def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>; 452 def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>; 453 def fexp2 : SDNode<"ISD::FEXP2" , SDTFPUnaryOp>; 454 def fpow : SDNode<"ISD::FPOW" , SDTFPBinOp>; 455 def flog2 : SDNode<"ISD::FLOG2" , SDTFPUnaryOp>; 456 def frint : SDNode<"ISD::FRINT" , SDTFPUnaryOp>; 457 def ftrunc : SDNode<"ISD::FTRUNC" , SDTFPUnaryOp>; 458 def fceil : SDNode<"ISD::FCEIL" , SDTFPUnaryOp>; 459 def ffloor : SDNode<"ISD::FFLOOR" , SDTFPUnaryOp>; 460 def fnearbyint : SDNode<"ISD::FNEARBYINT" , SDTFPUnaryOp>; 461 def fround : SDNode<"ISD::FROUND" , SDTFPUnaryOp>; 462 463 def fpround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>; 464 def fpextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>; 465 def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPSignOp>; 466 467 def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>; 468 def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>; 469 def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>; 470 def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>; 471 def f16_to_fp : SDNode<"ISD::FP16_TO_FP" , SDTIntToFPOp>; 472 def fp_to_f16 : SDNode<"ISD::FP_TO_FP16" , SDTFPToIntOp>; 473 474 def setcc : SDNode<"ISD::SETCC" , SDTSetCC>; 475 def select : SDNode<"ISD::SELECT" , SDTSelect>; 476 def vselect : SDNode<"ISD::VSELECT" , SDTVSelect>; 477 def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>; 478 479 def brcc : SDNode<"ISD::BR_CC" , SDTBrCC, [SDNPHasChain]>; 480 def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>; 481 def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>; 482 def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>; 483 def catchret : SDNode<"ISD::CATCHRET" , SDTCatchret, 484 [SDNPHasChain, SDNPSideEffect]>; 485 def cleanupret : SDNode<"ISD::CLEANUPRET" , SDTNone, [SDNPHasChain]>; 486 def catchpad : SDNode<"ISD::CATCHPAD" , SDTNone, 487 [SDNPHasChain, SDNPSideEffect]>; 488 489 def trap : SDNode<"ISD::TRAP" , SDTNone, 490 [SDNPHasChain, SDNPSideEffect]>; 491 def debugtrap : SDNode<"ISD::DEBUGTRAP" , SDTNone, 492 [SDNPHasChain, SDNPSideEffect]>; 493 494 def prefetch : SDNode<"ISD::PREFETCH" , SDTPrefetch, 495 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, 496 SDNPMemOperand]>; 497 498 def readcyclecounter : SDNode<"ISD::READCYCLECOUNTER", SDTIntLeaf, 499 [SDNPHasChain, SDNPSideEffect]>; 500 501 def atomic_fence : SDNode<"ISD::ATOMIC_FENCE" , SDTAtomicFence, 502 [SDNPHasChain, SDNPSideEffect]>; 503 504 def atomic_cmp_swap : SDNode<"ISD::ATOMIC_CMP_SWAP" , SDTAtomic3, 505 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 506 def atomic_load_add : SDNode<"ISD::ATOMIC_LOAD_ADD" , SDTAtomic2, 507 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 508 def atomic_swap : SDNode<"ISD::ATOMIC_SWAP", SDTAtomic2, 509 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 510 def atomic_load_sub : SDNode<"ISD::ATOMIC_LOAD_SUB" , SDTAtomic2, 511 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 512 def atomic_load_and : SDNode<"ISD::ATOMIC_LOAD_AND" , SDTAtomic2, 513 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 514 def atomic_load_or : SDNode<"ISD::ATOMIC_LOAD_OR" , SDTAtomic2, 515 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 516 def atomic_load_xor : SDNode<"ISD::ATOMIC_LOAD_XOR" , SDTAtomic2, 517 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 518 def atomic_load_nand: SDNode<"ISD::ATOMIC_LOAD_NAND", SDTAtomic2, 519 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 520 def atomic_load_min : SDNode<"ISD::ATOMIC_LOAD_MIN", SDTAtomic2, 521 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 522 def atomic_load_max : SDNode<"ISD::ATOMIC_LOAD_MAX", SDTAtomic2, 523 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 524 def atomic_load_umin : SDNode<"ISD::ATOMIC_LOAD_UMIN", SDTAtomic2, 525 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 526 def atomic_load_umax : SDNode<"ISD::ATOMIC_LOAD_UMAX", SDTAtomic2, 527 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 528 def atomic_load : SDNode<"ISD::ATOMIC_LOAD", SDTAtomicLoad, 529 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 530 def atomic_store : SDNode<"ISD::ATOMIC_STORE", SDTAtomicStore, 531 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 532 533 def masked_store : SDNode<"ISD::MSTORE", SDTMaskedStore, 534 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 535 def masked_load : SDNode<"ISD::MLOAD", SDTMaskedLoad, 536 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 537 def masked_scatter : SDNode<"ISD::MSCATTER", SDTMaskedScatter, 538 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 539 def masked_gather : SDNode<"ISD::MGATHER", SDTMaskedGather, 540 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 541 542 // Do not use ld, st directly. Use load, extload, sextload, zextload, store, 543 // and truncst (see below). 544 def ld : SDNode<"ISD::LOAD" , SDTLoad, 545 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 546 def st : SDNode<"ISD::STORE" , SDTStore, 547 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 548 def ist : SDNode<"ISD::STORE" , SDTIStore, 549 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 550 551 def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>; 552 def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, -1, []>, []>; 553 def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>, 554 []>; 555 556 // vector_extract/vector_insert are deprecated. extractelt/insertelt 557 // are preferred. 558 def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT", 559 SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>; 560 def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT", 561 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>; 562 def concat_vectors : SDNode<"ISD::CONCAT_VECTORS", 563 SDTypeProfile<1, 2, [SDTCisSubVecOfVec<1, 0>, SDTCisSameAs<1, 2>]>,[]>; 564 565 // This operator does not do subvector type checking. The ARM 566 // backend, at least, needs it. 567 def vector_extract_subvec : SDNode<"ISD::EXTRACT_SUBVECTOR", 568 SDTypeProfile<1, 2, [SDTCisInt<2>, SDTCisVec<1>, SDTCisVec<0>]>, 569 []>; 570 571 // This operator does subvector type checking. 572 def extract_subvector : SDNode<"ISD::EXTRACT_SUBVECTOR", SDTSubVecExtract, []>; 573 def insert_subvector : SDNode<"ISD::INSERT_SUBVECTOR", SDTSubVecInsert, []>; 574 575 // Nodes for intrinsics, you should use the intrinsic itself and let tblgen use 576 // these internally. Don't reference these directly. 577 def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID", 578 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>, 579 [SDNPHasChain]>; 580 def intrinsic_w_chain : SDNode<"ISD::INTRINSIC_W_CHAIN", 581 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, 582 [SDNPHasChain]>; 583 def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC_WO_CHAIN", 584 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, []>; 585 586 def SDT_assertext : SDTypeProfile<1, 1, 587 [SDTCisInt<0>, SDTCisInt<1>, SDTCisSameAs<1, 0>]>; 588 def assertsext : SDNode<"ISD::AssertSext", SDT_assertext>; 589 def assertzext : SDNode<"ISD::AssertZext", SDT_assertext>; 590 591 592 //===----------------------------------------------------------------------===// 593 // Selection DAG Condition Codes 594 595 class CondCode; // ISD::CondCode enums 596 def SETOEQ : CondCode; def SETOGT : CondCode; 597 def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode; 598 def SETONE : CondCode; def SETO : CondCode; def SETUO : CondCode; 599 def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode; 600 def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode; 601 602 def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode; 603 def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode; 604 605 606 //===----------------------------------------------------------------------===// 607 // Selection DAG Node Transformation Functions. 608 // 609 // This mechanism allows targets to manipulate nodes in the output DAG once a 610 // match has been formed. This is typically used to manipulate immediate 611 // values. 612 // 613 class SDNodeXForm<SDNode opc, code xformFunction> { 614 SDNode Opcode = opc; 615 code XFormFunction = xformFunction; 616 } 617 618 def NOOP_SDNodeXForm : SDNodeXForm<imm, [{}]>; 619 620 //===----------------------------------------------------------------------===// 621 // PatPred Subclasses. 622 // 623 // These allow specifying different sorts of predicates that control whether a 624 // node is matched. 625 // 626 class PatPred; 627 628 class CodePatPred<code predicate> : PatPred { 629 code PredicateCode = predicate; 630 } 631 632 633 //===----------------------------------------------------------------------===// 634 // Selection DAG Pattern Fragments. 635 // 636 // Pattern fragments are reusable chunks of dags that match specific things. 637 // They can take arguments and have C++ predicates that control whether they 638 // match. They are intended to make the patterns for common instructions more 639 // compact and readable. 640 // 641 642 /// PatFrag - Represents a pattern fragment. This can match something on the 643 /// DAG, from a single node to multiple nested other fragments. 644 /// 645 class PatFrag<dag ops, dag frag, code pred = [{}], 646 SDNodeXForm xform = NOOP_SDNodeXForm> : SDPatternOperator { 647 dag Operands = ops; 648 dag Fragment = frag; 649 code PredicateCode = pred; 650 code ImmediateCode = [{}]; 651 SDNodeXForm OperandTransform = xform; 652 653 // Define a few pre-packaged predicates. This helps GlobalISel import 654 // existing rules from SelectionDAG for many common cases. 655 // They will be tested prior to the code in pred and must not be used in 656 // ImmLeaf and its subclasses. 657 658 // Is the desired pre-packaged predicate for a load? 659 bit IsLoad = ?; 660 // Is the desired pre-packaged predicate for a store? 661 bit IsStore = ?; 662 663 // cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED; 664 // cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED; 665 bit IsUnindexed = ?; 666 667 // cast<LoadSDNode>(N)->getExtensionType() != ISD::NON_EXTLOAD 668 bit IsNonExtLoad = ?; 669 // cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD; 670 bit IsAnyExtLoad = ?; 671 // cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD; 672 bit IsSignExtLoad = ?; 673 // cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD; 674 bit IsZeroExtLoad = ?; 675 // !cast<StoreSDNode>(N)->isTruncatingStore(); 676 // cast<StoreSDNode>(N)->isTruncatingStore(); 677 bit IsTruncStore = ?; 678 679 // cast<LoadSDNode>(N)->getMemoryVT() == MVT::<VT>; 680 // cast<StoreSDNode>(N)->getMemoryVT() == MVT::<VT>; 681 ValueType MemoryVT = ?; 682 // cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::<VT>; 683 // cast<StoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::<VT>; 684 ValueType ScalarMemoryVT = ?; 685 } 686 687 // OutPatFrag is a pattern fragment that is used as part of an output pattern 688 // (not an input pattern). These do not have predicates or transforms, but are 689 // used to avoid repeated subexpressions in output patterns. 690 class OutPatFrag<dag ops, dag frag> 691 : PatFrag<ops, frag, [{}], NOOP_SDNodeXForm>; 692 693 // PatLeaf's are pattern fragments that have no operands. This is just a helper 694 // to define immediates and other common things concisely. 695 class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm> 696 : PatFrag<(ops), frag, pred, xform>; 697 698 699 // ImmLeaf is a pattern fragment with a constraint on the immediate. The 700 // constraint is a function that is run on the immediate (always with the value 701 // sign extended out to an int64_t) as Imm. For example: 702 // 703 // def immSExt8 : ImmLeaf<i16, [{ return (char)Imm == Imm; }]>; 704 // 705 // this is a more convenient form to match 'imm' nodes in than PatLeaf and also 706 // is preferred over using PatLeaf because it allows the code generator to 707 // reason more about the constraint. 708 // 709 // If FastIsel should ignore all instructions that have an operand of this type, 710 // the FastIselShouldIgnore flag can be set. This is an optimization to reduce 711 // the code size of the generated fast instruction selector. 712 class ImmLeaf<ValueType vt, code pred, SDNodeXForm xform = NOOP_SDNodeXForm, 713 SDNode ImmNode = imm> 714 : PatFrag<(ops), (vt ImmNode), [{}], xform> { 715 let ImmediateCode = pred; 716 bit FastIselShouldIgnore = 0; 717 718 // Is the data type of the immediate an APInt? 719 bit IsAPInt = 0; 720 721 // Is the data type of the immediate an APFloat? 722 bit IsAPFloat = 0; 723 } 724 725 // An ImmLeaf except that Imm is an APInt. This is useful when you need to 726 // zero-extend the immediate instead of sign-extend it. 727 // 728 // Note that FastISel does not currently understand IntImmLeaf and will not 729 // generate code for rules that make use of it. As such, it does not make sense 730 // to replace ImmLeaf with IntImmLeaf. However, replacing PatLeaf with an 731 // IntImmLeaf will allow GlobalISel to import the rule. 732 class IntImmLeaf<ValueType vt, code pred, SDNodeXForm xform = NOOP_SDNodeXForm> 733 : ImmLeaf<vt, pred, xform> { 734 let IsAPInt = 1; 735 let FastIselShouldIgnore = 1; 736 } 737 738 // An ImmLeaf except that Imm is an APFloat. 739 // 740 // Note that FastISel does not currently understand FPImmLeaf and will not 741 // generate code for rules that make use of it. 742 class FPImmLeaf<ValueType vt, code pred, SDNodeXForm xform = NOOP_SDNodeXForm> 743 : ImmLeaf<vt, pred, xform, fpimm> { 744 let IsAPFloat = 1; 745 let FastIselShouldIgnore = 1; 746 } 747 748 // Leaf fragments. 749 750 def vtInt : PatLeaf<(vt), [{ return N->getVT().isInteger(); }]>; 751 def vtFP : PatLeaf<(vt), [{ return N->getVT().isFloatingPoint(); }]>; 752 753 def immAllOnesV: PatLeaf<(build_vector), [{ 754 return ISD::isBuildVectorAllOnes(N); 755 }]>; 756 def immAllZerosV: PatLeaf<(build_vector), [{ 757 return ISD::isBuildVectorAllZeros(N); 758 }]>; 759 760 761 762 // Other helper fragments. 763 def not : PatFrag<(ops node:$in), (xor node:$in, -1)>; 764 def vnot : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV)>; 765 def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>; 766 767 // null_frag - The null pattern operator is used in multiclass instantiations 768 // which accept an SDPatternOperator for use in matching patterns for internal 769 // definitions. When expanding a pattern, if the null fragment is referenced 770 // in the expansion, the pattern is discarded and it is as-if '[]' had been 771 // specified. This allows multiclasses to have the isel patterns be optional. 772 def null_frag : SDPatternOperator; 773 774 // load fragments. 775 def unindexedload : PatFrag<(ops node:$ptr), (ld node:$ptr)> { 776 let IsLoad = 1; 777 let IsUnindexed = 1; 778 } 779 def load : PatFrag<(ops node:$ptr), (unindexedload node:$ptr)> { 780 let IsLoad = 1; 781 let IsNonExtLoad = 1; 782 } 783 784 // extending load fragments. 785 def extload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr)> { 786 let IsLoad = 1; 787 let IsAnyExtLoad = 1; 788 } 789 def sextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr)> { 790 let IsLoad = 1; 791 let IsSignExtLoad = 1; 792 } 793 def zextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr)> { 794 let IsLoad = 1; 795 let IsZeroExtLoad = 1; 796 } 797 798 def extloadi1 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 799 let IsLoad = 1; 800 let MemoryVT = i1; 801 } 802 def extloadi8 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 803 let IsLoad = 1; 804 let MemoryVT = i8; 805 } 806 def extloadi16 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 807 let IsLoad = 1; 808 let MemoryVT = i16; 809 } 810 def extloadi32 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 811 let IsLoad = 1; 812 let MemoryVT = i32; 813 } 814 def extloadf32 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 815 let IsLoad = 1; 816 let MemoryVT = f32; 817 } 818 def extloadf64 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 819 let IsLoad = 1; 820 let MemoryVT = f64; 821 } 822 823 def sextloadi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> { 824 let IsLoad = 1; 825 let MemoryVT = i1; 826 } 827 def sextloadi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> { 828 let IsLoad = 1; 829 let MemoryVT = i8; 830 } 831 def sextloadi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> { 832 let IsLoad = 1; 833 let MemoryVT = i16; 834 } 835 def sextloadi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> { 836 let IsLoad = 1; 837 let MemoryVT = i32; 838 } 839 840 def zextloadi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> { 841 let IsLoad = 1; 842 let MemoryVT = i1; 843 } 844 def zextloadi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> { 845 let IsLoad = 1; 846 let MemoryVT = i8; 847 } 848 def zextloadi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> { 849 let IsLoad = 1; 850 let MemoryVT = i16; 851 } 852 def zextloadi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> { 853 let IsLoad = 1; 854 let MemoryVT = i32; 855 } 856 857 def extloadvi1 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 858 let IsLoad = 1; 859 let ScalarMemoryVT = i1; 860 } 861 def extloadvi8 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 862 let IsLoad = 1; 863 let ScalarMemoryVT = i8; 864 } 865 def extloadvi16 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 866 let IsLoad = 1; 867 let ScalarMemoryVT = i16; 868 } 869 def extloadvi32 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 870 let IsLoad = 1; 871 let ScalarMemoryVT = i32; 872 } 873 def extloadvf32 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 874 let IsLoad = 1; 875 let ScalarMemoryVT = f32; 876 } 877 def extloadvf64 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 878 let IsLoad = 1; 879 let ScalarMemoryVT = f64; 880 } 881 882 def sextloadvi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> { 883 let IsLoad = 1; 884 let ScalarMemoryVT = i1; 885 } 886 def sextloadvi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> { 887 let IsLoad = 1; 888 let ScalarMemoryVT = i8; 889 } 890 def sextloadvi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> { 891 let IsLoad = 1; 892 let ScalarMemoryVT = i16; 893 } 894 def sextloadvi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> { 895 let IsLoad = 1; 896 let ScalarMemoryVT = i32; 897 } 898 899 def zextloadvi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> { 900 let IsLoad = 1; 901 let ScalarMemoryVT = i1; 902 } 903 def zextloadvi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> { 904 let IsLoad = 1; 905 let ScalarMemoryVT = i8; 906 } 907 def zextloadvi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> { 908 let IsLoad = 1; 909 let ScalarMemoryVT = i16; 910 } 911 def zextloadvi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> { 912 let IsLoad = 1; 913 let ScalarMemoryVT = i32; 914 } 915 916 // store fragments. 917 def unindexedstore : PatFrag<(ops node:$val, node:$ptr), 918 (st node:$val, node:$ptr)> { 919 let IsStore = 1; 920 let IsUnindexed = 1; 921 } 922 def store : PatFrag<(ops node:$val, node:$ptr), 923 (unindexedstore node:$val, node:$ptr)> { 924 let IsStore = 1; 925 let IsTruncStore = 0; 926 } 927 928 // truncstore fragments. 929 def truncstore : PatFrag<(ops node:$val, node:$ptr), 930 (unindexedstore node:$val, node:$ptr)> { 931 let IsStore = 1; 932 let IsTruncStore = 1; 933 } 934 def truncstorei8 : PatFrag<(ops node:$val, node:$ptr), 935 (truncstore node:$val, node:$ptr)> { 936 let IsStore = 1; 937 let MemoryVT = i8; 938 } 939 def truncstorei16 : PatFrag<(ops node:$val, node:$ptr), 940 (truncstore node:$val, node:$ptr)> { 941 let IsStore = 1; 942 let MemoryVT = i16; 943 } 944 def truncstorei32 : PatFrag<(ops node:$val, node:$ptr), 945 (truncstore node:$val, node:$ptr)> { 946 let IsStore = 1; 947 let MemoryVT = i32; 948 } 949 def truncstoref32 : PatFrag<(ops node:$val, node:$ptr), 950 (truncstore node:$val, node:$ptr)> { 951 let IsStore = 1; 952 let MemoryVT = f32; 953 } 954 def truncstoref64 : PatFrag<(ops node:$val, node:$ptr), 955 (truncstore node:$val, node:$ptr)> { 956 let IsStore = 1; 957 let MemoryVT = f64; 958 } 959 960 def truncstorevi8 : PatFrag<(ops node:$val, node:$ptr), 961 (truncstore node:$val, node:$ptr)> { 962 let IsStore = 1; 963 let ScalarMemoryVT = i8; 964 } 965 966 def truncstorevi16 : PatFrag<(ops node:$val, node:$ptr), 967 (truncstore node:$val, node:$ptr)> { 968 let IsStore = 1; 969 let ScalarMemoryVT = i16; 970 } 971 972 def truncstorevi32 : PatFrag<(ops node:$val, node:$ptr), 973 (truncstore node:$val, node:$ptr)> { 974 let IsStore = 1; 975 let ScalarMemoryVT = i32; 976 } 977 978 // indexed store fragments. 979 def istore : PatFrag<(ops node:$val, node:$base, node:$offset), 980 (ist node:$val, node:$base, node:$offset)> { 981 let IsStore = 1; 982 let IsTruncStore = 0; 983 } 984 985 def pre_store : PatFrag<(ops node:$val, node:$base, node:$offset), 986 (istore node:$val, node:$base, node:$offset), [{ 987 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 988 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC; 989 }]>; 990 991 def itruncstore : PatFrag<(ops node:$val, node:$base, node:$offset), 992 (ist node:$val, node:$base, node:$offset)> { 993 let IsStore = 1; 994 let IsTruncStore = 1; 995 } 996 def pre_truncst : PatFrag<(ops node:$val, node:$base, node:$offset), 997 (itruncstore node:$val, node:$base, node:$offset), [{ 998 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 999 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC; 1000 }]>; 1001 def pre_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset), 1002 (pre_truncst node:$val, node:$base, node:$offset)> { 1003 let IsStore = 1; 1004 let MemoryVT = i1; 1005 } 1006 def pre_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset), 1007 (pre_truncst node:$val, node:$base, node:$offset)> { 1008 let IsStore = 1; 1009 let MemoryVT = i8; 1010 } 1011 def pre_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset), 1012 (pre_truncst node:$val, node:$base, node:$offset)> { 1013 let IsStore = 1; 1014 let MemoryVT = i16; 1015 } 1016 def pre_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset), 1017 (pre_truncst node:$val, node:$base, node:$offset)> { 1018 let IsStore = 1; 1019 let MemoryVT = i32; 1020 } 1021 def pre_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset), 1022 (pre_truncst node:$val, node:$base, node:$offset)> { 1023 let IsStore = 1; 1024 let MemoryVT = f32; 1025 } 1026 1027 def post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset), 1028 (istore node:$val, node:$ptr, node:$offset), [{ 1029 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 1030 return AM == ISD::POST_INC || AM == ISD::POST_DEC; 1031 }]>; 1032 1033 def post_truncst : PatFrag<(ops node:$val, node:$base, node:$offset), 1034 (itruncstore node:$val, node:$base, node:$offset), [{ 1035 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 1036 return AM == ISD::POST_INC || AM == ISD::POST_DEC; 1037 }]>; 1038 def post_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset), 1039 (post_truncst node:$val, node:$base, node:$offset)> { 1040 let IsStore = 1; 1041 let MemoryVT = i1; 1042 } 1043 def post_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset), 1044 (post_truncst node:$val, node:$base, node:$offset)> { 1045 let IsStore = 1; 1046 let MemoryVT = i8; 1047 } 1048 def post_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset), 1049 (post_truncst node:$val, node:$base, node:$offset)> { 1050 let IsStore = 1; 1051 let MemoryVT = i16; 1052 } 1053 def post_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset), 1054 (post_truncst node:$val, node:$base, node:$offset)> { 1055 let IsStore = 1; 1056 let MemoryVT = i32; 1057 } 1058 def post_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset), 1059 (post_truncst node:$val, node:$base, node:$offset)> { 1060 let IsStore = 1; 1061 let MemoryVT = f32; 1062 } 1063 1064 // nontemporal store fragments. 1065 def nontemporalstore : PatFrag<(ops node:$val, node:$ptr), 1066 (store node:$val, node:$ptr), [{ 1067 return cast<StoreSDNode>(N)->isNonTemporal(); 1068 }]>; 1069 1070 def alignednontemporalstore : PatFrag<(ops node:$val, node:$ptr), 1071 (nontemporalstore node:$val, node:$ptr), [{ 1072 StoreSDNode *St = cast<StoreSDNode>(N); 1073 return St->getAlignment() >= St->getMemoryVT().getStoreSize(); 1074 }]>; 1075 1076 def unalignednontemporalstore : PatFrag<(ops node:$val, node:$ptr), 1077 (nontemporalstore node:$val, node:$ptr), [{ 1078 StoreSDNode *St = cast<StoreSDNode>(N); 1079 return St->getAlignment() < St->getMemoryVT().getStoreSize(); 1080 }]>; 1081 1082 // nontemporal load fragments. 1083 def nontemporalload : PatFrag<(ops node:$ptr), 1084 (load node:$ptr), [{ 1085 return cast<LoadSDNode>(N)->isNonTemporal(); 1086 }]>; 1087 1088 def alignednontemporalload : PatFrag<(ops node:$ptr), 1089 (nontemporalload node:$ptr), [{ 1090 LoadSDNode *Ld = cast<LoadSDNode>(N); 1091 return Ld->getAlignment() >= Ld->getMemoryVT().getStoreSize(); 1092 }]>; 1093 1094 // setcc convenience fragments. 1095 def setoeq : PatFrag<(ops node:$lhs, node:$rhs), 1096 (setcc node:$lhs, node:$rhs, SETOEQ)>; 1097 def setogt : PatFrag<(ops node:$lhs, node:$rhs), 1098 (setcc node:$lhs, node:$rhs, SETOGT)>; 1099 def setoge : PatFrag<(ops node:$lhs, node:$rhs), 1100 (setcc node:$lhs, node:$rhs, SETOGE)>; 1101 def setolt : PatFrag<(ops node:$lhs, node:$rhs), 1102 (setcc node:$lhs, node:$rhs, SETOLT)>; 1103 def setole : PatFrag<(ops node:$lhs, node:$rhs), 1104 (setcc node:$lhs, node:$rhs, SETOLE)>; 1105 def setone : PatFrag<(ops node:$lhs, node:$rhs), 1106 (setcc node:$lhs, node:$rhs, SETONE)>; 1107 def seto : PatFrag<(ops node:$lhs, node:$rhs), 1108 (setcc node:$lhs, node:$rhs, SETO)>; 1109 def setuo : PatFrag<(ops node:$lhs, node:$rhs), 1110 (setcc node:$lhs, node:$rhs, SETUO)>; 1111 def setueq : PatFrag<(ops node:$lhs, node:$rhs), 1112 (setcc node:$lhs, node:$rhs, SETUEQ)>; 1113 def setugt : PatFrag<(ops node:$lhs, node:$rhs), 1114 (setcc node:$lhs, node:$rhs, SETUGT)>; 1115 def setuge : PatFrag<(ops node:$lhs, node:$rhs), 1116 (setcc node:$lhs, node:$rhs, SETUGE)>; 1117 def setult : PatFrag<(ops node:$lhs, node:$rhs), 1118 (setcc node:$lhs, node:$rhs, SETULT)>; 1119 def setule : PatFrag<(ops node:$lhs, node:$rhs), 1120 (setcc node:$lhs, node:$rhs, SETULE)>; 1121 def setune : PatFrag<(ops node:$lhs, node:$rhs), 1122 (setcc node:$lhs, node:$rhs, SETUNE)>; 1123 def seteq : PatFrag<(ops node:$lhs, node:$rhs), 1124 (setcc node:$lhs, node:$rhs, SETEQ)>; 1125 def setgt : PatFrag<(ops node:$lhs, node:$rhs), 1126 (setcc node:$lhs, node:$rhs, SETGT)>; 1127 def setge : PatFrag<(ops node:$lhs, node:$rhs), 1128 (setcc node:$lhs, node:$rhs, SETGE)>; 1129 def setlt : PatFrag<(ops node:$lhs, node:$rhs), 1130 (setcc node:$lhs, node:$rhs, SETLT)>; 1131 def setle : PatFrag<(ops node:$lhs, node:$rhs), 1132 (setcc node:$lhs, node:$rhs, SETLE)>; 1133 def setne : PatFrag<(ops node:$lhs, node:$rhs), 1134 (setcc node:$lhs, node:$rhs, SETNE)>; 1135 1136 multiclass binary_atomic_op_ord<SDNode atomic_op> { 1137 def #NAME#_monotonic : PatFrag<(ops node:$ptr, node:$val), 1138 (!cast<SDNode>(#NAME) node:$ptr, node:$val), [{ 1139 return cast<AtomicSDNode>(N)->getOrdering() == AtomicOrdering::Monotonic; 1140 }]>; 1141 def #NAME#_acquire : PatFrag<(ops node:$ptr, node:$val), 1142 (!cast<SDNode>(#NAME) node:$ptr, node:$val), [{ 1143 return cast<AtomicSDNode>(N)->getOrdering() == AtomicOrdering::Acquire; 1144 }]>; 1145 def #NAME#_release : PatFrag<(ops node:$ptr, node:$val), 1146 (!cast<SDNode>(#NAME) node:$ptr, node:$val), [{ 1147 return cast<AtomicSDNode>(N)->getOrdering() == AtomicOrdering::Release; 1148 }]>; 1149 def #NAME#_acq_rel : PatFrag<(ops node:$ptr, node:$val), 1150 (!cast<SDNode>(#NAME) node:$ptr, node:$val), [{ 1151 return cast<AtomicSDNode>(N)->getOrdering() == AtomicOrdering::AcquireRelease; 1152 }]>; 1153 def #NAME#_seq_cst : PatFrag<(ops node:$ptr, node:$val), 1154 (!cast<SDNode>(#NAME) node:$ptr, node:$val), [{ 1155 return cast<AtomicSDNode>(N)->getOrdering() == AtomicOrdering::SequentiallyConsistent; 1156 }]>; 1157 } 1158 1159 multiclass ternary_atomic_op_ord<SDNode atomic_op> { 1160 def #NAME#_monotonic : PatFrag<(ops node:$ptr, node:$cmp, node:$val), 1161 (!cast<SDNode>(#NAME) node:$ptr, node:$cmp, node:$val), [{ 1162 return cast<AtomicSDNode>(N)->getOrdering() == AtomicOrdering::Monotonic; 1163 }]>; 1164 def #NAME#_acquire : PatFrag<(ops node:$ptr, node:$cmp, node:$val), 1165 (!cast<SDNode>(#NAME) node:$ptr, node:$cmp, node:$val), [{ 1166 return cast<AtomicSDNode>(N)->getOrdering() == AtomicOrdering::Acquire; 1167 }]>; 1168 def #NAME#_release : PatFrag<(ops node:$ptr, node:$cmp, node:$val), 1169 (!cast<SDNode>(#NAME) node:$ptr, node:$cmp, node:$val), [{ 1170 return cast<AtomicSDNode>(N)->getOrdering() == AtomicOrdering::Release; 1171 }]>; 1172 def #NAME#_acq_rel : PatFrag<(ops node:$ptr, node:$cmp, node:$val), 1173 (!cast<SDNode>(#NAME) node:$ptr, node:$cmp, node:$val), [{ 1174 return cast<AtomicSDNode>(N)->getOrdering() == AtomicOrdering::AcquireRelease; 1175 }]>; 1176 def #NAME#_seq_cst : PatFrag<(ops node:$ptr, node:$cmp, node:$val), 1177 (!cast<SDNode>(#NAME) node:$ptr, node:$cmp, node:$val), [{ 1178 return cast<AtomicSDNode>(N)->getOrdering() == AtomicOrdering::SequentiallyConsistent; 1179 }]>; 1180 } 1181 1182 multiclass binary_atomic_op<SDNode atomic_op> { 1183 def _8 : PatFrag<(ops node:$ptr, node:$val), 1184 (atomic_op node:$ptr, node:$val), [{ 1185 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8; 1186 }]>; 1187 def _16 : PatFrag<(ops node:$ptr, node:$val), 1188 (atomic_op node:$ptr, node:$val), [{ 1189 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16; 1190 }]>; 1191 def _32 : PatFrag<(ops node:$ptr, node:$val), 1192 (atomic_op node:$ptr, node:$val), [{ 1193 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32; 1194 }]>; 1195 def _64 : PatFrag<(ops node:$ptr, node:$val), 1196 (atomic_op node:$ptr, node:$val), [{ 1197 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64; 1198 }]>; 1199 1200 defm NAME#_8 : binary_atomic_op_ord<atomic_op>; 1201 defm NAME#_16 : binary_atomic_op_ord<atomic_op>; 1202 defm NAME#_32 : binary_atomic_op_ord<atomic_op>; 1203 defm NAME#_64 : binary_atomic_op_ord<atomic_op>; 1204 } 1205 1206 multiclass ternary_atomic_op<SDNode atomic_op> { 1207 def _8 : PatFrag<(ops node:$ptr, node:$cmp, node:$val), 1208 (atomic_op node:$ptr, node:$cmp, node:$val), [{ 1209 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8; 1210 }]>; 1211 def _16 : PatFrag<(ops node:$ptr, node:$cmp, node:$val), 1212 (atomic_op node:$ptr, node:$cmp, node:$val), [{ 1213 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16; 1214 }]>; 1215 def _32 : PatFrag<(ops node:$ptr, node:$cmp, node:$val), 1216 (atomic_op node:$ptr, node:$cmp, node:$val), [{ 1217 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32; 1218 }]>; 1219 def _64 : PatFrag<(ops node:$ptr, node:$cmp, node:$val), 1220 (atomic_op node:$ptr, node:$cmp, node:$val), [{ 1221 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64; 1222 }]>; 1223 1224 defm NAME#_8 : ternary_atomic_op_ord<atomic_op>; 1225 defm NAME#_16 : ternary_atomic_op_ord<atomic_op>; 1226 defm NAME#_32 : ternary_atomic_op_ord<atomic_op>; 1227 defm NAME#_64 : ternary_atomic_op_ord<atomic_op>; 1228 } 1229 1230 defm atomic_load_add : binary_atomic_op<atomic_load_add>; 1231 defm atomic_swap : binary_atomic_op<atomic_swap>; 1232 defm atomic_load_sub : binary_atomic_op<atomic_load_sub>; 1233 defm atomic_load_and : binary_atomic_op<atomic_load_and>; 1234 defm atomic_load_or : binary_atomic_op<atomic_load_or>; 1235 defm atomic_load_xor : binary_atomic_op<atomic_load_xor>; 1236 defm atomic_load_nand : binary_atomic_op<atomic_load_nand>; 1237 defm atomic_load_min : binary_atomic_op<atomic_load_min>; 1238 defm atomic_load_max : binary_atomic_op<atomic_load_max>; 1239 defm atomic_load_umin : binary_atomic_op<atomic_load_umin>; 1240 defm atomic_load_umax : binary_atomic_op<atomic_load_umax>; 1241 defm atomic_store : binary_atomic_op<atomic_store>; 1242 defm atomic_cmp_swap : ternary_atomic_op<atomic_cmp_swap>; 1243 1244 def atomic_load_8 : 1245 PatFrag<(ops node:$ptr), 1246 (atomic_load node:$ptr), [{ 1247 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8; 1248 }]>; 1249 def atomic_load_16 : 1250 PatFrag<(ops node:$ptr), 1251 (atomic_load node:$ptr), [{ 1252 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16; 1253 }]>; 1254 def atomic_load_32 : 1255 PatFrag<(ops node:$ptr), 1256 (atomic_load node:$ptr), [{ 1257 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32; 1258 }]>; 1259 def atomic_load_64 : 1260 PatFrag<(ops node:$ptr), 1261 (atomic_load node:$ptr), [{ 1262 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64; 1263 }]>; 1264 1265 //===----------------------------------------------------------------------===// 1266 // Selection DAG Pattern Support. 1267 // 1268 // Patterns are what are actually matched against by the target-flavored 1269 // instruction selection DAG. Instructions defined by the target implicitly 1270 // define patterns in most cases, but patterns can also be explicitly added when 1271 // an operation is defined by a sequence of instructions (e.g. loading a large 1272 // immediate value on RISC targets that do not support immediates as large as 1273 // their GPRs). 1274 // 1275 1276 class Pattern<dag patternToMatch, list<dag> resultInstrs> { 1277 dag PatternToMatch = patternToMatch; 1278 list<dag> ResultInstrs = resultInstrs; 1279 list<Predicate> Predicates = []; // See class Instruction in Target.td. 1280 int AddedComplexity = 0; // See class Instruction in Target.td. 1281 } 1282 1283 // Pat - A simple (but common) form of a pattern, which produces a simple result 1284 // not needing a full list. 1285 class Pat<dag pattern, dag result> : Pattern<pattern, [result]>; 1286 1287 //===----------------------------------------------------------------------===// 1288 // Complex pattern definitions. 1289 // 1290 1291 // Complex patterns, e.g. X86 addressing mode, requires pattern matching code 1292 // in C++. NumOperands is the number of operands returned by the select function; 1293 // SelectFunc is the name of the function used to pattern match the max. pattern; 1294 // RootNodes are the list of possible root nodes of the sub-dags to match. 1295 // e.g. X86 addressing mode - def addr : ComplexPattern<4, "SelectAddr", [add]>; 1296 // 1297 class ComplexPattern<ValueType ty, int numops, string fn, 1298 list<SDNode> roots = [], list<SDNodeProperty> props = [], 1299 int complexity = -1> { 1300 ValueType Ty = ty; 1301 int NumOperands = numops; 1302 string SelectFunc = fn; 1303 list<SDNode> RootNodes = roots; 1304 list<SDNodeProperty> Properties = props; 1305 int Complexity = complexity; 1306 } 1307
