1 //===-- llvm/Target/TargetOpcodes.def - Target Indep Opcodes ------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the target independent instruction opcodes. 11 // 12 //===----------------------------------------------------------------------===// 13 14 // NOTE: NO INCLUDE GUARD DESIRED! 15 16 /// HANDLE_TARGET_OPCODE defines an opcode and its associated enum value. 17 /// 18 #ifndef HANDLE_TARGET_OPCODE 19 #define HANDLE_TARGET_OPCODE(OPC, NUM) 20 #endif 21 22 /// HANDLE_TARGET_OPCODE_MARKER defines an alternative identifier for an opcode. 23 /// 24 #ifndef HANDLE_TARGET_OPCODE_MARKER 25 #define HANDLE_TARGET_OPCODE_MARKER(IDENT, OPC) 26 #endif 27 28 /// Every instruction defined here must also appear in Target.td. 29 /// 30 HANDLE_TARGET_OPCODE(PHI) 31 HANDLE_TARGET_OPCODE(INLINEASM) 32 HANDLE_TARGET_OPCODE(CFI_INSTRUCTION) 33 HANDLE_TARGET_OPCODE(EH_LABEL) 34 HANDLE_TARGET_OPCODE(GC_LABEL) 35 HANDLE_TARGET_OPCODE(ANNOTATION_LABEL) 36 37 /// KILL - This instruction is a noop that is used only to adjust the 38 /// liveness of registers. This can be useful when dealing with 39 /// sub-registers. 40 HANDLE_TARGET_OPCODE(KILL) 41 42 /// EXTRACT_SUBREG - This instruction takes two operands: a register 43 /// that has subregisters, and a subregister index. It returns the 44 /// extracted subregister value. This is commonly used to implement 45 /// truncation operations on target architectures which support it. 46 HANDLE_TARGET_OPCODE(EXTRACT_SUBREG) 47 48 /// INSERT_SUBREG - This instruction takes three operands: a register that 49 /// has subregisters, a register providing an insert value, and a 50 /// subregister index. It returns the value of the first register with the 51 /// value of the second register inserted. The first register is often 52 /// defined by an IMPLICIT_DEF, because it is commonly used to implement 53 /// anyext operations on target architectures which support it. 54 HANDLE_TARGET_OPCODE(INSERT_SUBREG) 55 56 /// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef. 57 HANDLE_TARGET_OPCODE(IMPLICIT_DEF) 58 59 /// SUBREG_TO_REG - Assert the value of bits in a super register. 60 /// The result of this instruction is the value of the second operand inserted 61 /// into the subregister specified by the third operand. All other bits are 62 /// assumed to be equal to the bits in the immediate integer constant in the 63 /// first operand. This instruction just communicates information; No code 64 /// should be generated. 65 /// This is typically used after an instruction where the write to a subregister 66 /// implicitly cleared the bits in the super registers. 67 HANDLE_TARGET_OPCODE(SUBREG_TO_REG) 68 69 /// COPY_TO_REGCLASS - This instruction is a placeholder for a plain 70 /// register-to-register copy into a specific register class. This is only 71 /// used between instruction selection and MachineInstr creation, before 72 /// virtual registers have been created for all the instructions, and it's 73 /// only needed in cases where the register classes implied by the 74 /// instructions are insufficient. It is emitted as a COPY MachineInstr. 75 HANDLE_TARGET_OPCODE(COPY_TO_REGCLASS) 76 77 /// DBG_VALUE - a mapping of the llvm.dbg.value intrinsic 78 HANDLE_TARGET_OPCODE(DBG_VALUE) 79 80 /// REG_SEQUENCE - This variadic instruction is used to form a register that 81 /// represents a consecutive sequence of sub-registers. It's used as a 82 /// register coalescing / allocation aid and must be eliminated before code 83 /// emission. 84 // In SDNode form, the first operand encodes the register class created by 85 // the REG_SEQUENCE, while each subsequent pair names a vreg + subreg index 86 // pair. Once it has been lowered to a MachineInstr, the regclass operand 87 // is no longer present. 88 /// e.g. v1027 = REG_SEQUENCE v1024, 3, v1025, 4, v1026, 5 89 /// After register coalescing references of v1024 should be replace with 90 /// v1027:3, v1025 with v1027:4, etc. 91 HANDLE_TARGET_OPCODE(REG_SEQUENCE) 92 93 /// COPY - Target-independent register copy. This instruction can also be 94 /// used to copy between subregisters of virtual registers. 95 HANDLE_TARGET_OPCODE(COPY) 96 97 /// BUNDLE - This instruction represents an instruction bundle. Instructions 98 /// which immediately follow a BUNDLE instruction which are marked with 99 /// 'InsideBundle' flag are inside the bundle. 100 HANDLE_TARGET_OPCODE(BUNDLE) 101 102 /// Lifetime markers. 103 HANDLE_TARGET_OPCODE(LIFETIME_START) 104 HANDLE_TARGET_OPCODE(LIFETIME_END) 105 106 /// A Stackmap instruction captures the location of live variables at its 107 /// position in the instruction stream. It is followed by a shadow of bytes 108 /// that must lie within the function and not contain another stackmap. 109 HANDLE_TARGET_OPCODE(STACKMAP) 110 111 /// FEntry all - This is a marker instruction which gets translated into a raw fentry call. 112 HANDLE_TARGET_OPCODE(FENTRY_CALL) 113 114 /// Patchable call instruction - this instruction represents a call to a 115 /// constant address, followed by a series of NOPs. It is intended to 116 /// support optimizations for dynamic languages (such as javascript) that 117 /// rewrite calls to runtimes with more efficient code sequences. 118 /// This also implies a stack map. 119 HANDLE_TARGET_OPCODE(PATCHPOINT) 120 121 /// This pseudo-instruction loads the stack guard value. Targets which need 122 /// to prevent the stack guard value or address from being spilled to the 123 /// stack should override TargetLowering::emitLoadStackGuardNode and 124 /// additionally expand this pseudo after register allocation. 125 HANDLE_TARGET_OPCODE(LOAD_STACK_GUARD) 126 127 /// Call instruction with associated vm state for deoptimization and list 128 /// of live pointers for relocation by the garbage collector. It is 129 /// intended to support garbage collection with fully precise relocating 130 /// collectors and deoptimizations in either the callee or caller. 131 HANDLE_TARGET_OPCODE(STATEPOINT) 132 133 /// Instruction that records the offset of a local stack allocation passed to 134 /// llvm.localescape. It has two arguments: the symbol for the label and the 135 /// frame index of the local stack allocation. 136 HANDLE_TARGET_OPCODE(LOCAL_ESCAPE) 137 138 /// Wraps a machine instruction which can fault, bundled with associated 139 /// information on how to handle such a fault. 140 /// For example loading instruction that may page fault, bundled with associated 141 /// information on how to handle such a page fault. It is intended to support 142 /// "zero cost" null checks in managed languages by allowing LLVM to fold 143 /// comparisons into existing memory operations. 144 HANDLE_TARGET_OPCODE(FAULTING_OP) 145 146 /// Wraps a machine instruction to add patchability constraints. An 147 /// instruction wrapped in PATCHABLE_OP has to either have a minimum 148 /// size or be preceded with a nop of that size. The first operand is 149 /// an immediate denoting the minimum size of the instruction, the 150 /// second operand is an immediate denoting the opcode of the original 151 /// instruction. The rest of the operands are the operands of the 152 /// original instruction. 153 HANDLE_TARGET_OPCODE(PATCHABLE_OP) 154 155 /// This is a marker instruction which gets translated into a nop sled, useful 156 /// for inserting instrumentation instructions at runtime. 157 HANDLE_TARGET_OPCODE(PATCHABLE_FUNCTION_ENTER) 158 159 /// Wraps a return instruction and its operands to enable adding nop sleds 160 /// either before or after the return. The nop sleds are useful for inserting 161 /// instrumentation instructions at runtime. 162 /// The patch here replaces the return instruction. 163 HANDLE_TARGET_OPCODE(PATCHABLE_RET) 164 165 /// This is a marker instruction which gets translated into a nop sled, useful 166 /// for inserting instrumentation instructions at runtime. 167 /// The patch here prepends the return instruction. 168 /// The same thing as in x86_64 is not possible for ARM because it has multiple 169 /// return instructions. Furthermore, CPU allows parametrized and even 170 /// conditional return instructions. In the current ARM implementation we are 171 /// making use of the fact that currently LLVM doesn't seem to generate 172 /// conditional return instructions. 173 /// On ARM, the same instruction can be used for popping multiple registers 174 /// from the stack and returning (it just pops pc register too), and LLVM 175 /// generates it sometimes. So we can't insert the sled between this stack 176 /// adjustment and the return without splitting the original instruction into 2 177 /// instructions. So on ARM, rather than jumping into the exit trampoline, we 178 /// call it, it does the tracing, preserves the stack and returns. 179 HANDLE_TARGET_OPCODE(PATCHABLE_FUNCTION_EXIT) 180 181 /// Wraps a tail call instruction and its operands to enable adding nop sleds 182 /// either before or after the tail exit. We use this as a disambiguation from 183 /// PATCHABLE_RET which specifically only works for return instructions. 184 HANDLE_TARGET_OPCODE(PATCHABLE_TAIL_CALL) 185 186 /// Wraps a logging call and its arguments with nop sleds. At runtime, this can be 187 /// patched to insert instrumentation instructions. 188 HANDLE_TARGET_OPCODE(PATCHABLE_EVENT_CALL) 189 190 /// The following generic opcodes are not supposed to appear after ISel. 191 /// This is something we might want to relax, but for now, this is convenient 192 /// to produce diagnostics. 193 194 /// Generic ADD instruction. This is an integer add. 195 HANDLE_TARGET_OPCODE(G_ADD) 196 HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPCODE_START, G_ADD) 197 198 /// Generic SUB instruction. This is an integer sub. 199 HANDLE_TARGET_OPCODE(G_SUB) 200 201 // Generic multiply instruction. 202 HANDLE_TARGET_OPCODE(G_MUL) 203 204 // Generic signed division instruction. 205 HANDLE_TARGET_OPCODE(G_SDIV) 206 207 // Generic unsigned division instruction. 208 HANDLE_TARGET_OPCODE(G_UDIV) 209 210 // Generic signed remainder instruction. 211 HANDLE_TARGET_OPCODE(G_SREM) 212 213 // Generic unsigned remainder instruction. 214 HANDLE_TARGET_OPCODE(G_UREM) 215 216 /// Generic bitwise and instruction. 217 HANDLE_TARGET_OPCODE(G_AND) 218 219 /// Generic bitwise or instruction. 220 HANDLE_TARGET_OPCODE(G_OR) 221 222 /// Generic bitwise exclusive-or instruction. 223 HANDLE_TARGET_OPCODE(G_XOR) 224 225 226 HANDLE_TARGET_OPCODE(G_IMPLICIT_DEF) 227 228 /// Generic PHI instruction with types. 229 HANDLE_TARGET_OPCODE(G_PHI) 230 231 /// Generic instruction to materialize the address of an alloca or other 232 /// stack-based object. 233 HANDLE_TARGET_OPCODE(G_FRAME_INDEX) 234 235 /// Generic reference to global value. 236 HANDLE_TARGET_OPCODE(G_GLOBAL_VALUE) 237 238 /// Generic instruction to extract blocks of bits from the register given 239 /// (typically a sub-register COPY after instruction selection). 240 HANDLE_TARGET_OPCODE(G_EXTRACT) 241 242 HANDLE_TARGET_OPCODE(G_UNMERGE_VALUES) 243 244 /// Generic instruction to insert blocks of bits from the registers given into 245 /// the source. 246 HANDLE_TARGET_OPCODE(G_INSERT) 247 248 /// Generic instruction to paste a variable number of components together into a 249 /// larger register. 250 HANDLE_TARGET_OPCODE(G_MERGE_VALUES) 251 252 /// Generic pointer to int conversion. 253 HANDLE_TARGET_OPCODE(G_PTRTOINT) 254 255 /// Generic int to pointer conversion. 256 HANDLE_TARGET_OPCODE(G_INTTOPTR) 257 258 /// Generic bitcast. The source and destination types must be different, or a 259 /// COPY is the relevant instruction. 260 HANDLE_TARGET_OPCODE(G_BITCAST) 261 262 /// Generic load. 263 HANDLE_TARGET_OPCODE(G_LOAD) 264 265 /// Generic store. 266 HANDLE_TARGET_OPCODE(G_STORE) 267 268 /// Generic conditional branch instruction. 269 HANDLE_TARGET_OPCODE(G_BRCOND) 270 271 /// Generic indirect branch instruction. 272 HANDLE_TARGET_OPCODE(G_BRINDIRECT) 273 274 /// Generic intrinsic use (without side effects). 275 HANDLE_TARGET_OPCODE(G_INTRINSIC) 276 277 /// Generic intrinsic use (with side effects). 278 HANDLE_TARGET_OPCODE(G_INTRINSIC_W_SIDE_EFFECTS) 279 280 /// Generic extension allowing rubbish in high bits. 281 HANDLE_TARGET_OPCODE(G_ANYEXT) 282 283 /// Generic instruction to discard the high bits of a register. This differs 284 /// from (G_EXTRACT val, 0) on its action on vectors: G_TRUNC will truncate 285 /// each element individually, G_EXTRACT will typically discard the high 286 /// elements of the vector. 287 HANDLE_TARGET_OPCODE(G_TRUNC) 288 289 /// Generic integer constant. 290 HANDLE_TARGET_OPCODE(G_CONSTANT) 291 292 /// Generic floating constant. 293 HANDLE_TARGET_OPCODE(G_FCONSTANT) 294 295 /// Generic va_start instruction. Stores to its one pointer operand. 296 HANDLE_TARGET_OPCODE(G_VASTART) 297 298 /// Generic va_start instruction. Stores to its one pointer operand. 299 HANDLE_TARGET_OPCODE(G_VAARG) 300 301 // Generic sign extend 302 HANDLE_TARGET_OPCODE(G_SEXT) 303 304 // Generic zero extend 305 HANDLE_TARGET_OPCODE(G_ZEXT) 306 307 // Generic left-shift 308 HANDLE_TARGET_OPCODE(G_SHL) 309 310 // Generic logical right-shift 311 HANDLE_TARGET_OPCODE(G_LSHR) 312 313 // Generic arithmetic right-shift 314 HANDLE_TARGET_OPCODE(G_ASHR) 315 316 /// Generic integer-base comparison, also applicable to vectors of integers. 317 HANDLE_TARGET_OPCODE(G_ICMP) 318 319 /// Generic floating-point comparison, also applicable to vectors. 320 HANDLE_TARGET_OPCODE(G_FCMP) 321 322 /// Generic select. 323 HANDLE_TARGET_OPCODE(G_SELECT) 324 325 /// Generic unsigned add instruction, consuming the normal operands plus a carry 326 /// flag, and similarly producing the result and a carry flag. 327 HANDLE_TARGET_OPCODE(G_UADDE) 328 329 /// Generic unsigned subtract instruction, consuming the normal operands plus a 330 /// carry flag, and similarly producing the result and a carry flag. 331 HANDLE_TARGET_OPCODE(G_USUBE) 332 333 /// Generic signed add instruction, producing the result and a signed overflow 334 /// flag. 335 HANDLE_TARGET_OPCODE(G_SADDO) 336 337 /// Generic signed subtract instruction, producing the result and a signed 338 /// overflow flag. 339 HANDLE_TARGET_OPCODE(G_SSUBO) 340 341 /// Generic unsigned multiply instruction, producing the result and a signed 342 /// overflow flag. 343 HANDLE_TARGET_OPCODE(G_UMULO) 344 345 /// Generic signed multiply instruction, producing the result and a signed 346 /// overflow flag. 347 HANDLE_TARGET_OPCODE(G_SMULO) 348 349 // Multiply two numbers at twice the incoming bit width (unsigned) and return 350 // the high half of the result. 351 HANDLE_TARGET_OPCODE(G_UMULH) 352 353 // Multiply two numbers at twice the incoming bit width (signed) and return 354 // the high half of the result. 355 HANDLE_TARGET_OPCODE(G_SMULH) 356 357 /// Generic FP addition. 358 HANDLE_TARGET_OPCODE(G_FADD) 359 360 /// Generic FP subtraction. 361 HANDLE_TARGET_OPCODE(G_FSUB) 362 363 /// Generic FP multiplication. 364 HANDLE_TARGET_OPCODE(G_FMUL) 365 366 /// Generic FMA multiplication. Behaves like llvm fma intrinsic 367 HANDLE_TARGET_OPCODE(G_FMA) 368 369 /// Generic FP division. 370 HANDLE_TARGET_OPCODE(G_FDIV) 371 372 /// Generic FP remainder. 373 HANDLE_TARGET_OPCODE(G_FREM) 374 375 /// Generic FP exponentiation. 376 HANDLE_TARGET_OPCODE(G_FPOW) 377 378 /// Generic base-e exponential of a value. 379 HANDLE_TARGET_OPCODE(G_FEXP) 380 381 /// Generic base-2 exponential of a value. 382 HANDLE_TARGET_OPCODE(G_FEXP2) 383 384 /// Floating point base-e logarithm of a value. 385 HANDLE_TARGET_OPCODE(G_FLOG) 386 387 /// Floating point base-2 logarithm of a value. 388 HANDLE_TARGET_OPCODE(G_FLOG2) 389 390 /// Generic FP negation. 391 HANDLE_TARGET_OPCODE(G_FNEG) 392 393 /// Generic FP extension. 394 HANDLE_TARGET_OPCODE(G_FPEXT) 395 396 /// Generic float to signed-int conversion 397 HANDLE_TARGET_OPCODE(G_FPTRUNC) 398 399 /// Generic float to signed-int conversion 400 HANDLE_TARGET_OPCODE(G_FPTOSI) 401 402 /// Generic float to unsigned-int conversion 403 HANDLE_TARGET_OPCODE(G_FPTOUI) 404 405 /// Generic signed-int to float conversion 406 HANDLE_TARGET_OPCODE(G_SITOFP) 407 408 /// Generic unsigned-int to float conversion 409 HANDLE_TARGET_OPCODE(G_UITOFP) 410 411 /// Generic pointer offset 412 HANDLE_TARGET_OPCODE(G_GEP) 413 414 /// Clear the specified number of low bits in a pointer. This rounds the value 415 /// *down* to the given alignment. 416 HANDLE_TARGET_OPCODE(G_PTR_MASK) 417 418 /// Generic BRANCH instruction. This is an unconditional branch. 419 HANDLE_TARGET_OPCODE(G_BR) 420 421 /// Generic insertelement. 422 HANDLE_TARGET_OPCODE(G_INSERT_VECTOR_ELT) 423 424 /// Generic extractelement. 425 HANDLE_TARGET_OPCODE(G_EXTRACT_VECTOR_ELT) 426 427 /// Generic shufflevector. 428 HANDLE_TARGET_OPCODE(G_SHUFFLE_VECTOR) 429 430 /// Generic byte swap. 431 HANDLE_TARGET_OPCODE(G_BSWAP) 432 433 // TODO: Add more generic opcodes as we move along. 434 435 /// Marker for the end of the generic opcode. 436 /// This is used to check if an opcode is in the range of the 437 /// generic opcodes. 438 HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPCODE_END, G_BSWAP) 439 440 /// BUILTIN_OP_END - This must be the last enum value in this list. 441 /// The target-specific post-isel opcode values start here. 442 HANDLE_TARGET_OPCODE_MARKER(GENERIC_OP_END, PRE_ISEL_GENERIC_OPCODE_END) 443
