1 //===-- llvm/Target/TargetOpcodes.def - Target Indep Opcodes ------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the target independent instruction opcodes. 11 // 12 //===----------------------------------------------------------------------===// 13 14 // NOTE: NO INCLUDE GUARD DESIRED! 15 16 /// HANDLE_TARGET_OPCODE defines an opcode and its associated enum value. 17 /// 18 #ifndef HANDLE_TARGET_OPCODE 19 #define HANDLE_TARGET_OPCODE(OPC, NUM) 20 #endif 21 22 /// HANDLE_TARGET_OPCODE_MARKER defines an alternative identifier for an opcode. 23 /// 24 #ifndef HANDLE_TARGET_OPCODE_MARKER 25 #define HANDLE_TARGET_OPCODE_MARKER(IDENT, OPC) 26 #endif 27 28 /// Every instruction defined here must also appear in Target.td. 29 /// 30 HANDLE_TARGET_OPCODE(PHI) 31 HANDLE_TARGET_OPCODE(INLINEASM) 32 HANDLE_TARGET_OPCODE(CFI_INSTRUCTION) 33 HANDLE_TARGET_OPCODE(EH_LABEL) 34 HANDLE_TARGET_OPCODE(GC_LABEL) 35 36 /// KILL - This instruction is a noop that is used only to adjust the 37 /// liveness of registers. This can be useful when dealing with 38 /// sub-registers. 39 HANDLE_TARGET_OPCODE(KILL) 40 41 /// EXTRACT_SUBREG - This instruction takes two operands: a register 42 /// that has subregisters, and a subregister index. It returns the 43 /// extracted subregister value. This is commonly used to implement 44 /// truncation operations on target architectures which support it. 45 HANDLE_TARGET_OPCODE(EXTRACT_SUBREG) 46 47 /// INSERT_SUBREG - This instruction takes three operands: a register that 48 /// has subregisters, a register providing an insert value, and a 49 /// subregister index. It returns the value of the first register with the 50 /// value of the second register inserted. The first register is often 51 /// defined by an IMPLICIT_DEF, because it is commonly used to implement 52 /// anyext operations on target architectures which support it. 53 HANDLE_TARGET_OPCODE(INSERT_SUBREG) 54 55 /// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef. 56 HANDLE_TARGET_OPCODE(IMPLICIT_DEF) 57 58 /// SUBREG_TO_REG - Assert the value of bits in a super register. 59 /// The result of this instruction is the value of the second operand inserted 60 /// into the subregister specified by the third operand. All other bits are 61 /// assumed to be equal to the bits in the immediate integer constant in the 62 /// first operand. This instruction just communicates information; No code 63 /// should be generated. 64 /// This is typically used after an instruction where the write to a subregister 65 /// implicitly cleared the bits in the super registers. 66 HANDLE_TARGET_OPCODE(SUBREG_TO_REG) 67 68 /// COPY_TO_REGCLASS - This instruction is a placeholder for a plain 69 /// register-to-register copy into a specific register class. This is only 70 /// used between instruction selection and MachineInstr creation, before 71 /// virtual registers have been created for all the instructions, and it's 72 /// only needed in cases where the register classes implied by the 73 /// instructions are insufficient. It is emitted as a COPY MachineInstr. 74 HANDLE_TARGET_OPCODE(COPY_TO_REGCLASS) 75 76 /// DBG_VALUE - a mapping of the llvm.dbg.value intrinsic 77 HANDLE_TARGET_OPCODE(DBG_VALUE) 78 79 /// REG_SEQUENCE - This variadic instruction is used to form a register that 80 /// represents a consecutive sequence of sub-registers. It's used as a 81 /// register coalescing / allocation aid and must be eliminated before code 82 /// emission. 83 // In SDNode form, the first operand encodes the register class created by 84 // the REG_SEQUENCE, while each subsequent pair names a vreg + subreg index 85 // pair. Once it has been lowered to a MachineInstr, the regclass operand 86 // is no longer present. 87 /// e.g. v1027 = REG_SEQUENCE v1024, 3, v1025, 4, v1026, 5 88 /// After register coalescing references of v1024 should be replace with 89 /// v1027:3, v1025 with v1027:4, etc. 90 HANDLE_TARGET_OPCODE(REG_SEQUENCE) 91 92 /// COPY - Target-independent register copy. This instruction can also be 93 /// used to copy between subregisters of virtual registers. 94 HANDLE_TARGET_OPCODE(COPY) 95 96 /// BUNDLE - This instruction represents an instruction bundle. Instructions 97 /// which immediately follow a BUNDLE instruction which are marked with 98 /// 'InsideBundle' flag are inside the bundle. 99 HANDLE_TARGET_OPCODE(BUNDLE) 100 101 /// Lifetime markers. 102 HANDLE_TARGET_OPCODE(LIFETIME_START) 103 HANDLE_TARGET_OPCODE(LIFETIME_END) 104 105 /// A Stackmap instruction captures the location of live variables at its 106 /// position in the instruction stream. It is followed by a shadow of bytes 107 /// that must lie within the function and not contain another stackmap. 108 HANDLE_TARGET_OPCODE(STACKMAP) 109 110 /// FEntry all - This is a marker instruction which gets translated into a raw fentry call. 111 HANDLE_TARGET_OPCODE(FENTRY_CALL) 112 113 /// Patchable call instruction - this instruction represents a call to a 114 /// constant address, followed by a series of NOPs. It is intended to 115 /// support optimizations for dynamic languages (such as javascript) that 116 /// rewrite calls to runtimes with more efficient code sequences. 117 /// This also implies a stack map. 118 HANDLE_TARGET_OPCODE(PATCHPOINT) 119 120 /// This pseudo-instruction loads the stack guard value. Targets which need 121 /// to prevent the stack guard value or address from being spilled to the 122 /// stack should override TargetLowering::emitLoadStackGuardNode and 123 /// additionally expand this pseudo after register allocation. 124 HANDLE_TARGET_OPCODE(LOAD_STACK_GUARD) 125 126 /// Call instruction with associated vm state for deoptimization and list 127 /// of live pointers for relocation by the garbage collector. It is 128 /// intended to support garbage collection with fully precise relocating 129 /// collectors and deoptimizations in either the callee or caller. 130 HANDLE_TARGET_OPCODE(STATEPOINT) 131 132 /// Instruction that records the offset of a local stack allocation passed to 133 /// llvm.localescape. It has two arguments: the symbol for the label and the 134 /// frame index of the local stack allocation. 135 HANDLE_TARGET_OPCODE(LOCAL_ESCAPE) 136 137 /// Wraps a machine instruction which can fault, bundled with associated 138 /// information on how to handle such a fault. 139 /// For example loading instruction that may page fault, bundled with associated 140 /// information on how to handle such a page fault. It is intended to support 141 /// "zero cost" null checks in managed languages by allowing LLVM to fold 142 /// comparisons into existing memory operations. 143 HANDLE_TARGET_OPCODE(FAULTING_OP) 144 145 /// Wraps a machine instruction to add patchability constraints. An 146 /// instruction wrapped in PATCHABLE_OP has to either have a minimum 147 /// size or be preceded with a nop of that size. The first operand is 148 /// an immediate denoting the minimum size of the instruction, the 149 /// second operand is an immediate denoting the opcode of the original 150 /// instruction. The rest of the operands are the operands of the 151 /// original instruction. 152 HANDLE_TARGET_OPCODE(PATCHABLE_OP) 153 154 /// This is a marker instruction which gets translated into a nop sled, useful 155 /// for inserting instrumentation instructions at runtime. 156 HANDLE_TARGET_OPCODE(PATCHABLE_FUNCTION_ENTER) 157 158 /// Wraps a return instruction and its operands to enable adding nop sleds 159 /// either before or after the return. The nop sleds are useful for inserting 160 /// instrumentation instructions at runtime. 161 /// The patch here replaces the return instruction. 162 HANDLE_TARGET_OPCODE(PATCHABLE_RET) 163 164 /// This is a marker instruction which gets translated into a nop sled, useful 165 /// for inserting instrumentation instructions at runtime. 166 /// The patch here prepends the return instruction. 167 /// The same thing as in x86_64 is not possible for ARM because it has multiple 168 /// return instructions. Furthermore, CPU allows parametrized and even 169 /// conditional return instructions. In the current ARM implementation we are 170 /// making use of the fact that currently LLVM doesn't seem to generate 171 /// conditional return instructions. 172 /// On ARM, the same instruction can be used for popping multiple registers 173 /// from the stack and returning (it just pops pc register too), and LLVM 174 /// generates it sometimes. So we can't insert the sled between this stack 175 /// adjustment and the return without splitting the original instruction into 2 176 /// instructions. So on ARM, rather than jumping into the exit trampoline, we 177 /// call it, it does the tracing, preserves the stack and returns. 178 HANDLE_TARGET_OPCODE(PATCHABLE_FUNCTION_EXIT) 179 180 /// Wraps a tail call instruction and its operands to enable adding nop sleds 181 /// either before or after the tail exit. We use this as a disambiguation from 182 /// PATCHABLE_RET which specifically only works for return instructions. 183 HANDLE_TARGET_OPCODE(PATCHABLE_TAIL_CALL) 184 185 /// The following generic opcodes are not supposed to appear after ISel. 186 /// This is something we might want to relax, but for now, this is convenient 187 /// to produce diagnostics. 188 189 /// Generic ADD instruction. This is an integer add. 190 HANDLE_TARGET_OPCODE(G_ADD) 191 HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPCODE_START, G_ADD) 192 193 /// Generic SUB instruction. This is an integer sub. 194 HANDLE_TARGET_OPCODE(G_SUB) 195 196 // Generic multiply instruction. 197 HANDLE_TARGET_OPCODE(G_MUL) 198 199 // Generic signed division instruction. 200 HANDLE_TARGET_OPCODE(G_SDIV) 201 202 // Generic unsigned division instruction. 203 HANDLE_TARGET_OPCODE(G_UDIV) 204 205 // Generic signed remainder instruction. 206 HANDLE_TARGET_OPCODE(G_SREM) 207 208 // Generic unsigned remainder instruction. 209 HANDLE_TARGET_OPCODE(G_UREM) 210 211 /// Generic bitwise and instruction. 212 HANDLE_TARGET_OPCODE(G_AND) 213 214 /// Generic bitwise or instruction. 215 HANDLE_TARGET_OPCODE(G_OR) 216 217 /// Generic bitwise exclusive-or instruction. 218 HANDLE_TARGET_OPCODE(G_XOR) 219 220 221 /// Generic instruction to materialize the address of an alloca or other 222 /// stack-based object. 223 HANDLE_TARGET_OPCODE(G_FRAME_INDEX) 224 225 /// Generic reference to global value. 226 HANDLE_TARGET_OPCODE(G_GLOBAL_VALUE) 227 228 /// Generic instruction to extract blocks of bits from the register given 229 /// (typically a sub-register COPY after instruction selection). 230 HANDLE_TARGET_OPCODE(G_EXTRACT) 231 232 HANDLE_TARGET_OPCODE(G_UNMERGE_VALUES) 233 234 /// Generic instruction to insert blocks of bits from the registers given into 235 /// the source. 236 HANDLE_TARGET_OPCODE(G_INSERT) 237 238 /// Generic instruction to paste a variable number of components together into a 239 /// larger register. 240 HANDLE_TARGET_OPCODE(G_SEQUENCE) 241 242 HANDLE_TARGET_OPCODE(G_MERGE_VALUES) 243 244 /// Generic pointer to int conversion. 245 HANDLE_TARGET_OPCODE(G_PTRTOINT) 246 247 /// Generic int to pointer conversion. 248 HANDLE_TARGET_OPCODE(G_INTTOPTR) 249 250 /// Generic bitcast. The source and destination types must be different, or a 251 /// COPY is the relevant instruction. 252 HANDLE_TARGET_OPCODE(G_BITCAST) 253 254 /// Generic load. 255 HANDLE_TARGET_OPCODE(G_LOAD) 256 257 /// Generic store. 258 HANDLE_TARGET_OPCODE(G_STORE) 259 260 /// Generic conditional branch instruction. 261 HANDLE_TARGET_OPCODE(G_BRCOND) 262 263 /// Generic indirect branch instruction. 264 HANDLE_TARGET_OPCODE(G_BRINDIRECT) 265 266 /// Generic intrinsic use (without side effects). 267 HANDLE_TARGET_OPCODE(G_INTRINSIC) 268 269 /// Generic intrinsic use (with side effects). 270 HANDLE_TARGET_OPCODE(G_INTRINSIC_W_SIDE_EFFECTS) 271 272 /// Generic extension allowing rubbish in high bits. 273 HANDLE_TARGET_OPCODE(G_ANYEXT) 274 275 /// Generic instruction to discard the high bits of a register. This differs 276 /// from (G_EXTRACT val, 0) on its action on vectors: G_TRUNC will truncate 277 /// each element individually, G_EXTRACT will typically discard the high 278 /// elements of the vector. 279 HANDLE_TARGET_OPCODE(G_TRUNC) 280 281 /// Generic integer constant. 282 HANDLE_TARGET_OPCODE(G_CONSTANT) 283 284 /// Generic floating constant. 285 HANDLE_TARGET_OPCODE(G_FCONSTANT) 286 287 /// Generic va_start instruction. Stores to its one pointer operand. 288 HANDLE_TARGET_OPCODE(G_VASTART) 289 290 /// Generic va_start instruction. Stores to its one pointer operand. 291 HANDLE_TARGET_OPCODE(G_VAARG) 292 293 // Generic sign extend 294 HANDLE_TARGET_OPCODE(G_SEXT) 295 296 // Generic zero extend 297 HANDLE_TARGET_OPCODE(G_ZEXT) 298 299 // Generic left-shift 300 HANDLE_TARGET_OPCODE(G_SHL) 301 302 // Generic logical right-shift 303 HANDLE_TARGET_OPCODE(G_LSHR) 304 305 // Generic arithmetic right-shift 306 HANDLE_TARGET_OPCODE(G_ASHR) 307 308 /// Generic integer-base comparison, also applicable to vectors of integers. 309 HANDLE_TARGET_OPCODE(G_ICMP) 310 311 /// Generic floating-point comparison, also applicable to vectors. 312 HANDLE_TARGET_OPCODE(G_FCMP) 313 314 /// Generic select. 315 HANDLE_TARGET_OPCODE(G_SELECT) 316 317 /// Generic unsigned add instruction, consuming the normal operands plus a carry 318 /// flag, and similarly producing the result and a carry flag. 319 HANDLE_TARGET_OPCODE(G_UADDE) 320 321 /// Generic unsigned subtract instruction, consuming the normal operands plus a 322 /// carry flag, and similarly producing the result and a carry flag. 323 HANDLE_TARGET_OPCODE(G_USUBE) 324 325 /// Generic signed add instruction, producing the result and a signed overflow 326 /// flag. 327 HANDLE_TARGET_OPCODE(G_SADDO) 328 329 /// Generic signed subtract instruction, producing the result and a signed 330 /// overflow flag. 331 HANDLE_TARGET_OPCODE(G_SSUBO) 332 333 /// Generic unsigned multiply instruction, producing the result and a signed 334 /// overflow flag. 335 HANDLE_TARGET_OPCODE(G_UMULO) 336 337 /// Generic signed multiply instruction, producing the result and a signed 338 /// overflow flag. 339 HANDLE_TARGET_OPCODE(G_SMULO) 340 341 // Multiply two numbers at twice the incoming bit width (unsigned) and return 342 // the high half of the result. 343 HANDLE_TARGET_OPCODE(G_UMULH) 344 345 // Multiply two numbers at twice the incoming bit width (signed) and return 346 // the high half of the result. 347 HANDLE_TARGET_OPCODE(G_SMULH) 348 349 /// Generic FP addition. 350 HANDLE_TARGET_OPCODE(G_FADD) 351 352 /// Generic FP subtraction. 353 HANDLE_TARGET_OPCODE(G_FSUB) 354 355 /// Generic FP multiplication. 356 HANDLE_TARGET_OPCODE(G_FMUL) 357 358 /// Generic FP division. 359 HANDLE_TARGET_OPCODE(G_FDIV) 360 361 /// Generic FP remainder. 362 HANDLE_TARGET_OPCODE(G_FREM) 363 364 /// Generic FP exponentiation. 365 HANDLE_TARGET_OPCODE(G_FPOW) 366 367 /// Generic FP negation. 368 HANDLE_TARGET_OPCODE(G_FNEG) 369 370 /// Generic FP extension. 371 HANDLE_TARGET_OPCODE(G_FPEXT) 372 373 /// Generic float to signed-int conversion 374 HANDLE_TARGET_OPCODE(G_FPTRUNC) 375 376 /// Generic float to signed-int conversion 377 HANDLE_TARGET_OPCODE(G_FPTOSI) 378 379 /// Generic float to unsigned-int conversion 380 HANDLE_TARGET_OPCODE(G_FPTOUI) 381 382 /// Generic signed-int to float conversion 383 HANDLE_TARGET_OPCODE(G_SITOFP) 384 385 /// Generic unsigned-int to float conversion 386 HANDLE_TARGET_OPCODE(G_UITOFP) 387 388 /// Generic pointer offset 389 HANDLE_TARGET_OPCODE(G_GEP) 390 391 /// Clear the specified number of low bits in a pointer. This rounds the value 392 /// *down* to the given alignment. 393 HANDLE_TARGET_OPCODE(G_PTR_MASK) 394 395 /// Generic BRANCH instruction. This is an unconditional branch. 396 HANDLE_TARGET_OPCODE(G_BR) 397 398 /// Generic insertelement. 399 HANDLE_TARGET_OPCODE(G_INSERT_VECTOR_ELT) 400 401 /// Generic extractelement. 402 HANDLE_TARGET_OPCODE(G_EXTRACT_VECTOR_ELT) 403 404 /// Generic shufflevector. 405 HANDLE_TARGET_OPCODE(G_SHUFFLE_VECTOR) 406 407 // TODO: Add more generic opcodes as we move along. 408 409 /// Marker for the end of the generic opcode. 410 /// This is used to check if an opcode is in the range of the 411 /// generic opcodes. 412 HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPCODE_END, G_SHUFFLE_VECTOR) 413 414 /// BUILTIN_OP_END - This must be the last enum value in this list. 415 /// The target-specific post-isel opcode values start here. 416 HANDLE_TARGET_OPCODE_MARKER(GENERIC_OP_END, PRE_ISEL_GENERIC_OPCODE_END) 417
