1 //==-- llvm/Target/TargetSubtargetInfo.h - Target Information ----*- C++ -*-==// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes the subtarget options of a Target machine. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_TARGET_TARGETSUBTARGETINFO_H 15 #define LLVM_TARGET_TARGETSUBTARGETINFO_H 16 17 #include "llvm/ADT/ArrayRef.h" 18 #include "llvm/ADT/SmallVector.h" 19 #include "llvm/ADT/StringRef.h" 20 #include "llvm/CodeGen/PBQPRAConstraint.h" 21 #include "llvm/CodeGen/ScheduleDAGMutation.h" 22 #include "llvm/CodeGen/SchedulerRegistry.h" 23 #include "llvm/MC/MCInst.h" 24 #include "llvm/MC/MCSubtargetInfo.h" 25 #include "llvm/Support/CodeGen.h" 26 #include <memory> 27 #include <vector> 28 29 namespace llvm { 30 31 class CallLowering; 32 class InstructionSelector; 33 class LegalizerInfo; 34 class MachineInstr; 35 class RegisterBankInfo; 36 class SDep; 37 class SelectionDAGTargetInfo; 38 class SUnit; 39 class TargetFrameLowering; 40 class TargetInstrInfo; 41 class TargetLowering; 42 class TargetRegisterClass; 43 class TargetRegisterInfo; 44 class TargetSchedModel; 45 struct MachineSchedPolicy; 46 47 //===----------------------------------------------------------------------===// 48 /// 49 /// TargetSubtargetInfo - Generic base class for all target subtargets. All 50 /// Target-specific options that control code generation and printing should 51 /// be exposed through a TargetSubtargetInfo-derived class. 52 /// 53 class TargetSubtargetInfo : public MCSubtargetInfo { 54 protected: // Can only create subclasses... 55 TargetSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS, 56 ArrayRef<SubtargetFeatureKV> PF, 57 ArrayRef<SubtargetFeatureKV> PD, 58 const SubtargetInfoKV *ProcSched, 59 const MCWriteProcResEntry *WPR, 60 const MCWriteLatencyEntry *WL, 61 const MCReadAdvanceEntry *RA, const InstrStage *IS, 62 const unsigned *OC, const unsigned *FP); 63 64 public: 65 // AntiDepBreakMode - Type of anti-dependence breaking that should 66 // be performed before post-RA scheduling. 67 typedef enum { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL } AntiDepBreakMode; 68 typedef SmallVectorImpl<const TargetRegisterClass *> RegClassVector; 69 70 TargetSubtargetInfo() = delete; 71 TargetSubtargetInfo(const TargetSubtargetInfo &) = delete; 72 void operator=(const TargetSubtargetInfo &) = delete; 73 virtual ~TargetSubtargetInfo(); 74 75 virtual bool isXRaySupported() const { return false; } 76 77 // Interfaces to the major aspects of target machine information: 78 // 79 // -- Instruction opcode and operand information 80 // -- Pipelines and scheduling information 81 // -- Stack frame information 82 // -- Selection DAG lowering information 83 // -- Call lowering information 84 // 85 // N.B. These objects may change during compilation. It's not safe to cache 86 // them between functions. 87 virtual const TargetInstrInfo *getInstrInfo() const { return nullptr; } 88 virtual const TargetFrameLowering *getFrameLowering() const { 89 return nullptr; 90 } 91 virtual const TargetLowering *getTargetLowering() const { return nullptr; } 92 virtual const SelectionDAGTargetInfo *getSelectionDAGInfo() const { 93 return nullptr; 94 } 95 virtual const CallLowering *getCallLowering() const { return nullptr; } 96 97 // FIXME: This lets targets specialize the selector by subtarget (which lets 98 // us do things like a dedicated avx512 selector). However, we might want 99 // to also specialize selectors by MachineFunction, which would let us be 100 // aware of optsize/optnone and such. 101 virtual const InstructionSelector *getInstructionSelector() const { 102 return nullptr; 103 } 104 105 /// Target can subclass this hook to select a different DAG scheduler. 106 virtual RegisterScheduler::FunctionPassCtor 107 getDAGScheduler(CodeGenOpt::Level) const { 108 return nullptr; 109 } 110 111 virtual const LegalizerInfo *getLegalizerInfo() const { return nullptr; } 112 113 /// getRegisterInfo - If register information is available, return it. If 114 /// not, return null. 115 /// 116 virtual const TargetRegisterInfo *getRegisterInfo() const { return nullptr; } 117 118 /// If the information for the register banks is available, return it. 119 /// Otherwise return nullptr. 120 virtual const RegisterBankInfo *getRegBankInfo() const { return nullptr; } 121 122 /// getInstrItineraryData - Returns instruction itinerary data for the target 123 /// or specific subtarget. 124 /// 125 virtual const InstrItineraryData *getInstrItineraryData() const { 126 return nullptr; 127 } 128 129 /// Resolve a SchedClass at runtime, where SchedClass identifies an 130 /// MCSchedClassDesc with the isVariant property. This may return the ID of 131 /// another variant SchedClass, but repeated invocation must quickly terminate 132 /// in a nonvariant SchedClass. 133 virtual unsigned resolveSchedClass(unsigned SchedClass, 134 const MachineInstr *MI, 135 const TargetSchedModel *SchedModel) const { 136 return 0; 137 } 138 139 /// \brief True if the subtarget should run MachineScheduler after aggressive 140 /// coalescing. 141 /// 142 /// This currently replaces the SelectionDAG scheduler with the "source" order 143 /// scheduler (though see below for an option to turn this off and use the 144 /// TargetLowering preference). It does not yet disable the postRA scheduler. 145 virtual bool enableMachineScheduler() const; 146 147 /// \brief Support printing of [latency:throughput] comment in output .S file. 148 virtual bool supportPrintSchedInfo() const { return false; } 149 150 /// \brief True if the machine scheduler should disable the TLI preference 151 /// for preRA scheduling with the source level scheduler. 152 virtual bool enableMachineSchedDefaultSched() const { return true; } 153 154 /// \brief True if the subtarget should enable joining global copies. 155 /// 156 /// By default this is enabled if the machine scheduler is enabled, but 157 /// can be overridden. 158 virtual bool enableJoinGlobalCopies() const; 159 160 /// True if the subtarget should run a scheduler after register allocation. 161 /// 162 /// By default this queries the PostRAScheduling bit in the scheduling model 163 /// which is the preferred way to influence this. 164 virtual bool enablePostRAScheduler() const; 165 166 /// \brief True if the subtarget should run the atomic expansion pass. 167 virtual bool enableAtomicExpand() const; 168 169 /// \brief Override generic scheduling policy within a region. 170 /// 171 /// This is a convenient way for targets that don't provide any custom 172 /// scheduling heuristics (no custom MachineSchedStrategy) to make 173 /// changes to the generic scheduling policy. 174 virtual void overrideSchedPolicy(MachineSchedPolicy &Policy, 175 unsigned NumRegionInstrs) const {} 176 177 // \brief Perform target specific adjustments to the latency of a schedule 178 // dependency. 179 virtual void adjustSchedDependency(SUnit *def, SUnit *use, SDep &dep) const {} 180 181 // For use with PostRAScheduling: get the anti-dependence breaking that should 182 // be performed before post-RA scheduling. 183 virtual AntiDepBreakMode getAntiDepBreakMode() const { return ANTIDEP_NONE; } 184 185 // For use with PostRAScheduling: in CriticalPathRCs, return any register 186 // classes that should only be considered for anti-dependence breaking if they 187 // are on the critical path. 188 virtual void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const { 189 return CriticalPathRCs.clear(); 190 } 191 192 // \brief Provide an ordered list of schedule DAG mutations for the post-RA 193 // scheduler. 194 virtual void getPostRAMutations( 195 std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const { 196 } 197 198 // \brief Provide an ordered list of schedule DAG mutations for the machine 199 // pipeliner. 200 virtual void getSMSMutations( 201 std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const { 202 } 203 204 // For use with PostRAScheduling: get the minimum optimization level needed 205 // to enable post-RA scheduling. 206 virtual CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const { 207 return CodeGenOpt::Default; 208 } 209 210 /// \brief True if the subtarget should run the local reassignment 211 /// heuristic of the register allocator. 212 /// This heuristic may be compile time intensive, \p OptLevel provides 213 /// a finer grain to tune the register allocator. 214 virtual bool enableRALocalReassignment(CodeGenOpt::Level OptLevel) const; 215 216 /// \brief Enable use of alias analysis during code generation (during MI 217 /// scheduling, DAGCombine, etc.). 218 virtual bool useAA() const; 219 220 /// \brief Enable the use of the early if conversion pass. 221 virtual bool enableEarlyIfConversion() const { return false; } 222 223 /// \brief Return PBQPConstraint(s) for the target. 224 /// 225 /// Override to provide custom PBQP constraints. 226 virtual std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const { 227 return nullptr; 228 } 229 230 /// Enable tracking of subregister liveness in register allocator. 231 /// Please use MachineRegisterInfo::subRegLivenessEnabled() instead where 232 /// possible. 233 virtual bool enableSubRegLiveness() const { return false; } 234 235 /// Returns string representation of scheduler comment 236 std::string getSchedInfoStr(const MachineInstr &MI) const override; 237 std::string getSchedInfoStr(MCInst const &MCI) const override; 238 }; 239 240 } // end namespace llvm 241 242 #endif // LLVM_TARGET_TARGETSUBTARGETINFO_H 243
