1 #ifndef _ASM_X86_MCE_H 2 #define _ASM_X86_MCE_H 3 4 #include <linux/types.h> 5 #include <asm/ioctls.h> 6 7 /* 8 * Machine Check support for x86 9 */ 10 11 /* MCG_CAP register defines */ 12 #define MCG_BANKCNT_MASK 0xff /* Number of Banks */ 13 #define MCG_CTL_P (1ULL<<8) /* MCG_CTL register available */ 14 #define MCG_EXT_P (1ULL<<9) /* Extended registers available */ 15 #define MCG_CMCI_P (1ULL<<10) /* CMCI supported */ 16 #define MCG_EXT_CNT_MASK 0xff0000 /* Number of Extended registers */ 17 #define MCG_EXT_CNT_SHIFT 16 18 #define MCG_EXT_CNT(c) (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT) 19 #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */ 20 21 /* MCG_STATUS register defines */ 22 #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */ 23 #define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */ 24 #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */ 25 26 /* MCi_STATUS register defines */ 27 #define MCI_STATUS_VAL (1ULL<<63) /* valid error */ 28 #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */ 29 #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */ 30 #define MCI_STATUS_EN (1ULL<<60) /* error enabled */ 31 #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */ 32 #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */ 33 #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */ 34 #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */ 35 #define MCI_STATUS_AR (1ULL<<55) /* Action required */ 36 37 /* MCi_MISC register defines */ 38 #define MCI_MISC_ADDR_LSB(m) ((m) & 0x3f) 39 #define MCI_MISC_ADDR_MODE(m) (((m) >> 6) & 7) 40 #define MCI_MISC_ADDR_SEGOFF 0 /* segment offset */ 41 #define MCI_MISC_ADDR_LINEAR 1 /* linear address */ 42 #define MCI_MISC_ADDR_PHYS 2 /* physical address */ 43 #define MCI_MISC_ADDR_MEM 3 /* memory address */ 44 #define MCI_MISC_ADDR_GENERIC 7 /* generic */ 45 46 /* CTL2 register defines */ 47 #define MCI_CTL2_CMCI_EN (1ULL << 30) 48 #define MCI_CTL2_CMCI_THRESHOLD_MASK 0x7fffULL 49 50 #define MCJ_CTX_MASK 3 51 #define MCJ_CTX(flags) ((flags) & MCJ_CTX_MASK) 52 #define MCJ_CTX_RANDOM 0 /* inject context: random */ 53 #define MCJ_CTX_PROCESS 1 /* inject context: process */ 54 #define MCJ_CTX_IRQ 2 /* inject context: IRQ */ 55 #define MCJ_NMI_BROADCAST 4 /* do NMI broadcasting */ 56 #define MCJ_EXCEPTION 8 /* raise as exception */ 57 58 /* Fields are zero when not available */ 59 struct mce { 60 __u64 status; 61 __u64 misc; 62 __u64 addr; 63 __u64 mcgstatus; 64 __u64 ip; 65 __u64 tsc; /* cpu time stamp counter */ 66 __u64 time; /* wall time_t when error was detected */ 67 __u8 cpuvendor; /* cpu vendor as encoded in system.h */ 68 __u8 inject_flags; /* software inject flags */ 69 __u16 pad; 70 __u32 cpuid; /* CPUID 1 EAX */ 71 __u8 cs; /* code segment */ 72 __u8 bank; /* machine check bank */ 73 __u8 cpu; /* cpu number; obsolete; use extcpu now */ 74 __u8 finished; /* entry is valid */ 75 __u32 extcpu; /* linux cpu number that detected the error */ 76 __u32 socketid; /* CPU socket ID */ 77 __u32 apicid; /* CPU initial apic ID */ 78 __u64 mcgcap; /* MCGCAP MSR: machine check capabilities of CPU */ 79 __u64 aux0; /* model specific */ 80 __u64 aux1; /* model specific */ 81 }; 82 83 /* 84 * This structure contains all data related to the MCE log. Also 85 * carries a signature to make it easier to find from external 86 * debugging tools. Each entry is only valid when its finished flag 87 * is set. 88 */ 89 90 #define MCE_LOG_LEN 32 91 92 struct mce_log { 93 char signature[12]; /* "MACHINECHECK" */ 94 unsigned len; /* = MCE_LOG_LEN */ 95 unsigned next; 96 unsigned flags; 97 unsigned recordlen; /* length of struct mce */ 98 struct mce entry[MCE_LOG_LEN]; 99 }; 100 101 #define MCE_OVERFLOW 0 /* bit 0 in flags means overflow */ 102 103 #define MCE_LOG_SIGNATURE "MACHINECHECK" 104 105 #define MCE_GET_RECORD_LEN _IOR('M', 1, int) 106 #define MCE_GET_LOG_LEN _IOR('M', 2, int) 107 #define MCE_GETCLEAR_FLAGS _IOR('M', 3, int) 108 109 /* Software defined banks */ 110 #define MCE_EXTENDED_BANK 128 111 #define MCE_THERMAL_BANK MCE_EXTENDED_BANK + 0 112 113 #define K8_MCE_THRESHOLD_BASE (MCE_EXTENDED_BANK + 1) /* MCE_AMD */ 114 #define K8_MCE_THRESHOLD_BANK_0 (MCE_THRESHOLD_BASE + 0 * 9) 115 #define K8_MCE_THRESHOLD_BANK_1 (MCE_THRESHOLD_BASE + 1 * 9) 116 #define K8_MCE_THRESHOLD_BANK_2 (MCE_THRESHOLD_BASE + 2 * 9) 117 #define K8_MCE_THRESHOLD_BANK_3 (MCE_THRESHOLD_BASE + 3 * 9) 118 #define K8_MCE_THRESHOLD_BANK_4 (MCE_THRESHOLD_BASE + 4 * 9) 119 #define K8_MCE_THRESHOLD_BANK_5 (MCE_THRESHOLD_BASE + 5 * 9) 120 #define K8_MCE_THRESHOLD_DRAM_ECC (MCE_THRESHOLD_BANK_4 + 0) 121 122 123 #endif /* _ASM_X86_MCE_H */ 124
