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      1 /* Copyright (C) 2003-2014 Free Software Foundation, Inc.
      2 
      3    This file is part of GCC.
      4 
      5    GCC is free software; you can redistribute it and/or modify
      6    it under the terms of the GNU General Public License as published by
      7    the Free Software Foundation; either version 3, or (at your option)
      8    any later version.
      9 
     10    GCC is distributed in the hope that it will be useful,
     11    but WITHOUT ANY WARRANTY; without even the implied warranty of
     12    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     13    GNU General Public License for more details.
     14 
     15    Under Section 7 of GPL version 3, you are granted additional
     16    permissions described in the GCC Runtime Library Exception, version
     17    3.1, as published by the Free Software Foundation.
     18 
     19    You should have received a copy of the GNU General Public License and
     20    a copy of the GCC Runtime Library Exception along with this program;
     21    see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
     22    <http://www.gnu.org/licenses/>.  */
     23 
     24 /* Implemented from the specification included in the Intel C++ Compiler
     25    User Guide and Reference, version 9.0.  */
     26 
     27 #ifndef _PMMINTRIN_H_INCLUDED
     28 #define _PMMINTRIN_H_INCLUDED
     29 
     30 /* We need definitions from the SSE2 and SSE header files*/
     31 #include <emmintrin.h>
     32 
     33 #ifndef __SSE3__
     34 #pragma GCC push_options
     35 #pragma GCC target("sse3")
     36 #define __DISABLE_SSE3__
     37 #endif /* __SSE3__ */
     38 
     39 /* Additional bits in the MXCSR.  */
     40 #define _MM_DENORMALS_ZERO_MASK		0x0040
     41 #define _MM_DENORMALS_ZERO_ON		0x0040
     42 #define _MM_DENORMALS_ZERO_OFF		0x0000
     43 
     44 #define _MM_SET_DENORMALS_ZERO_MODE(mode) \
     45   _mm_setcsr ((_mm_getcsr () & ~_MM_DENORMALS_ZERO_MASK) | (mode))
     46 #define _MM_GET_DENORMALS_ZERO_MODE() \
     47   (_mm_getcsr() & _MM_DENORMALS_ZERO_MASK)
     48 
     49 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
     50 _mm_addsub_ps (__m128 __X, __m128 __Y)
     51 {
     52   return (__m128) __builtin_ia32_addsubps ((__v4sf)__X, (__v4sf)__Y);
     53 }
     54 
     55 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
     56 _mm_hadd_ps (__m128 __X, __m128 __Y)
     57 {
     58   return (__m128) __builtin_ia32_haddps ((__v4sf)__X, (__v4sf)__Y);
     59 }
     60 
     61 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
     62 _mm_hsub_ps (__m128 __X, __m128 __Y)
     63 {
     64   return (__m128) __builtin_ia32_hsubps ((__v4sf)__X, (__v4sf)__Y);
     65 }
     66 
     67 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
     68 _mm_movehdup_ps (__m128 __X)
     69 {
     70   return (__m128) __builtin_ia32_movshdup ((__v4sf)__X);
     71 }
     72 
     73 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
     74 _mm_moveldup_ps (__m128 __X)
     75 {
     76   return (__m128) __builtin_ia32_movsldup ((__v4sf)__X);
     77 }
     78 
     79 extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
     80 _mm_addsub_pd (__m128d __X, __m128d __Y)
     81 {
     82   return (__m128d) __builtin_ia32_addsubpd ((__v2df)__X, (__v2df)__Y);
     83 }
     84 
     85 extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
     86 _mm_hadd_pd (__m128d __X, __m128d __Y)
     87 {
     88   return (__m128d) __builtin_ia32_haddpd ((__v2df)__X, (__v2df)__Y);
     89 }
     90 
     91 extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
     92 _mm_hsub_pd (__m128d __X, __m128d __Y)
     93 {
     94   return (__m128d) __builtin_ia32_hsubpd ((__v2df)__X, (__v2df)__Y);
     95 }
     96 
     97 extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
     98 _mm_loaddup_pd (double const *__P)
     99 {
    100   return _mm_load1_pd (__P);
    101 }
    102 
    103 extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
    104 _mm_movedup_pd (__m128d __X)
    105 {
    106   return _mm_shuffle_pd (__X, __X, _MM_SHUFFLE2 (0,0));
    107 }
    108 
    109 extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
    110 _mm_lddqu_si128 (__m128i const *__P)
    111 {
    112   return (__m128i) __builtin_ia32_lddqu ((char const *)__P);
    113 }
    114 
    115 extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__))
    116 _mm_monitor (void const * __P, unsigned int __E, unsigned int __H)
    117 {
    118   __builtin_ia32_monitor (__P, __E, __H);
    119 }
    120 
    121 extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__))
    122 _mm_mwait (unsigned int __E, unsigned int __H)
    123 {
    124   __builtin_ia32_mwait (__E, __H);
    125 }
    126 
    127 #ifdef __DISABLE_SSE3__
    128 #undef __DISABLE_SSE3__
    129 #pragma GCC pop_options
    130 #endif /* __DISABLE_SSE3__ */
    131 
    132 #endif /* _PMMINTRIN_H_INCLUDED */
    133