1 @c Copyright (C) 1996-2016 Free Software Foundation, Inc. 2 @c This is part of the GAS manual. 3 @c For copying conditions, see the file as.texinfo. 4 @ifset GENERIC 5 @page 6 @node D10V-Dependent 7 @chapter D10V Dependent Features 8 @end ifset 9 @ifclear GENERIC 10 @node Machine Dependencies 11 @chapter D10V Dependent Features 12 @end ifclear 13 14 @cindex D10V support 15 @menu 16 * D10V-Opts:: D10V Options 17 * D10V-Syntax:: Syntax 18 * D10V-Float:: Floating Point 19 * D10V-Opcodes:: Opcodes 20 @end menu 21 22 @node D10V-Opts 23 @section D10V Options 24 @cindex options, D10V 25 @cindex D10V options 26 The Mitsubishi D10V version of @code{@value{AS}} has a few machine 27 dependent options. 28 29 @table @samp 30 @item -O 31 The D10V can often execute two sub-instructions in parallel. When this option 32 is used, @code{@value{AS}} will attempt to optimize its output by detecting when 33 instructions can be executed in parallel. 34 @item --nowarnswap 35 To optimize execution performance, @code{@value{AS}} will sometimes swap the 36 order of instructions. Normally this generates a warning. When this option 37 is used, no warning will be generated when instructions are swapped. 38 @item --gstabs-packing 39 @itemx --no-gstabs-packing 40 @code{@value{AS}} packs adjacent short instructions into a single packed 41 instruction. @samp{--no-gstabs-packing} turns instruction packing off if 42 @samp{--gstabs} is specified as well; @samp{--gstabs-packing} (the 43 default) turns instruction packing on even when @samp{--gstabs} is 44 specified. 45 @end table 46 47 @node D10V-Syntax 48 @section Syntax 49 @cindex D10V syntax 50 @cindex syntax, D10V 51 52 The D10V syntax is based on the syntax in Mitsubishi's D10V architecture manual. 53 The differences are detailed below. 54 55 @menu 56 * D10V-Size:: Size Modifiers 57 * D10V-Subs:: Sub-Instructions 58 * D10V-Chars:: Special Characters 59 * D10V-Regs:: Register Names 60 * D10V-Addressing:: Addressing Modes 61 * D10V-Word:: @@WORD Modifier 62 @end menu 63 64 65 @node D10V-Size 66 @subsection Size Modifiers 67 @cindex D10V size modifiers 68 @cindex size modifiers, D10V 69 The D10V version of @code{@value{AS}} uses the instruction names in the D10V 70 Architecture Manual. However, the names in the manual are sometimes ambiguous. 71 There are instruction names that can assemble to a short or long form opcode. 72 How does the assembler pick the correct form? @code{@value{AS}} will always pick the 73 smallest form if it can. When dealing with a symbol that is not defined yet when a 74 line is being assembled, it will always use the long form. If you need to force the 75 assembler to use either the short or long form of the instruction, you can append 76 either @samp{.s} (short) or @samp{.l} (long) to it. For example, if you are writing 77 an assembly program and you want to do a branch to a symbol that is defined later 78 in your program, you can write @samp{bra.s foo}. 79 Objdump and GDB will always append @samp{.s} or @samp{.l} to instructions which 80 have both short and long forms. 81 82 @node D10V-Subs 83 @subsection Sub-Instructions 84 @cindex D10V sub-instructions 85 @cindex sub-instructions, D10V 86 The D10V assembler takes as input a series of instructions, either one-per-line, 87 or in the special two-per-line format described in the next section. Some of these 88 instructions will be short-form or sub-instructions. These sub-instructions can be packed 89 into a single instruction. The assembler will do this automatically. It will also detect 90 when it should not pack instructions. For example, when a label is defined, the next 91 instruction will never be packaged with the previous one. Whenever a branch and link 92 instruction is called, it will not be packaged with the next instruction so the return 93 address will be valid. Nops are automatically inserted when necessary. 94 95 If you do not want the assembler automatically making these decisions, you can control 96 the packaging and execution type (parallel or sequential) with the special execution 97 symbols described in the next section. 98 99 @node D10V-Chars 100 @subsection Special Characters 101 @cindex line comment character, D10V 102 @cindex D10V line comment character 103 A semicolon (@samp{;}) can be used anywhere on a line to start a 104 comment that extends to the end of the line. 105 106 If a @samp{#} appears as the first character of a line, the whole line 107 is treated as a comment, but in this case the line could also be a 108 logical line number directive (@pxref{Comments}) or a preprocessor 109 control command (@pxref{Preprocessing}). 110 111 @cindex sub-instruction ordering, D10V 112 @cindex D10V sub-instruction ordering 113 Sub-instructions may be executed in order, in reverse-order, or in parallel. 114 Instructions listed in the standard one-per-line format will be executed sequentially. 115 To specify the executing order, use the following symbols: 116 @table @samp 117 @item -> 118 Sequential with instruction on the left first. 119 @item <- 120 Sequential with instruction on the right first. 121 @item || 122 Parallel 123 @end table 124 The D10V syntax allows either one instruction per line, one instruction per line with 125 the execution symbol, or two instructions per line. For example 126 @table @code 127 @item abs a1 -> abs r0 128 Execute these sequentially. The instruction on the right is in the right 129 container and is executed second. 130 @item abs r0 <- abs a1 131 Execute these reverse-sequentially. The instruction on the right is in the right 132 container, and is executed first. 133 @item ld2w r2,@@r8+ || mac a0,r0,r7 134 Execute these in parallel. 135 @item ld2w r2,@@r8+ || 136 @itemx mac a0,r0,r7 137 Two-line format. Execute these in parallel. 138 @item ld2w r2,@@r8+ 139 @itemx mac a0,r0,r7 140 Two-line format. Execute these sequentially. Assembler will 141 put them in the proper containers. 142 @item ld2w r2,@@r8+ -> 143 @itemx mac a0,r0,r7 144 Two-line format. Execute these sequentially. Same as above but 145 second instruction will always go into right container. 146 @end table 147 @cindex symbol names, @samp{$} in 148 @cindex @code{$} in symbol names 149 Since @samp{$} has no special meaning, you may use it in symbol names. 150 151 @node D10V-Regs 152 @subsection Register Names 153 @cindex D10V registers 154 @cindex registers, D10V 155 You can use the predefined symbols @samp{r0} through @samp{r15} to refer to the D10V 156 registers. You can also use @samp{sp} as an alias for @samp{r15}. The accumulators 157 are @samp{a0} and @samp{a1}. There are special register-pair names that may 158 optionally be used in opcodes that require even-numbered registers. Register names are 159 not case sensitive. 160 161 Register Pairs 162 @table @code 163 @item r0-r1 164 @item r2-r3 165 @item r4-r5 166 @item r6-r7 167 @item r8-r9 168 @item r10-r11 169 @item r12-r13 170 @item r14-r15 171 @end table 172 173 The D10V also has predefined symbols for these control registers and status bits: 174 @table @code 175 @item psw 176 Processor Status Word 177 @item bpsw 178 Backup Processor Status Word 179 @item pc 180 Program Counter 181 @item bpc 182 Backup Program Counter 183 @item rpt_c 184 Repeat Count 185 @item rpt_s 186 Repeat Start address 187 @item rpt_e 188 Repeat End address 189 @item mod_s 190 Modulo Start address 191 @item mod_e 192 Modulo End address 193 @item iba 194 Instruction Break Address 195 @item f0 196 Flag 0 197 @item f1 198 Flag 1 199 @item c 200 Carry flag 201 @end table 202 203 @node D10V-Addressing 204 @subsection Addressing Modes 205 @cindex addressing modes, D10V 206 @cindex D10V addressing modes 207 @code{@value{AS}} understands the following addressing modes for the D10V. 208 @code{R@var{n}} in the following refers to any of the numbered 209 registers, but @emph{not} the control registers. 210 @table @code 211 @item R@var{n} 212 Register direct 213 @item @@R@var{n} 214 Register indirect 215 @item @@R@var{n}+ 216 Register indirect with post-increment 217 @item @@R@var{n}- 218 Register indirect with post-decrement 219 @item @@-SP 220 Register indirect with pre-decrement 221 @item @@(@var{disp}, R@var{n}) 222 Register indirect with displacement 223 @item @var{addr} 224 PC relative address (for branch or rep). 225 @item #@var{imm} 226 Immediate data (the @samp{#} is optional and ignored) 227 @end table 228 229 @node D10V-Word 230 @subsection @@WORD Modifier 231 @cindex D10V @@word modifier 232 @cindex @@word modifier, D10V 233 Any symbol followed by @code{@@word} will be replaced by the symbol's value 234 shifted right by 2. This is used in situations such as loading a register 235 with the address of a function (or any other code fragment). For example, if 236 you want to load a register with the location of the function @code{main} then 237 jump to that function, you could do it as follows: 238 @smallexample 239 @group 240 ldi r2, main@@word 241 jmp r2 242 @end group 243 @end smallexample 244 245 @node D10V-Float 246 @section Floating Point 247 @cindex floating point, D10V 248 @cindex D10V floating point 249 The D10V has no hardware floating point, but the @code{.float} and @code{.double} 250 directives generates @sc{ieee} floating-point numbers for compatibility 251 with other development tools. 252 253 @node D10V-Opcodes 254 @section Opcodes 255 @cindex D10V opcode summary 256 @cindex opcode summary, D10V 257 @cindex mnemonics, D10V 258 @cindex instruction summary, D10V 259 For detailed information on the D10V machine instruction set, see 260 @cite{D10V Architecture: A VLIW Microprocessor for Multimedia Applications} 261 (Mitsubishi Electric Corp.). 262 @code{@value{AS}} implements all the standard D10V opcodes. The only changes are those 263 described in the section on size modifiers 264 265
