1 @c Copyright (C) 2002-2016 Free Software Foundation, Inc. 2 @c Contributed by David Mosberger-Tang <davidm (a] hpl.hp.com> 3 @c This is part of the GAS manual. 4 @c For copying conditions, see the file as.texinfo. 5 6 @ifset GENERIC 7 @page 8 @node IA-64-Dependent 9 @chapter IA-64 Dependent Features 10 @end ifset 11 12 @ifclear GENERIC 13 @node Machine Dependencies 14 @chapter IA-64 Dependent Features 15 @end ifclear 16 17 @cindex IA-64 support 18 @menu 19 * IA-64 Options:: Options 20 * IA-64 Syntax:: Syntax 21 @c * IA-64 Floating Point:: Floating Point // to be written 22 @c * IA-64 Directives:: IA-64 Machine Directives // to be written 23 * IA-64 Opcodes:: Opcodes 24 @end menu 25 26 @node IA-64 Options 27 @section Options 28 @cindex IA-64 options 29 @cindex options for IA-64 30 31 @table @option 32 @cindex @code{-mconstant-gp} command line option, IA-64 33 34 @item -mconstant-gp 35 This option instructs the assembler to mark the resulting object file 36 as using the ``constant GP'' model. With this model, it is assumed 37 that the entire program uses a single global pointer (GP) value. Note 38 that this option does not in any fashion affect the machine code 39 emitted by the assembler. All it does is turn on the EF_IA_64_CONS_GP 40 flag in the ELF file header. 41 42 @item -mauto-pic 43 This option instructs the assembler to mark the resulting object file 44 as using the ``constant GP without function descriptor'' data model. 45 This model is like the ``constant GP'' model, except that it 46 additionally does away with function descriptors. What this means is 47 that the address of a function refers directly to the function's code 48 entry-point. Normally, such an address would refer to a function 49 descriptor, which contains both the code entry-point and the GP-value 50 needed by the function. Note that this option does not in any fashion 51 affect the machine code emitted by the assembler. All it does is 52 turn on the EF_IA_64_NOFUNCDESC_CONS_GP flag in the ELF file header. 53 54 @item -milp32 55 @itemx -milp64 56 @itemx -mlp64 57 @itemx -mp64 58 These options select the data model. The assembler defaults to @code{-mlp64} 59 (LP64 data model). 60 61 @item -mle 62 @itemx -mbe 63 These options select the byte order. The @code{-mle} option selects little-endian 64 byte order (default) and @code{-mbe} selects big-endian byte order. Note that 65 IA-64 machine code always uses little-endian byte order. 66 67 @item -mtune=itanium1 68 @itemx -mtune=itanium2 69 Tune for a particular IA-64 CPU, @var{itanium1} or @var{itanium2}. The 70 default is @var{itanium2}. 71 72 @item -munwind-check=warning 73 @itemx -munwind-check=error 74 These options control what the assembler will do when performing 75 consistency checks on unwind directives. @code{-munwind-check=warning} 76 will make the assembler issue a warning when an unwind directive check 77 fails. This is the default. @code{-munwind-check=error} will make the 78 assembler issue an error when an unwind directive check fails. 79 80 @item -mhint.b=ok 81 @itemx -mhint.b=warning 82 @itemx -mhint.b=error 83 These options control what the assembler will do when the @samp{hint.b} 84 instruction is used. @code{-mhint.b=ok} will make the assembler accept 85 @samp{hint.b}. @code{-mint.b=warning} will make the assembler issue a 86 warning when @samp{hint.b} is used. @code{-mhint.b=error} will make 87 the assembler treat @samp{hint.b} as an error, which is the default. 88 89 @item -x 90 @itemx -xexplicit 91 These options turn on dependency violation checking. 92 93 @item -xauto 94 This option instructs the assembler to automatically insert stop bits where necessary 95 to remove dependency violations. This is the default mode. 96 97 @item -xnone 98 This option turns off dependency violation checking. 99 100 @item -xdebug 101 This turns on debug output intended to help tracking down bugs in the dependency 102 violation checker. 103 104 @item -xdebugn 105 This is a shortcut for -xnone -xdebug. 106 107 @item -xdebugx 108 This is a shortcut for -xexplicit -xdebug. 109 110 @end table 111 112 @cindex IA-64 Syntax 113 @node IA-64 Syntax 114 @section Syntax 115 The assembler syntax closely follows the IA-64 Assembly Language 116 Reference Guide. 117 118 @menu 119 * IA-64-Chars:: Special Characters 120 * IA-64-Regs:: Register Names 121 * IA-64-Bits:: Bit Names 122 * IA-64-Relocs:: Relocations 123 @end menu 124 125 @node IA-64-Chars 126 @subsection Special Characters 127 128 @cindex line comment character, IA-64 129 @cindex IA-64 line comment character 130 @samp{//} is the line comment token. 131 132 @cindex line separator, IA-64 133 @cindex statement separator, IA-64 134 @cindex IA-64 line separator 135 @samp{;} can be used instead of a newline to separate statements. 136 137 @node IA-64-Regs 138 @subsection Register Names 139 @cindex IA-64 registers 140 @cindex register names, IA-64 141 142 The 128 integer registers are referred to as @samp{r@var{n}}. 143 The 128 floating-point registers are referred to as @samp{f@var{n}}. 144 The 128 application registers are referred to as @samp{ar@var{n}}. 145 The 128 control registers are referred to as @samp{cr@var{n}}. 146 The 64 one-bit predicate registers are referred to as @samp{p@var{n}}. 147 The 8 branch registers are referred to as @samp{b@var{n}}. 148 In addition, the assembler defines a number of aliases: 149 @samp{gp} (@samp{r1}), @samp{sp} (@samp{r12}), @samp{rp} (@samp{b0}), 150 @samp{ret0} (@samp{r8}), @samp{ret1} (@samp{r9}), @samp{ret2} (@samp{r10}), 151 @samp{ret3} (@samp{r9}), @samp{farg@var{n}} (@samp{f8+@var{n}}), and 152 @samp{fret@var{n}} (@samp{f8+@var{n}}). 153 154 For convenience, the assembler also defines aliases for all named application 155 and control registers. For example, @samp{ar.bsp} refers to the register 156 backing store pointer (@samp{ar17}). Similarly, @samp{cr.eoi} refers to 157 the end-of-interrupt register (@samp{cr67}). 158 159 @node IA-64-Bits 160 @subsection IA-64 Processor-Status-Register (PSR) Bit Names 161 @cindex IA-64 Processor-status-Register bit names 162 @cindex PSR bits 163 @cindex bit names, IA-64 164 165 The assembler defines bit masks for each of the bits in the IA-64 166 processor status register. For example, @samp{psr.ic} corresponds to 167 a value of 0x2000. These masks are primarily intended for use with 168 the @samp{ssm}/@samp{sum} and @samp{rsm}/@samp{rum} 169 instructions, but they can be used anywhere else where an integer 170 constant is expected. 171 172 @node IA-64-Relocs 173 @subsection Relocations 174 @cindex IA-64 relocations 175 176 In addition to the standard IA-64 relocations, the following relocations are 177 implemented by @code{@value{AS}}: 178 179 @table @code 180 @item @@slotcount(@var{V}) 181 Convert the address offset @var{V} into a slot count. This pseudo 182 function is available only on VMS. The expression @var{V} must be 183 known at assembly time: it can't reference undefined symbols or symbols in 184 different sections. 185 @end table 186 187 @node IA-64 Opcodes 188 @section Opcodes 189 For detailed information on the IA-64 machine instruction set, see the 190 @c Attempt to work around a very overfull hbox. 191 @iftex 192 IA-64 Assembly Language Reference Guide available at 193 @smallfonts 194 @example 195 http://developer.intel.com/design/itanium/arch_spec.htm 196 @end example 197 @textfonts 198 @end iftex 199 @ifnottex 200 @uref{http://developer.intel.com/design/itanium/arch_spec.htm,IA-64 Architecture Handbook}. 201 @end ifnottex 202
