1 #name: ARM V7-R+MP instructions 2 #as: -march=armv7-r+mp 3 #objdump: -dr --prefix-addresses --show-raw-insn 4 #source: arch7ar-mp.s 5 6 .*: +file format .*arm.* 7 8 Disassembly of section .text: 9 0[0-9a-f]+ <[^>]+> f590f000 pldw \[r0\] 10 0[0-9a-f]+ <[^>]+> f59ef000 pldw \[lr\] 11 0[0-9a-f]+ <[^>]+> f591f000 pldw \[r1\] 12 0[0-9a-f]+ <[^>]+> f590ffff pldw \[r0, #4095\] ; 0xfff 13 0[0-9a-f]+ <[^>]+> f510ffff pldw \[r0, #-4095\] ; 0xfffff001 14 0[0-9a-f]+ <[^>]+> f790f000 pldw \[r0, r0\] 15 0[0-9a-f]+ <[^>]+> f791f000 pldw \[r1, r0\] 16 0[0-9a-f]+ <[^>]+> f79ef000 pldw \[lr, r0\] 17 0[0-9a-f]+ <[^>]+> f790f001 pldw \[r0, r1\] 18 0[0-9a-f]+ <[^>]+> f790f00e pldw \[r0, lr\] 19 0[0-9a-f]+ <[^>]+> f790f100 pldw \[r0, r0, lsl #2\] 20 0[0-9a-f]+ <[^>]+> f8b0 f000 pldw \[r0\] 21 0[0-9a-f]+ <[^>]+> f8be f000 pldw \[lr\] 22 0[0-9a-f]+ <[^>]+> f8b1 f000 pldw \[r1\] 23 0[0-9a-f]+ <[^>]+> f8b0 ffff pldw \[r0, #4095\] ; 0xfff 24 0[0-9a-f]+ <[^>]+> f830 fcff pldw \[r0, #-255\] 25 0[0-9a-f]+ <[^>]+> f830 f000 pldw \[r0, r0\] 26 0[0-9a-f]+ <[^>]+> f831 f000 pldw \[r1, r0\] 27 0[0-9a-f]+ <[^>]+> f83e f000 pldw \[lr, r0\] 28 0[0-9a-f]+ <[^>]+> f830 f001 pldw \[r0, r1\] 29 0[0-9a-f]+ <[^>]+> f830 f00e pldw \[r0, lr\] 30 0[0-9a-f]+ <[^>]+> f830 f030 pldw \[r0, r0, lsl #3\] 31
