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      1 # name: Mixed 16 and 32-bit Thumb conditional instructions
      2 # as: -march=armv6kt2 -mimplicit-it=always
      3 #skip: *-*-*aout*
      4 # source: thumb2_it.s
      5 # objdump: -dr --prefix-addresses --show-raw-insn
      6 
      7 .*: +file format .*arm.*
      8 
      9 Disassembly of section .text:
     10 0+000 <[^>]+> bf05      	ittet	eq
     11 0+002 <[^>]+> 1880      	addeq	r0, r0, r2
     12 0+004 <[^>]+> 4440      	addeq	r0, r8
     13 0+006 <[^>]+> 1888      	addne	r0, r1, r2
     14 0+008 <[^>]+> eb11 0002 	addseq.w	r0, r1, r2
     15 0+00c <[^>]+> 4410      	add	r0, r2
     16 0+00e <[^>]+> 4440      	add	r0, r8
     17 0+010 <[^>]+> 1880      	adds	r0, r0, r2
     18 0+012 <[^>]+> eb10 0008 	adds.w	r0, r0, r8
     19 0+016 <[^>]+> 1888      	adds	r0, r1, r2
     20 0+018 <[^>]+> bf0a      	itet	eq
     21 0+01a <[^>]+> 4310      	orreq	r0, r2
     22 0+01c <[^>]+> ea40 0008 	orrne.w	r0, r0, r8
     23 0+020 <[^>]+> ea50 0002 	orrseq.w	r0, r0, r2
     24 0+024 <[^>]+> ea40 0002 	orr.w	r0, r0, r2
     25 0+028 <[^>]+> ea40 0008 	orr.w	r0, r0, r8
     26 0+02c <[^>]+> 4310      	orrs	r0, r2
     27 0+02e <[^>]+> bf01      	itttt	eq
     28 0+030 <[^>]+> 4090      	lsleq	r0, r2
     29 0+032 <[^>]+> fa00 f008 	lsleq.w	r0, r0, r8
     30 0+036 <[^>]+> fa01 f002 	lsleq.w	r0, r1, r2
     31 0+03a <[^>]+> fa10 f002 	lslseq.w	r0, r0, r2
     32 0+03e <[^>]+> bf02      	ittt	eq
     33 0+040 <[^>]+> 0048      	lsleq	r0, r1, #1
     34 0+042 <[^>]+> ea4f 0048 	moveq.w	r0, r8, lsl #1
     35 0+046 <[^>]+> ea5f 0040 	movseq.w	r0, r0, lsl #1
     36 0+04a <[^>]+> fa00 f002 	lsl.w	r0, r0, r2
     37 0+04e <[^>]+> 4090      	lsls	r0, r2
     38 0+050 <[^>]+> ea4f 0041 	mov.w	r0, r1, lsl #1
     39 0+054 <[^>]+> 0048      	lsls	r0, r1, #1
     40 0+056 <[^>]+> bf01      	itttt	eq
     41 0+058 <[^>]+> 4288      	cmpeq	r0, r1
     42 0+05a <[^>]+> 4540      	cmpeq	r0, r8
     43 0+05c <[^>]+> 4608      	moveq	r0, r1
     44 0+05e <[^>]+> ea5f 0001 	movseq.w	r0, r1
     45 0+062 <[^>]+> bf08      	it	eq
     46 0+064 <[^>]+> 4640      	moveq	r0, r8
     47 0+066 <[^>]+> 4608      	mov	r0, r1
     48 0+068 <[^>]+> 0008      	movs	r0, r1
     49 0+06a <[^>]+> ea5f 0008 	movs.w	r0, r8
     50 0+06e <[^>]+> bf01      	itttt	eq
     51 0+070 <[^>]+> 43c8      	mvneq	r0, r1
     52 0+072 <[^>]+> ea6f 0008 	mvneq.w	r0, r8
     53 0+076 <[^>]+> ea7f 0001 	mvnseq.w	r0, r1
     54 0+07a <[^>]+> 42c8      	cmneq	r0, r1
     55 0+07c <[^>]+> ea6f 0001 	mvn.w	r0, r1
     56 0+080 <[^>]+> 43c8      	mvns	r0, r1
     57 0+082 <[^>]+> bf02      	ittt	eq
     58 0+084 <[^>]+> 4248      	negeq	r0, r1
     59 0+086 <[^>]+> f1c8 0000 	rsbeq	r0, r8, #0
     60 0+08a <[^>]+> f1d1 0000 	rsbseq	r0, r1, #0
     61 0+08e <[^>]+> f1c1 0000 	rsb	r0, r1, #0
     62 0+092 <[^>]+> 4248      	negs	r0, r1
     63 0+094 <[^>]+> bfc8      	it	gt
     64 0+096 <[^>]+> 4220      	tstgt	r0, r4
     65