1 .text 2 3 // Accumulator to Half D-register Moves 4 5 R0.L = A0; 6 R0.L = A0 (FU); 7 R0.L = A0 (IS); 8 R0.L = A0 (IU); 9 R0.L = A0 (T); 10 R0.L = A0 (TFU); // Not documented 11 R0.L = A0 (S2RND); 12 R0.L = A0 (ISS2); 13 R0.L = A0 (IH); 14 15 // Accumulator to D-register Moves 16 17 R0 = A0; 18 R0 = A0 (FU); 19 R0 = A0 (IS); // Not documented 20 R0 = A0 (IU); // Not documented 21 R0 = A0 (S2RND); 22 R0 = A0 (ISS2); 23 24 // Multiply 16-Bit Operands to Half Dreg 25 26 R0.H = R1.L * R2.H; 27 R0.H = R1.L * R2.H (FU); 28 R0.H = R1.L * R2.H (IS); 29 R0.H = R1.L * R2.H (IU); 30 R0.H = R1.L * R2.H (T); 31 R0.H = R1.L * R2.H (TFU); 32 R0.H = R1.L * R2.H (S2RND); 33 R0.H = R1.L * R2.H (ISS2); 34 R0.H = R1.L * R2.H (IH); 35 36 // Multiply 16-Bit Operands to Dreg 37 38 R0 = R1.L * R2.H; 39 R0 = R1.L * R2.H (FU); 40 R0 = R1.L * R2.H (IS); 41 R0 = R1.L * R2.H (S2RND); // Not documented 42 R0 = R1.L * R2.H (ISS2); 43 44 // Multiply and Multiply-Accumulate to Accumulator 45 46 A0 = R1.L * R2.H; 47 A0 = R1.L * R2.H (FU); 48 A0 = R1.L * R2.H (IS); 49 A0 = R1.L * R2.H (W32); 50 51 // Multiply and Multiply-Accumulate to Half-Register 52 53 R0.L = (A0 = R1.L * R2.H); 54 R0.L = (A0 = R1.L * R2.H) (FU); 55 R0.L = (A0 = R1.L * R2.H) (IS); 56 R0.L = (A0 = R1.L * R2.H) (IU); 57 R0.L = (A0 = R1.L * R2.H) (T); 58 R0.L = (A0 = R1.L * R2.H) (TFU); 59 R0.L = (A0 = R1.L * R2.H) (S2RND); 60 R0.L = (A0 = R1.L * R2.H) (ISS2); 61 R0.L = (A0 = R1.L * R2.H) (IH); 62 63 // Multiply and Multiply-Accumulate to Data Register 64 65 R0 = (A0 = R1.L * R2.H); 66 R0 = (A0 = R1.L * R2.H) (FU); 67 R0 = (A0 = R1.L * R2.H) (IS); 68 R0 = (A0 = R1.L * R2.H) (IU); // Not documented 69 R0 = (A0 = R1.L * R2.H) (S2RND); 70 R0 = (A0 = R1.L * R2.H) (ISS2); 71 72 73
