1 2 .EXTERN MY_LABEL2; 3 .section .text; 4 5 // 6 //6 CONTROL CODE BIT MANAGEMENT 7 // 8 9 //CC = Dreg == Dreg ; /* equal, register, signed (a) */ 10 CC = R7 == R0; 11 CC = R6 == R1; 12 CC = R0 == R7; 13 14 //CC = Dreg == imm3 ; /* equal, immediate, signed (a) */ 15 CC = R7 == -4; 16 CC = R7 == 3; 17 CC = R0 == -4; 18 CC = R0 == 3; 19 20 //CC = Dreg < Dreg ; /* less than, register, signed (a) */ 21 CC = R7 < R0; 22 CC = R6 < R0; 23 CC = R7 < R1; 24 CC = R1 < R7; 25 CC = R0 < R6; 26 27 //CC = Dreg < imm3 ; /* less than, immediate, signed (a) */ 28 CC = R7 < -4; 29 CC = R6 < -4; 30 CC = R7 < 3; 31 CC = R1 < 3; 32 33 //CC = Dreg <= Dreg ; /* less than or equal, register, signed (a) */ 34 CC = R7 <= R0; 35 CC = R6 <= R0; 36 CC = R7 <= R1; 37 CC = R1 <= R7; 38 CC = R0 <= R6; 39 40 //CC = Dreg <= imm3 ; /* less than or equal, immediate, signed (a) */ 41 CC = R7 <= -4; 42 CC = R6 <= -4; 43 CC = R7 <= 3; 44 CC = R1 <= 3; 45 46 //CC = Dreg < Dreg (IU) ; /* less than, register, unsigned (a) */ 47 CC = R7 < R0(IU); 48 CC = R6 < R0(IU); 49 CC = R7 < R1(IU); 50 CC = R1 < R7(IU); 51 CC = R0 < R6(IU); 52 53 //CC = Dreg < uimm3 (IU) ; /* less than, immediate, unsigned (a) */ 54 CC = R7 < 0(IU); 55 CC = R6 < 0(IU); 56 CC = R7 < 7(IU); 57 CC = R1 < 7(IU); 58 //CC = Dreg <= Dreg (IU) ; /* less than or equal, register, unsigned (a) */ 59 CC = R7 <= R0(IU); 60 CC = R6 <= R0(IU); 61 CC = R7 <= R1(IU); 62 CC = R1 <= R7(IU); 63 CC = R0 <= R6(IU); 64 65 66 //CC = Dreg <= uimm3 (IU) ; /* less than or equal, immediate unsigned (a) */ 67 CC = R7 <= 0(IU); 68 CC = R6 <= 0(IU); 69 CC = R7 <= 7(IU); 70 CC = R1 <= 7(IU); 71 72 //CC = Preg == Preg ; /* equal, register, signed (a) */ 73 CC = P5 == P0; 74 CC = P5 == P1; 75 CC = P0 == P2; 76 CC = P3 == P5; 77 78 //CC = Preg == imm3 ; /* equal, immediate, signed (a) */ 79 CC = P5 == -4; 80 CC = P5 == 0; 81 CC = P5 == 3; 82 CC = P2 == -4; 83 CC = P2 == 0; 84 CC = P2 == 3; 85 86 //CC = Preg < Preg ; /* less than, register, signed (a) */ 87 CC = P5 < P0; 88 CC = P5 < P1; 89 CC = P0 < P2; 90 CC = P3 < P5; 91 92 //CC = Preg < imm3 ; /* less than, immediate, signed (a) */ 93 CC = P5 < -4; 94 CC = P5 < 0; 95 CC = P5 < 3; 96 CC = P2 < -4; 97 CC = P2 < 0; 98 CC = P2 < 3; 99 100 101 //CC = Preg <= Preg ; /* less than or equal, register, signed (a) */ 102 CC = P5 <= P0; 103 CC = P5 <= P1; 104 CC = P0 <= P2; 105 CC = P3 <= P5; 106 107 //CC = Preg <= imm3 ; /* less than or equal, immediate, signed (a) */ 108 CC = P5 <= -4; 109 CC = P5 <= 0; 110 CC = P5 <= 3; 111 CC = P2 <= -4; 112 CC = P2 <= 0; 113 CC = P2 <= 3; 114 115 //CC = Preg < Preg (IU) ; /* less than, register, unsigned (a) */ 116 CC = P5 < P0(IU); 117 CC = P5 < P1(IU); 118 CC = P0 < P2(IU); 119 CC = P3 < P5(IU); 120 121 //CC = Preg < uimm3 (IU) ; /* less than, immediate, unsigned (a) */ 122 CC = P5 < 0(IU); 123 CC = P5 < 7(IU); 124 CC = P2 < 0(IU); 125 CC = P2 < 7(IU); 126 127 //CC = Preg <= Preg (IU) ; /* less than or equal, register, unsigned (a) */ 128 CC = P5 <= P0(IU); 129 CC = P5 <= P1(IU); 130 CC = P0 <= P2(IU); 131 CC = P3 <= P5(IU); 132 133 //CC = Preg <= uimm3 (IU) ; /* less than or equal, immediate unsigned (a) */ 134 CC = P5 <= 0(IU); 135 CC = P5 <= 7(IU); 136 CC = P2 <= 0(IU); 137 CC = P2 <= 7(IU); 138 139 CC = A0 == A1 ; /* equal, signed (a) */ 140 CC = A0 < A1 ; /* less than, Accumulator, signed (a) */ 141 CC = A0 <= A1 ; /* less than or equal, Accumulator, signed (a) */ 142 143 //Dreg = CC ; /* CC into 32-bit data register, zero-extended (a) */ 144 R7 = CC; 145 R0 = CC; 146 147 //statbit = CC ; /* status bit equals CC (a) */ 148 AZ = CC; 149 AN = CC; 150 AC0= CC; 151 AC1= CC; 152 //V = CC; 153 VS = CC; 154 AV0= CC; 155 AV0S= CC; 156 AV1 = CC; 157 AV1S= CC; 158 AQ = CC; 159 //statbit |= CC ; /* status bit equals status bit OR CC (a) */ 160 AZ |= CC; 161 AN |= CC; 162 AC0|= CC; 163 AC1|= CC; 164 //V |= CC; 165 VS |= CC; 166 AV0|= CC; 167 AV0S|= CC; 168 AV1 |= CC; 169 AV1S|= CC; 170 AQ |= CC; 171 172 //statbit &= CC ; /* status bit equals status bit AND CC (a) */ 173 AZ &= CC; 174 AN &= CC; 175 AC0&= CC; 176 AC1&= CC; 177 //V &= CC; 178 VS &= CC; 179 AV0&= CC; 180 AV0S&= CC; 181 AV1 &= CC; 182 AV1S&= CC; 183 AQ &= CC; 184 185 //statbit ^= CC ; /* status bit equals status bit XOR CC (a) */ 186 187 AZ ^= CC; 188 AN ^= CC; 189 AC0^= CC; 190 AC1^= CC; 191 //V ^= CC; 192 VS ^= CC; 193 AV0^= CC; 194 AV0S^= CC; 195 AV1 ^= CC; 196 AV1S^= CC; 197 AQ ^= CC; 198 //CC = Dreg ; /* CC set if the register is non-zero (a) */ 199 CC = R7; 200 CC = R6; 201 CC = R1; 202 CC = R0; 203 204 205 //CC = statbit ; /* CC equals status bit (a) */ 206 CC = AZ; 207 CC = AN; 208 CC = AC0; 209 CC = AC1; 210 //CC = V; 211 CC = VS; 212 CC = AV0; 213 CC = AV0S; 214 CC = AV1; 215 CC = AV1S; 216 CC = AQ; 217 218 //CC |= statbit ; /* CC equals CC OR status bit (a) */ 219 CC |= AZ; 220 CC |= AN; 221 CC |= AC0; 222 CC |= AC1; 223 //CC |= V; 224 CC |= VS; 225 CC |= AV0; 226 CC |= AV0S; 227 CC |= AV1; 228 CC |= AV1S; 229 CC |= AQ; 230 231 //CC &= statbit ; /* CC equals CC AND status bit (a) */ 232 CC &= AZ; 233 CC &= AN; 234 CC &= AC0; 235 CC &= AC1; 236 //CC &= V; 237 CC &= VS; 238 CC &= AV0; 239 CC &= AV0S; 240 CC &= AV1; 241 CC &= AV1S; 242 CC &= AQ; 243 244 //CC ^= statbit ; /* CC equals CC XOR status bit (a) */ 245 CC ^= AZ; 246 CC ^= AN; 247 CC ^= AC0; 248 CC ^= AC1; 249 //CC ^= V; 250 CC ^= VS; 251 CC ^= AV0; 252 CC ^= AV0S; 253 CC ^= AV1; 254 CC ^= AV1S; 255 CC ^= AQ; 256 257 CC = ! CC ; /* (a) */ 258
