1 /* 2 * test relax 3 * lw <-> lw! : register number must be in 0-15, offset == 0 4 * lh <-> lh! : register number must be in 0-15, offset == 0 5 * lbu <-> lbu! : register number must be in 0-15, offset == 0 6 * sw <-> sw! : register number must be in 0-15, offset == 0 7 * sh <-> sh! : register number must be in 0-15, offset == 0 8 * sb <-> sb! : register number must be in 0-15, offset == 0 9 10 * Author: ligang 11 */ 12 13 /* This macro transform 32b instruction to 16b. */ 14 .macro tran3216 insn32, insn16 15 .align 4 16 17 \insn32 r0, [r3, 0] #32b -> 16b 18 \insn16 r0, [r3] 19 20 \insn32 r3, [r15, 0] #32b -> 16b 21 \insn16 r3, [r15] 22 23 \insn32 r15, [r8, 0] #32b -> 16b 24 \insn16 r15, [r8] 25 26 \insn32 r4, [r8, 0] #No transform 27 \insn32 r25, [r19, 0] 28 29 \insn32 r5, [r7, 0] #32b -> 16b 30 \insn32 r5, [r7, 0] #32b -> 16b 31 32 \insn16 r2, [r3] 33 \insn32 r2, [r3, 0] #32b -> 16b 34 35 .endm 36 37 /* This macro transform 16b instruction to 32b. */ 38 .macro tran1632 insn32, insn16 39 .align 4 40 41 \insn16 r0, [r3] #16b -> 32b 42 \insn32 r18, [r23, 10] 43 44 \insn16 r15, [r0] #16b -> 32b 45 \insn32 r17, [r26, 10] 46 47 \insn16 r6, [r8] #No transform 48 \insn16 r6, [r8] #No transform 49 50 \insn16 r3, [r7] #No transform 51 \insn32 r3, [r7, 0] 52 53 .endm 54 .space 1 55 tran3216 "lw", "lw!" 56 .fill 10, 1 57 tran3216 "lh", "lh!" 58 .org 0x101 59 tran3216 "lbu", "lbu!" 60 .org 0x203 61 tran3216 "sw", "sw!" 62 tran3216 "sh", "sh!" 63 tran3216 "sb", "sb!" 64 65 tran1632 "lw", "lw!" 66 tran1632 "lh", "lh!" 67 tran1632 "lbu", "lbu!" 68 tran1632 "sw", "sw!" 69 tran1632 "sh", "sh!" 70 tran1632 "sb", "sb!" 71
