1 /* Disassembler interface for targets using CGEN. -*- C -*- 2 CGEN: Cpu tools GENerator 3 4 THIS FILE IS MACHINE GENERATED WITH CGEN. 5 - the resultant file is machine generated, cgen-dis.in isn't 6 7 Copyright (C) 1996-2016 Free Software Foundation, Inc. 8 9 This file is part of libopcodes. 10 11 This library is free software; you can redistribute it and/or modify 12 it under the terms of the GNU General Public License as published by 13 the Free Software Foundation; either version 3, or (at your option) 14 any later version. 15 16 It is distributed in the hope that it will be useful, but WITHOUT 17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 18 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 19 License for more details. 20 21 You should have received a copy of the GNU General Public License 22 along with this program; if not, write to the Free Software Foundation, Inc., 23 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ 24 25 /* ??? Eventually more and more of this stuff can go to cpu-independent files. 26 Keep that in mind. */ 27 28 #include "sysdep.h" 29 #include <stdio.h> 30 #include "ansidecl.h" 31 #include "dis-asm.h" 32 #include "bfd.h" 33 #include "symcat.h" 34 #include "libiberty.h" 35 #include "epiphany-desc.h" 36 #include "epiphany-opc.h" 37 #include "opintl.h" 38 39 /* Default text to print if an instruction isn't recognized. */ 40 #define UNKNOWN_INSN_MSG _("*unknown*") 41 42 static void print_normal 43 (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int); 44 static void print_address 45 (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED; 46 static void print_keyword 47 (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED; 48 static void print_insn_normal 49 (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int); 50 static int print_insn 51 (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, unsigned); 52 static int default_print_insn 53 (CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED; 54 static int read_insn 55 (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *, 56 unsigned long *); 57 58 /* -- disassembler routines inserted here. */ 60 61 /* -- dis.c */ 62 63 #define CGEN_PRINT_INSN epiphany_print_insn 64 65 static int 66 epiphany_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) 67 { 68 bfd_byte buf[CGEN_MAX_INSN_SIZE]; 69 int buflen; 70 int status; 71 72 info->bytes_per_chunk = 2; 73 info->bytes_per_line = 4; 74 75 /* Attempt to read the base part of the insn. */ 76 buflen = cd->base_insn_bitsize / 8; 77 status = (*info->read_memory_func) (pc, buf, buflen, info); 78 79 /* Try again with the minimum part, if min < base. */ 80 if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize)) 81 { 82 buflen = cd->min_insn_bitsize / 8; 83 status = (*info->read_memory_func) (pc, buf, buflen, info); 84 } 85 86 if (status != 0) 87 { 88 (*info->memory_error_func) (status, pc, info); 89 return -1; 90 } 91 92 return print_insn (cd, pc, info, buf, buflen); 93 } 94 95 96 static void 97 print_postindex (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 98 void * dis_info, 99 long value, 100 unsigned int attrs ATTRIBUTE_UNUSED, 101 bfd_vma pc ATTRIBUTE_UNUSED, 102 int length ATTRIBUTE_UNUSED) 103 { 104 disassemble_info *info = (disassemble_info *) dis_info; 105 (*info->fprintf_func) (info->stream, value ? "-" : "+"); 106 } 107 108 static void 109 print_simm_not_reg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 110 void * dis_info, 111 long value, 112 unsigned int attrs ATTRIBUTE_UNUSED, 113 bfd_vma pc ATTRIBUTE_UNUSED, 114 int length ATTRIBUTE_UNUSED) 115 { 116 print_address (cd, dis_info, value, attrs, pc, length); 117 } 118 119 static void 120 print_uimm_not_reg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 121 void * dis_info, 122 unsigned long value, 123 unsigned int attrs ATTRIBUTE_UNUSED, 124 bfd_vma pc ATTRIBUTE_UNUSED, 125 int length ATTRIBUTE_UNUSED) 126 { 127 disassemble_info *info = (disassemble_info *)dis_info; 128 129 if (value & 0x800) 130 (*info->fprintf_func) (info->stream, "-"); 131 132 value &= 0x7ff; 133 print_address (cd, dis_info, value, attrs, pc, length); 134 } 135 136 137 /* -- */ 139 140 void epiphany_cgen_print_operand 141 (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int); 142 143 /* Main entry point for printing operands. 144 XINFO is a `void *' and not a `disassemble_info *' to not put a requirement 145 of dis-asm.h on cgen.h. 146 147 This function is basically just a big switch statement. Earlier versions 148 used tables to look up the function to use, but 149 - if the table contains both assembler and disassembler functions then 150 the disassembler contains much of the assembler and vice-versa, 151 - there's a lot of inlining possibilities as things grow, 152 - using a switch statement avoids the function call overhead. 153 154 This function could be moved into `print_insn_normal', but keeping it 155 separate makes clear the interface between `print_insn_normal' and each of 156 the handlers. */ 157 158 void 159 epiphany_cgen_print_operand (CGEN_CPU_DESC cd, 160 int opindex, 161 void * xinfo, 162 CGEN_FIELDS *fields, 163 void const *attrs ATTRIBUTE_UNUSED, 164 bfd_vma pc, 165 int length) 166 { 167 disassemble_info *info = (disassemble_info *) xinfo; 168 169 switch (opindex) 170 { 171 case EPIPHANY_OPERAND_DIRECTION : 172 print_postindex (cd, info, fields->f_addsubx, 0, pc, length); 173 break; 174 case EPIPHANY_OPERAND_DISP11 : 175 print_uimm_not_reg (cd, info, fields->f_disp11, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length); 176 break; 177 case EPIPHANY_OPERAND_DISP3 : 178 print_normal (cd, info, fields->f_disp3, 0, pc, length); 179 break; 180 case EPIPHANY_OPERAND_DPMI : 181 print_postindex (cd, info, fields->f_subd, 0, pc, length); 182 break; 183 case EPIPHANY_OPERAND_FRD : 184 print_keyword (cd, info, & epiphany_cgen_opval_gr_names, fields->f_rd, 0); 185 break; 186 case EPIPHANY_OPERAND_FRD6 : 187 print_keyword (cd, info, & epiphany_cgen_opval_gr_names, fields->f_rd6, 0|(1<<CGEN_OPERAND_VIRTUAL)); 188 break; 189 case EPIPHANY_OPERAND_FRM : 190 print_keyword (cd, info, & epiphany_cgen_opval_gr_names, fields->f_rm, 0); 191 break; 192 case EPIPHANY_OPERAND_FRM6 : 193 print_keyword (cd, info, & epiphany_cgen_opval_gr_names, fields->f_rm6, 0|(1<<CGEN_OPERAND_VIRTUAL)); 194 break; 195 case EPIPHANY_OPERAND_FRN : 196 print_keyword (cd, info, & epiphany_cgen_opval_gr_names, fields->f_rn, 0); 197 break; 198 case EPIPHANY_OPERAND_FRN6 : 199 print_keyword (cd, info, & epiphany_cgen_opval_gr_names, fields->f_rn6, 0|(1<<CGEN_OPERAND_VIRTUAL)); 200 break; 201 case EPIPHANY_OPERAND_IMM16 : 202 print_address (cd, info, fields->f_imm16, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_VIRTUAL), pc, length); 203 break; 204 case EPIPHANY_OPERAND_IMM8 : 205 print_address (cd, info, fields->f_imm8, 0|(1<<CGEN_OPERAND_RELAX), pc, length); 206 break; 207 case EPIPHANY_OPERAND_RD : 208 print_keyword (cd, info, & epiphany_cgen_opval_gr_names, fields->f_rd, 0); 209 break; 210 case EPIPHANY_OPERAND_RD6 : 211 print_keyword (cd, info, & epiphany_cgen_opval_gr_names, fields->f_rd6, 0|(1<<CGEN_OPERAND_VIRTUAL)); 212 break; 213 case EPIPHANY_OPERAND_RM : 214 print_keyword (cd, info, & epiphany_cgen_opval_gr_names, fields->f_rm, 0); 215 break; 216 case EPIPHANY_OPERAND_RM6 : 217 print_keyword (cd, info, & epiphany_cgen_opval_gr_names, fields->f_rm6, 0|(1<<CGEN_OPERAND_VIRTUAL)); 218 break; 219 case EPIPHANY_OPERAND_RN : 220 print_keyword (cd, info, & epiphany_cgen_opval_gr_names, fields->f_rn, 0); 221 break; 222 case EPIPHANY_OPERAND_RN6 : 223 print_keyword (cd, info, & epiphany_cgen_opval_gr_names, fields->f_rn6, 0|(1<<CGEN_OPERAND_VIRTUAL)); 224 break; 225 case EPIPHANY_OPERAND_SD : 226 print_keyword (cd, info, & epiphany_cgen_opval_cr_names, fields->f_sd, 0); 227 break; 228 case EPIPHANY_OPERAND_SD6 : 229 print_keyword (cd, info, & epiphany_cgen_opval_cr_names, fields->f_sd6, 0|(1<<CGEN_OPERAND_VIRTUAL)); 230 break; 231 case EPIPHANY_OPERAND_SDDMA : 232 print_keyword (cd, info, & epiphany_cgen_opval_crdma_names, fields->f_sd6, 0|(1<<CGEN_OPERAND_VIRTUAL)); 233 break; 234 case EPIPHANY_OPERAND_SDMEM : 235 print_keyword (cd, info, & epiphany_cgen_opval_crmem_names, fields->f_sd6, 0|(1<<CGEN_OPERAND_VIRTUAL)); 236 break; 237 case EPIPHANY_OPERAND_SDMESH : 238 print_keyword (cd, info, & epiphany_cgen_opval_crmesh_names, fields->f_sd6, 0|(1<<CGEN_OPERAND_VIRTUAL)); 239 break; 240 case EPIPHANY_OPERAND_SHIFT : 241 print_normal (cd, info, fields->f_shift, 0, pc, length); 242 break; 243 case EPIPHANY_OPERAND_SIMM11 : 244 print_simm_not_reg (cd, info, fields->f_sdisp11, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_VIRTUAL), pc, length); 245 break; 246 case EPIPHANY_OPERAND_SIMM24 : 247 print_address (cd, info, fields->f_simm24, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); 248 break; 249 case EPIPHANY_OPERAND_SIMM3 : 250 print_simm_not_reg (cd, info, fields->f_sdisp3, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_RELAX), pc, length); 251 break; 252 case EPIPHANY_OPERAND_SIMM8 : 253 print_address (cd, info, fields->f_simm8, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); 254 break; 255 case EPIPHANY_OPERAND_SN : 256 print_keyword (cd, info, & epiphany_cgen_opval_cr_names, fields->f_sn, 0); 257 break; 258 case EPIPHANY_OPERAND_SN6 : 259 print_keyword (cd, info, & epiphany_cgen_opval_cr_names, fields->f_sn6, 0|(1<<CGEN_OPERAND_VIRTUAL)); 260 break; 261 case EPIPHANY_OPERAND_SNDMA : 262 print_keyword (cd, info, & epiphany_cgen_opval_crdma_names, fields->f_sn6, 0|(1<<CGEN_OPERAND_VIRTUAL)); 263 break; 264 case EPIPHANY_OPERAND_SNMEM : 265 print_keyword (cd, info, & epiphany_cgen_opval_crmem_names, fields->f_sn6, 0|(1<<CGEN_OPERAND_VIRTUAL)); 266 break; 267 case EPIPHANY_OPERAND_SNMESH : 268 print_keyword (cd, info, & epiphany_cgen_opval_crmesh_names, fields->f_sn6, 0|(1<<CGEN_OPERAND_VIRTUAL)); 269 break; 270 case EPIPHANY_OPERAND_SWI_NUM : 271 print_uimm_not_reg (cd, info, fields->f_trap_num, 0, pc, length); 272 break; 273 case EPIPHANY_OPERAND_TRAPNUM6 : 274 print_normal (cd, info, fields->f_trap_num, 0, pc, length); 275 break; 276 277 default : 278 /* xgettext:c-format */ 279 fprintf (stderr, _("Unrecognized field %d while printing insn.\n"), 280 opindex); 281 abort (); 282 } 283 } 284 285 cgen_print_fn * const epiphany_cgen_print_handlers[] = 286 { 287 print_insn_normal, 288 }; 289 290 291 void 292 epiphany_cgen_init_dis (CGEN_CPU_DESC cd) 293 { 294 epiphany_cgen_init_opcode_table (cd); 295 epiphany_cgen_init_ibld_table (cd); 296 cd->print_handlers = & epiphany_cgen_print_handlers[0]; 297 cd->print_operand = epiphany_cgen_print_operand; 298 } 299 300 301 /* Default print handler. */ 303 304 static void 305 print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 306 void *dis_info, 307 long value, 308 unsigned int attrs, 309 bfd_vma pc ATTRIBUTE_UNUSED, 310 int length ATTRIBUTE_UNUSED) 311 { 312 disassemble_info *info = (disassemble_info *) dis_info; 313 314 /* Print the operand as directed by the attributes. */ 315 if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) 316 ; /* nothing to do */ 317 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) 318 (*info->fprintf_func) (info->stream, "%ld", value); 319 else 320 (*info->fprintf_func) (info->stream, "0x%lx", value); 321 } 322 323 /* Default address handler. */ 324 325 static void 326 print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 327 void *dis_info, 328 bfd_vma value, 329 unsigned int attrs, 330 bfd_vma pc ATTRIBUTE_UNUSED, 331 int length ATTRIBUTE_UNUSED) 332 { 333 disassemble_info *info = (disassemble_info *) dis_info; 334 335 /* Print the operand as directed by the attributes. */ 336 if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) 337 ; /* Nothing to do. */ 338 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR)) 339 (*info->print_address_func) (value, info); 340 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR)) 341 (*info->print_address_func) (value, info); 342 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) 343 (*info->fprintf_func) (info->stream, "%ld", (long) value); 344 else 345 (*info->fprintf_func) (info->stream, "0x%lx", (long) value); 346 } 347 348 /* Keyword print handler. */ 349 350 static void 351 print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 352 void *dis_info, 353 CGEN_KEYWORD *keyword_table, 354 long value, 355 unsigned int attrs ATTRIBUTE_UNUSED) 356 { 357 disassemble_info *info = (disassemble_info *) dis_info; 358 const CGEN_KEYWORD_ENTRY *ke; 359 360 ke = cgen_keyword_lookup_value (keyword_table, value); 361 if (ke != NULL) 362 (*info->fprintf_func) (info->stream, "%s", ke->name); 363 else 364 (*info->fprintf_func) (info->stream, "???"); 365 } 366 367 /* Default insn printer. 369 370 DIS_INFO is defined as `void *' so the disassembler needn't know anything 371 about disassemble_info. */ 372 373 static void 374 print_insn_normal (CGEN_CPU_DESC cd, 375 void *dis_info, 376 const CGEN_INSN *insn, 377 CGEN_FIELDS *fields, 378 bfd_vma pc, 379 int length) 380 { 381 const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); 382 disassemble_info *info = (disassemble_info *) dis_info; 383 const CGEN_SYNTAX_CHAR_TYPE *syn; 384 385 CGEN_INIT_PRINT (cd); 386 387 for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) 388 { 389 if (CGEN_SYNTAX_MNEMONIC_P (*syn)) 390 { 391 (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn)); 392 continue; 393 } 394 if (CGEN_SYNTAX_CHAR_P (*syn)) 395 { 396 (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn)); 397 continue; 398 } 399 400 /* We have an operand. */ 401 epiphany_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info, 402 fields, CGEN_INSN_ATTRS (insn), pc, length); 403 } 404 } 405 406 /* Subroutine of print_insn. Reads an insn into the given buffers and updates 408 the extract info. 409 Returns 0 if all is well, non-zero otherwise. */ 410 411 static int 412 read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 413 bfd_vma pc, 414 disassemble_info *info, 415 bfd_byte *buf, 416 int buflen, 417 CGEN_EXTRACT_INFO *ex_info, 418 unsigned long *insn_value) 419 { 420 int status = (*info->read_memory_func) (pc, buf, buflen, info); 421 422 if (status != 0) 423 { 424 (*info->memory_error_func) (status, pc, info); 425 return -1; 426 } 427 428 ex_info->dis_info = info; 429 ex_info->valid = (1 << buflen) - 1; 430 ex_info->insn_bytes = buf; 431 432 *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG); 433 return 0; 434 } 435 436 /* Utility to print an insn. 437 BUF is the base part of the insn, target byte order, BUFLEN bytes long. 438 The result is the size of the insn in bytes or zero for an unknown insn 439 or -1 if an error occurs fetching data (memory_error_func will have 440 been called). */ 441 442 static int 443 print_insn (CGEN_CPU_DESC cd, 444 bfd_vma pc, 445 disassemble_info *info, 446 bfd_byte *buf, 447 unsigned int buflen) 448 { 449 CGEN_INSN_INT insn_value; 450 const CGEN_INSN_LIST *insn_list; 451 CGEN_EXTRACT_INFO ex_info; 452 int basesize; 453 454 /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ 455 basesize = cd->base_insn_bitsize < buflen * 8 ? 456 cd->base_insn_bitsize : buflen * 8; 457 insn_value = cgen_get_insn_value (cd, buf, basesize); 458 459 460 /* Fill in ex_info fields like read_insn would. Don't actually call 461 read_insn, since the incoming buffer is already read (and possibly 462 modified a la m32r). */ 463 ex_info.valid = (1 << buflen) - 1; 464 ex_info.dis_info = info; 465 ex_info.insn_bytes = buf; 466 467 /* The instructions are stored in hash lists. 468 Pick the first one and keep trying until we find the right one. */ 469 470 insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value); 471 while (insn_list != NULL) 472 { 473 const CGEN_INSN *insn = insn_list->insn; 474 CGEN_FIELDS fields; 475 int length; 476 unsigned long insn_value_cropped; 477 478 #ifdef CGEN_VALIDATE_INSN_SUPPORTED 479 /* Not needed as insn shouldn't be in hash lists if not supported. */ 480 /* Supported by this cpu? */ 481 if (! epiphany_cgen_insn_supported (cd, insn)) 482 { 483 insn_list = CGEN_DIS_NEXT_INSN (insn_list); 484 continue; 485 } 486 #endif 487 488 /* Basic bit mask must be correct. */ 489 /* ??? May wish to allow target to defer this check until the extract 490 handler. */ 491 492 /* Base size may exceed this instruction's size. Extract the 493 relevant part from the buffer. */ 494 if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen && 495 (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) 496 insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn), 497 info->endian == BFD_ENDIAN_BIG); 498 else 499 insn_value_cropped = insn_value; 500 501 if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn)) 502 == CGEN_INSN_BASE_VALUE (insn)) 503 { 504 /* Printing is handled in two passes. The first pass parses the 505 machine insn and extracts the fields. The second pass prints 506 them. */ 507 508 /* Make sure the entire insn is loaded into insn_value, if it 509 can fit. */ 510 if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) && 511 (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) 512 { 513 unsigned long full_insn_value; 514 int rc = read_insn (cd, pc, info, buf, 515 CGEN_INSN_BITSIZE (insn) / 8, 516 & ex_info, & full_insn_value); 517 if (rc != 0) 518 return rc; 519 length = CGEN_EXTRACT_FN (cd, insn) 520 (cd, insn, &ex_info, full_insn_value, &fields, pc); 521 } 522 else 523 length = CGEN_EXTRACT_FN (cd, insn) 524 (cd, insn, &ex_info, insn_value_cropped, &fields, pc); 525 526 /* Length < 0 -> error. */ 527 if (length < 0) 528 return length; 529 if (length > 0) 530 { 531 CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length); 532 /* Length is in bits, result is in bytes. */ 533 return length / 8; 534 } 535 } 536 537 insn_list = CGEN_DIS_NEXT_INSN (insn_list); 538 } 539 540 return 0; 541 } 542 543 /* Default value for CGEN_PRINT_INSN. 544 The result is the size of the insn in bytes or zero for an unknown insn 545 or -1 if an error occured fetching bytes. */ 546 547 #ifndef CGEN_PRINT_INSN 548 #define CGEN_PRINT_INSN default_print_insn 549 #endif 550 551 static int 552 default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) 553 { 554 bfd_byte buf[CGEN_MAX_INSN_SIZE]; 555 int buflen; 556 int status; 557 558 /* Attempt to read the base part of the insn. */ 559 buflen = cd->base_insn_bitsize / 8; 560 status = (*info->read_memory_func) (pc, buf, buflen, info); 561 562 /* Try again with the minimum part, if min < base. */ 563 if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize)) 564 { 565 buflen = cd->min_insn_bitsize / 8; 566 status = (*info->read_memory_func) (pc, buf, buflen, info); 567 } 568 569 if (status != 0) 570 { 571 (*info->memory_error_func) (status, pc, info); 572 return -1; 573 } 574 575 return print_insn (cd, pc, info, buf, buflen); 576 } 577 578 /* Main entry point. 579 Print one instruction from PC on INFO->STREAM. 580 Return the size of the instruction (in bytes). */ 581 582 typedef struct cpu_desc_list 583 { 584 struct cpu_desc_list *next; 585 CGEN_BITSET *isa; 586 int mach; 587 int endian; 588 CGEN_CPU_DESC cd; 589 } cpu_desc_list; 590 591 int 592 print_insn_epiphany (bfd_vma pc, disassemble_info *info) 593 { 594 static cpu_desc_list *cd_list = 0; 595 cpu_desc_list *cl = 0; 596 static CGEN_CPU_DESC cd = 0; 597 static CGEN_BITSET *prev_isa; 598 static int prev_mach; 599 static int prev_endian; 600 int length; 601 CGEN_BITSET *isa; 602 int mach; 603 int endian = (info->endian == BFD_ENDIAN_BIG 604 ? CGEN_ENDIAN_BIG 605 : CGEN_ENDIAN_LITTLE); 606 enum bfd_architecture arch; 607 608 /* ??? gdb will set mach but leave the architecture as "unknown" */ 609 #ifndef CGEN_BFD_ARCH 610 #define CGEN_BFD_ARCH bfd_arch_epiphany 611 #endif 612 arch = info->arch; 613 if (arch == bfd_arch_unknown) 614 arch = CGEN_BFD_ARCH; 615 616 /* There's no standard way to compute the machine or isa number 617 so we leave it to the target. */ 618 #ifdef CGEN_COMPUTE_MACH 619 mach = CGEN_COMPUTE_MACH (info); 620 #else 621 mach = info->mach; 622 #endif 623 624 #ifdef CGEN_COMPUTE_ISA 625 { 626 static CGEN_BITSET *permanent_isa; 627 628 if (!permanent_isa) 629 permanent_isa = cgen_bitset_create (MAX_ISAS); 630 isa = permanent_isa; 631 cgen_bitset_clear (isa); 632 cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info)); 633 } 634 #else 635 isa = info->insn_sets; 636 #endif 637 638 /* If we've switched cpu's, try to find a handle we've used before */ 639 if (cd 640 && (cgen_bitset_compare (isa, prev_isa) != 0 641 || mach != prev_mach 642 || endian != prev_endian)) 643 { 644 cd = 0; 645 for (cl = cd_list; cl; cl = cl->next) 646 { 647 if (cgen_bitset_compare (cl->isa, isa) == 0 && 648 cl->mach == mach && 649 cl->endian == endian) 650 { 651 cd = cl->cd; 652 prev_isa = cd->isas; 653 break; 654 } 655 } 656 } 657 658 /* If we haven't initialized yet, initialize the opcode table. */ 659 if (! cd) 660 { 661 const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach); 662 const char *mach_name; 663 664 if (!arch_type) 665 abort (); 666 mach_name = arch_type->printable_name; 667 668 prev_isa = cgen_bitset_copy (isa); 669 prev_mach = mach; 670 prev_endian = endian; 671 cd = epiphany_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, 672 CGEN_CPU_OPEN_BFDMACH, mach_name, 673 CGEN_CPU_OPEN_ENDIAN, prev_endian, 674 CGEN_CPU_OPEN_END); 675 if (!cd) 676 abort (); 677 678 /* Save this away for future reference. */ 679 cl = xmalloc (sizeof (struct cpu_desc_list)); 680 cl->cd = cd; 681 cl->isa = prev_isa; 682 cl->mach = mach; 683 cl->endian = endian; 684 cl->next = cd_list; 685 cd_list = cl; 686 687 epiphany_cgen_init_dis (cd); 688 } 689 690 /* We try to have as much common code as possible. 691 But at this point some targets need to take over. */ 692 /* ??? Some targets may need a hook elsewhere. Try to avoid this, 693 but if not possible try to move this hook elsewhere rather than 694 have two hooks. */ 695 length = CGEN_PRINT_INSN (cd, pc, info); 696 if (length > 0) 697 return length; 698 if (length < 0) 699 return -1; 700 701 (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); 702 return cd->default_insn_bitsize / 8; 703 } 704
