1 /* Instruction building/extraction support for m32r. -*- C -*- 2 3 THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. 4 - the resultant file is machine generated, cgen-ibld.in isn't 5 6 Copyright (C) 1996-2016 Free Software Foundation, Inc. 7 8 This file is part of libopcodes. 9 10 This library is free software; you can redistribute it and/or modify 11 it under the terms of the GNU General Public License as published by 12 the Free Software Foundation; either version 3, or (at your option) 13 any later version. 14 15 It is distributed in the hope that it will be useful, but WITHOUT 16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 18 License for more details. 19 20 You should have received a copy of the GNU General Public License 21 along with this program; if not, write to the Free Software Foundation, Inc., 22 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ 23 24 /* ??? Eventually more and more of this stuff can go to cpu-independent files. 25 Keep that in mind. */ 26 27 #include "sysdep.h" 28 #include <stdio.h> 29 #include "ansidecl.h" 30 #include "dis-asm.h" 31 #include "bfd.h" 32 #include "symcat.h" 33 #include "m32r-desc.h" 34 #include "m32r-opc.h" 35 #include "cgen/basic-modes.h" 36 #include "opintl.h" 37 #include "safe-ctype.h" 38 39 #undef min 40 #define min(a,b) ((a) < (b) ? (a) : (b)) 41 #undef max 42 #define max(a,b) ((a) > (b) ? (a) : (b)) 43 44 /* Used by the ifield rtx function. */ 45 #define FLD(f) (fields->f) 46 47 static const char * insert_normal 48 (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int, 49 unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR); 50 static const char * insert_insn_normal 51 (CGEN_CPU_DESC, const CGEN_INSN *, 52 CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); 53 static int extract_normal 54 (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, 55 unsigned int, unsigned int, unsigned int, unsigned int, 56 unsigned int, unsigned int, bfd_vma, long *); 57 static int extract_insn_normal 58 (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, 59 CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); 60 #if CGEN_INT_INSN_P 61 static void put_insn_int_value 62 (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT); 63 #endif 64 #if ! CGEN_INT_INSN_P 65 static CGEN_INLINE void insert_1 66 (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *); 67 static CGEN_INLINE int fill_cache 68 (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma); 69 static CGEN_INLINE long extract_1 70 (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma); 71 #endif 72 73 /* Operand insertion. */ 75 76 #if ! CGEN_INT_INSN_P 77 78 /* Subroutine of insert_normal. */ 79 80 static CGEN_INLINE void 81 insert_1 (CGEN_CPU_DESC cd, 82 unsigned long value, 83 int start, 84 int length, 85 int word_length, 86 unsigned char *bufp) 87 { 88 unsigned long x,mask; 89 int shift; 90 91 x = cgen_get_insn_value (cd, bufp, word_length); 92 93 /* Written this way to avoid undefined behaviour. */ 94 mask = (((1L << (length - 1)) - 1) << 1) | 1; 95 if (CGEN_INSN_LSB0_P) 96 shift = (start + 1) - length; 97 else 98 shift = (word_length - (start + length)); 99 x = (x & ~(mask << shift)) | ((value & mask) << shift); 100 101 cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); 102 } 103 104 #endif /* ! CGEN_INT_INSN_P */ 105 106 /* Default insertion routine. 107 108 ATTRS is a mask of the boolean attributes. 109 WORD_OFFSET is the offset in bits from the start of the insn of the value. 110 WORD_LENGTH is the length of the word in bits in which the value resides. 111 START is the starting bit number in the word, architecture origin. 112 LENGTH is the length of VALUE in bits. 113 TOTAL_LENGTH is the total length of the insn in bits. 114 115 The result is an error message or NULL if success. */ 116 117 /* ??? This duplicates functionality with bfd's howto table and 118 bfd_install_relocation. */ 119 /* ??? This doesn't handle bfd_vma's. Create another function when 120 necessary. */ 121 122 static const char * 123 insert_normal (CGEN_CPU_DESC cd, 124 long value, 125 unsigned int attrs, 126 unsigned int word_offset, 127 unsigned int start, 128 unsigned int length, 129 unsigned int word_length, 130 unsigned int total_length, 131 CGEN_INSN_BYTES_PTR buffer) 132 { 133 static char errbuf[100]; 134 /* Written this way to avoid undefined behaviour. */ 135 unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1; 136 137 /* If LENGTH is zero, this operand doesn't contribute to the value. */ 138 if (length == 0) 139 return NULL; 140 141 if (word_length > 8 * sizeof (CGEN_INSN_INT)) 142 abort (); 143 144 /* For architectures with insns smaller than the base-insn-bitsize, 145 word_length may be too big. */ 146 if (cd->min_insn_bitsize < cd->base_insn_bitsize) 147 { 148 if (word_offset == 0 149 && word_length > total_length) 150 word_length = total_length; 151 } 152 153 /* Ensure VALUE will fit. */ 154 if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT)) 155 { 156 long minval = - (1L << (length - 1)); 157 unsigned long maxval = mask; 158 159 if ((value > 0 && (unsigned long) value > maxval) 160 || value < minval) 161 { 162 /* xgettext:c-format */ 163 sprintf (errbuf, 164 _("operand out of range (%ld not between %ld and %lu)"), 165 value, minval, maxval); 166 return errbuf; 167 } 168 } 169 else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)) 170 { 171 unsigned long maxval = mask; 172 unsigned long val = (unsigned long) value; 173 174 /* For hosts with a word size > 32 check to see if value has been sign 175 extended beyond 32 bits. If so then ignore these higher sign bits 176 as the user is attempting to store a 32-bit signed value into an 177 unsigned 32-bit field which is allowed. */ 178 if (sizeof (unsigned long) > 4 && ((value >> 32) == -1)) 179 val &= 0xFFFFFFFF; 180 181 if (val > maxval) 182 { 183 /* xgettext:c-format */ 184 sprintf (errbuf, 185 _("operand out of range (0x%lx not between 0 and 0x%lx)"), 186 val, maxval); 187 return errbuf; 188 } 189 } 190 else 191 { 192 if (! cgen_signed_overflow_ok_p (cd)) 193 { 194 long minval = - (1L << (length - 1)); 195 long maxval = (1L << (length - 1)) - 1; 196 197 if (value < minval || value > maxval) 198 { 199 sprintf 200 /* xgettext:c-format */ 201 (errbuf, _("operand out of range (%ld not between %ld and %ld)"), 202 value, minval, maxval); 203 return errbuf; 204 } 205 } 206 } 207 208 #if CGEN_INT_INSN_P 209 210 { 211 int shift_within_word, shift_to_word, shift; 212 213 /* How to shift the value to BIT0 of the word. */ 214 shift_to_word = total_length - (word_offset + word_length); 215 216 /* How to shift the value to the field within the word. */ 217 if (CGEN_INSN_LSB0_P) 218 shift_within_word = start + 1 - length; 219 else 220 shift_within_word = word_length - start - length; 221 222 /* The total SHIFT, then mask in the value. */ 223 shift = shift_to_word + shift_within_word; 224 *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift); 225 } 226 227 #else /* ! CGEN_INT_INSN_P */ 228 229 { 230 unsigned char *bufp = (unsigned char *) buffer + word_offset / 8; 231 232 insert_1 (cd, value, start, length, word_length, bufp); 233 } 234 235 #endif /* ! CGEN_INT_INSN_P */ 236 237 return NULL; 238 } 239 240 /* Default insn builder (insert handler). 241 The instruction is recorded in CGEN_INT_INSN_P byte order (meaning 242 that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is 243 recorded in host byte order, otherwise BUFFER is an array of bytes 244 and the value is recorded in target byte order). 245 The result is an error message or NULL if success. */ 246 247 static const char * 248 insert_insn_normal (CGEN_CPU_DESC cd, 249 const CGEN_INSN * insn, 250 CGEN_FIELDS * fields, 251 CGEN_INSN_BYTES_PTR buffer, 252 bfd_vma pc) 253 { 254 const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); 255 unsigned long value; 256 const CGEN_SYNTAX_CHAR_TYPE * syn; 257 258 CGEN_INIT_INSERT (cd); 259 value = CGEN_INSN_BASE_VALUE (insn); 260 261 /* If we're recording insns as numbers (rather than a string of bytes), 262 target byte order handling is deferred until later. */ 263 264 #if CGEN_INT_INSN_P 265 266 put_insn_int_value (cd, buffer, cd->base_insn_bitsize, 267 CGEN_FIELDS_BITSIZE (fields), value); 268 269 #else 270 271 cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, 272 (unsigned) CGEN_FIELDS_BITSIZE (fields)), 273 value); 274 275 #endif /* ! CGEN_INT_INSN_P */ 276 277 /* ??? It would be better to scan the format's fields. 278 Still need to be able to insert a value based on the operand though; 279 e.g. storing a branch displacement that got resolved later. 280 Needs more thought first. */ 281 282 for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn) 283 { 284 const char *errmsg; 285 286 if (CGEN_SYNTAX_CHAR_P (* syn)) 287 continue; 288 289 errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn), 290 fields, buffer, pc); 291 if (errmsg) 292 return errmsg; 293 } 294 295 return NULL; 296 } 297 298 #if CGEN_INT_INSN_P 299 /* Cover function to store an insn value into an integral insn. Must go here 300 because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */ 301 302 static void 303 put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 304 CGEN_INSN_BYTES_PTR buf, 305 int length, 306 int insn_length, 307 CGEN_INSN_INT value) 308 { 309 /* For architectures with insns smaller than the base-insn-bitsize, 310 length may be too big. */ 311 if (length > insn_length) 312 *buf = value; 313 else 314 { 315 int shift = insn_length - length; 316 /* Written this way to avoid undefined behaviour. */ 317 CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1; 318 319 *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift); 320 } 321 } 322 #endif 323 324 /* Operand extraction. */ 326 327 #if ! CGEN_INT_INSN_P 328 329 /* Subroutine of extract_normal. 330 Ensure sufficient bytes are cached in EX_INFO. 331 OFFSET is the offset in bytes from the start of the insn of the value. 332 BYTES is the length of the needed value. 333 Returns 1 for success, 0 for failure. */ 334 335 static CGEN_INLINE int 336 fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 337 CGEN_EXTRACT_INFO *ex_info, 338 int offset, 339 int bytes, 340 bfd_vma pc) 341 { 342 /* It's doubtful that the middle part has already been fetched so 343 we don't optimize that case. kiss. */ 344 unsigned int mask; 345 disassemble_info *info = (disassemble_info *) ex_info->dis_info; 346 347 /* First do a quick check. */ 348 mask = (1 << bytes) - 1; 349 if (((ex_info->valid >> offset) & mask) == mask) 350 return 1; 351 352 /* Search for the first byte we need to read. */ 353 for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1) 354 if (! (mask & ex_info->valid)) 355 break; 356 357 if (bytes) 358 { 359 int status; 360 361 pc += offset; 362 status = (*info->read_memory_func) 363 (pc, ex_info->insn_bytes + offset, bytes, info); 364 365 if (status != 0) 366 { 367 (*info->memory_error_func) (status, pc, info); 368 return 0; 369 } 370 371 ex_info->valid |= ((1 << bytes) - 1) << offset; 372 } 373 374 return 1; 375 } 376 377 /* Subroutine of extract_normal. */ 378 379 static CGEN_INLINE long 380 extract_1 (CGEN_CPU_DESC cd, 381 CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, 382 int start, 383 int length, 384 int word_length, 385 unsigned char *bufp, 386 bfd_vma pc ATTRIBUTE_UNUSED) 387 { 388 unsigned long x; 389 int shift; 390 391 x = cgen_get_insn_value (cd, bufp, word_length); 392 393 if (CGEN_INSN_LSB0_P) 394 shift = (start + 1) - length; 395 else 396 shift = (word_length - (start + length)); 397 return x >> shift; 398 } 399 400 #endif /* ! CGEN_INT_INSN_P */ 401 402 /* Default extraction routine. 403 404 INSN_VALUE is the first base_insn_bitsize bits of the insn in host order, 405 or sometimes less for cases like the m32r where the base insn size is 32 406 but some insns are 16 bits. 407 ATTRS is a mask of the boolean attributes. We only need `SIGNED', 408 but for generality we take a bitmask of all of them. 409 WORD_OFFSET is the offset in bits from the start of the insn of the value. 410 WORD_LENGTH is the length of the word in bits in which the value resides. 411 START is the starting bit number in the word, architecture origin. 412 LENGTH is the length of VALUE in bits. 413 TOTAL_LENGTH is the total length of the insn in bits. 414 415 Returns 1 for success, 0 for failure. */ 416 417 /* ??? The return code isn't properly used. wip. */ 418 419 /* ??? This doesn't handle bfd_vma's. Create another function when 420 necessary. */ 421 422 static int 423 extract_normal (CGEN_CPU_DESC cd, 424 #if ! CGEN_INT_INSN_P 425 CGEN_EXTRACT_INFO *ex_info, 426 #else 427 CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, 428 #endif 429 CGEN_INSN_INT insn_value, 430 unsigned int attrs, 431 unsigned int word_offset, 432 unsigned int start, 433 unsigned int length, 434 unsigned int word_length, 435 unsigned int total_length, 436 #if ! CGEN_INT_INSN_P 437 bfd_vma pc, 438 #else 439 bfd_vma pc ATTRIBUTE_UNUSED, 440 #endif 441 long *valuep) 442 { 443 long value, mask; 444 445 /* If LENGTH is zero, this operand doesn't contribute to the value 446 so give it a standard value of zero. */ 447 if (length == 0) 448 { 449 *valuep = 0; 450 return 1; 451 } 452 453 if (word_length > 8 * sizeof (CGEN_INSN_INT)) 454 abort (); 455 456 /* For architectures with insns smaller than the insn-base-bitsize, 457 word_length may be too big. */ 458 if (cd->min_insn_bitsize < cd->base_insn_bitsize) 459 { 460 if (word_offset + word_length > total_length) 461 word_length = total_length - word_offset; 462 } 463 464 /* Does the value reside in INSN_VALUE, and at the right alignment? */ 465 466 if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length)) 467 { 468 if (CGEN_INSN_LSB0_P) 469 value = insn_value >> ((word_offset + start + 1) - length); 470 else 471 value = insn_value >> (total_length - ( word_offset + start + length)); 472 } 473 474 #if ! CGEN_INT_INSN_P 475 476 else 477 { 478 unsigned char *bufp = ex_info->insn_bytes + word_offset / 8; 479 480 if (word_length > 8 * sizeof (CGEN_INSN_INT)) 481 abort (); 482 483 if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0) 484 return 0; 485 486 value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc); 487 } 488 489 #endif /* ! CGEN_INT_INSN_P */ 490 491 /* Written this way to avoid undefined behaviour. */ 492 mask = (((1L << (length - 1)) - 1) << 1) | 1; 493 494 value &= mask; 495 /* sign extend? */ 496 if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED) 497 && (value & (1L << (length - 1)))) 498 value |= ~mask; 499 500 *valuep = value; 501 502 return 1; 503 } 504 505 /* Default insn extractor. 506 507 INSN_VALUE is the first base_insn_bitsize bits, translated to host order. 508 The extracted fields are stored in FIELDS. 509 EX_INFO is used to handle reading variable length insns. 510 Return the length of the insn in bits, or 0 if no match, 511 or -1 if an error occurs fetching data (memory_error_func will have 512 been called). */ 513 514 static int 515 extract_insn_normal (CGEN_CPU_DESC cd, 516 const CGEN_INSN *insn, 517 CGEN_EXTRACT_INFO *ex_info, 518 CGEN_INSN_INT insn_value, 519 CGEN_FIELDS *fields, 520 bfd_vma pc) 521 { 522 const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); 523 const CGEN_SYNTAX_CHAR_TYPE *syn; 524 525 CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); 526 527 CGEN_INIT_EXTRACT (cd); 528 529 for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) 530 { 531 int length; 532 533 if (CGEN_SYNTAX_CHAR_P (*syn)) 534 continue; 535 536 length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn), 537 ex_info, insn_value, fields, pc); 538 if (length <= 0) 539 return length; 540 } 541 542 /* We recognized and successfully extracted this insn. */ 543 return CGEN_INSN_BITSIZE (insn); 544 } 545 546 /* Machine generated code added here. */ 548 549 const char * m32r_cgen_insert_operand 550 (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); 551 552 /* Main entry point for operand insertion. 553 554 This function is basically just a big switch statement. Earlier versions 555 used tables to look up the function to use, but 556 - if the table contains both assembler and disassembler functions then 557 the disassembler contains much of the assembler and vice-versa, 558 - there's a lot of inlining possibilities as things grow, 559 - using a switch statement avoids the function call overhead. 560 561 This function could be moved into `parse_insn_normal', but keeping it 562 separate makes clear the interface between `parse_insn_normal' and each of 563 the handlers. It's also needed by GAS to insert operands that couldn't be 564 resolved during parsing. */ 565 566 const char * 567 m32r_cgen_insert_operand (CGEN_CPU_DESC cd, 568 int opindex, 569 CGEN_FIELDS * fields, 570 CGEN_INSN_BYTES_PTR buffer, 571 bfd_vma pc ATTRIBUTE_UNUSED) 572 { 573 const char * errmsg = NULL; 574 unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); 575 576 switch (opindex) 577 { 578 case M32R_OPERAND_ACC : 579 errmsg = insert_normal (cd, fields->f_acc, 0, 0, 8, 1, 32, total_length, buffer); 580 break; 581 case M32R_OPERAND_ACCD : 582 errmsg = insert_normal (cd, fields->f_accd, 0, 0, 4, 2, 32, total_length, buffer); 583 break; 584 case M32R_OPERAND_ACCS : 585 errmsg = insert_normal (cd, fields->f_accs, 0, 0, 12, 2, 32, total_length, buffer); 586 break; 587 case M32R_OPERAND_DCR : 588 errmsg = insert_normal (cd, fields->f_r1, 0, 0, 4, 4, 32, total_length, buffer); 589 break; 590 case M32R_OPERAND_DISP16 : 591 { 592 long value = fields->f_disp16; 593 value = ((SI) (((value) - (pc))) >> (2)); 594 errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 16, 16, 32, total_length, buffer); 595 } 596 break; 597 case M32R_OPERAND_DISP24 : 598 { 599 long value = fields->f_disp24; 600 value = ((SI) (((value) - (pc))) >> (2)); 601 errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 24, 32, total_length, buffer); 602 } 603 break; 604 case M32R_OPERAND_DISP8 : 605 { 606 long value = fields->f_disp8; 607 value = ((SI) (((value) - (((pc) & (-4))))) >> (2)); 608 errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 8, 32, total_length, buffer); 609 } 610 break; 611 case M32R_OPERAND_DR : 612 errmsg = insert_normal (cd, fields->f_r1, 0, 0, 4, 4, 32, total_length, buffer); 613 break; 614 case M32R_OPERAND_HASH : 615 break; 616 case M32R_OPERAND_HI16 : 617 errmsg = insert_normal (cd, fields->f_hi16, 0|(1<<CGEN_IFLD_SIGN_OPT), 0, 16, 16, 32, total_length, buffer); 618 break; 619 case M32R_OPERAND_IMM1 : 620 { 621 long value = fields->f_imm1; 622 value = ((value) - (1)); 623 errmsg = insert_normal (cd, value, 0, 0, 15, 1, 32, total_length, buffer); 624 } 625 break; 626 case M32R_OPERAND_SCR : 627 errmsg = insert_normal (cd, fields->f_r2, 0, 0, 12, 4, 32, total_length, buffer); 628 break; 629 case M32R_OPERAND_SIMM16 : 630 errmsg = insert_normal (cd, fields->f_simm16, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 16, 32, total_length, buffer); 631 break; 632 case M32R_OPERAND_SIMM8 : 633 errmsg = insert_normal (cd, fields->f_simm8, 0|(1<<CGEN_IFLD_SIGNED), 0, 8, 8, 32, total_length, buffer); 634 break; 635 case M32R_OPERAND_SLO16 : 636 errmsg = insert_normal (cd, fields->f_simm16, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 16, 32, total_length, buffer); 637 break; 638 case M32R_OPERAND_SR : 639 errmsg = insert_normal (cd, fields->f_r2, 0, 0, 12, 4, 32, total_length, buffer); 640 break; 641 case M32R_OPERAND_SRC1 : 642 errmsg = insert_normal (cd, fields->f_r1, 0, 0, 4, 4, 32, total_length, buffer); 643 break; 644 case M32R_OPERAND_SRC2 : 645 errmsg = insert_normal (cd, fields->f_r2, 0, 0, 12, 4, 32, total_length, buffer); 646 break; 647 case M32R_OPERAND_UIMM16 : 648 errmsg = insert_normal (cd, fields->f_uimm16, 0, 0, 16, 16, 32, total_length, buffer); 649 break; 650 case M32R_OPERAND_UIMM24 : 651 errmsg = insert_normal (cd, fields->f_uimm24, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_ABS_ADDR), 0, 8, 24, 32, total_length, buffer); 652 break; 653 case M32R_OPERAND_UIMM3 : 654 errmsg = insert_normal (cd, fields->f_uimm3, 0, 0, 5, 3, 32, total_length, buffer); 655 break; 656 case M32R_OPERAND_UIMM4 : 657 errmsg = insert_normal (cd, fields->f_uimm4, 0, 0, 12, 4, 32, total_length, buffer); 658 break; 659 case M32R_OPERAND_UIMM5 : 660 errmsg = insert_normal (cd, fields->f_uimm5, 0, 0, 11, 5, 32, total_length, buffer); 661 break; 662 case M32R_OPERAND_UIMM8 : 663 errmsg = insert_normal (cd, fields->f_uimm8, 0, 0, 8, 8, 32, total_length, buffer); 664 break; 665 case M32R_OPERAND_ULO16 : 666 errmsg = insert_normal (cd, fields->f_uimm16, 0, 0, 16, 16, 32, total_length, buffer); 667 break; 668 669 default : 670 /* xgettext:c-format */ 671 fprintf (stderr, _("Unrecognized field %d while building insn.\n"), 672 opindex); 673 abort (); 674 } 675 676 return errmsg; 677 } 678 679 int m32r_cgen_extract_operand 680 (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); 681 682 /* Main entry point for operand extraction. 683 The result is <= 0 for error, >0 for success. 684 ??? Actual values aren't well defined right now. 685 686 This function is basically just a big switch statement. Earlier versions 687 used tables to look up the function to use, but 688 - if the table contains both assembler and disassembler functions then 689 the disassembler contains much of the assembler and vice-versa, 690 - there's a lot of inlining possibilities as things grow, 691 - using a switch statement avoids the function call overhead. 692 693 This function could be moved into `print_insn_normal', but keeping it 694 separate makes clear the interface between `print_insn_normal' and each of 695 the handlers. */ 696 697 int 698 m32r_cgen_extract_operand (CGEN_CPU_DESC cd, 699 int opindex, 700 CGEN_EXTRACT_INFO *ex_info, 701 CGEN_INSN_INT insn_value, 702 CGEN_FIELDS * fields, 703 bfd_vma pc) 704 { 705 /* Assume success (for those operands that are nops). */ 706 int length = 1; 707 unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); 708 709 switch (opindex) 710 { 711 case M32R_OPERAND_ACC : 712 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 1, 32, total_length, pc, & fields->f_acc); 713 break; 714 case M32R_OPERAND_ACCD : 715 length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 2, 32, total_length, pc, & fields->f_accd); 716 break; 717 case M32R_OPERAND_ACCS : 718 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 2, 32, total_length, pc, & fields->f_accs); 719 break; 720 case M32R_OPERAND_DCR : 721 length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_r1); 722 break; 723 case M32R_OPERAND_DISP16 : 724 { 725 long value; 726 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 16, 16, 32, total_length, pc, & value); 727 value = ((((value) << (2))) + (pc)); 728 fields->f_disp16 = value; 729 } 730 break; 731 case M32R_OPERAND_DISP24 : 732 { 733 long value; 734 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 24, 32, total_length, pc, & value); 735 value = ((((value) << (2))) + (pc)); 736 fields->f_disp24 = value; 737 } 738 break; 739 case M32R_OPERAND_DISP8 : 740 { 741 long value; 742 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 8, 32, total_length, pc, & value); 743 value = ((((value) << (2))) + (((pc) & (-4)))); 744 fields->f_disp8 = value; 745 } 746 break; 747 case M32R_OPERAND_DR : 748 length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_r1); 749 break; 750 case M32R_OPERAND_HASH : 751 break; 752 case M32R_OPERAND_HI16 : 753 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGN_OPT), 0, 16, 16, 32, total_length, pc, & fields->f_hi16); 754 break; 755 case M32R_OPERAND_IMM1 : 756 { 757 long value; 758 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 1, 32, total_length, pc, & value); 759 value = ((value) + (1)); 760 fields->f_imm1 = value; 761 } 762 break; 763 case M32R_OPERAND_SCR : 764 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_r2); 765 break; 766 case M32R_OPERAND_SIMM16 : 767 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 16, 32, total_length, pc, & fields->f_simm16); 768 break; 769 case M32R_OPERAND_SIMM8 : 770 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 8, 8, 32, total_length, pc, & fields->f_simm8); 771 break; 772 case M32R_OPERAND_SLO16 : 773 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 16, 32, total_length, pc, & fields->f_simm16); 774 break; 775 case M32R_OPERAND_SR : 776 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_r2); 777 break; 778 case M32R_OPERAND_SRC1 : 779 length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_r1); 780 break; 781 case M32R_OPERAND_SRC2 : 782 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_r2); 783 break; 784 case M32R_OPERAND_UIMM16 : 785 length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & fields->f_uimm16); 786 break; 787 case M32R_OPERAND_UIMM24 : 788 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_ABS_ADDR), 0, 8, 24, 32, total_length, pc, & fields->f_uimm24); 789 break; 790 case M32R_OPERAND_UIMM3 : 791 length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 3, 32, total_length, pc, & fields->f_uimm3); 792 break; 793 case M32R_OPERAND_UIMM4 : 794 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_uimm4); 795 break; 796 case M32R_OPERAND_UIMM5 : 797 length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 5, 32, total_length, pc, & fields->f_uimm5); 798 break; 799 case M32R_OPERAND_UIMM8 : 800 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 32, total_length, pc, & fields->f_uimm8); 801 break; 802 case M32R_OPERAND_ULO16 : 803 length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & fields->f_uimm16); 804 break; 805 806 default : 807 /* xgettext:c-format */ 808 fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"), 809 opindex); 810 abort (); 811 } 812 813 return length; 814 } 815 816 cgen_insert_fn * const m32r_cgen_insert_handlers[] = 817 { 818 insert_insn_normal, 819 }; 820 821 cgen_extract_fn * const m32r_cgen_extract_handlers[] = 822 { 823 extract_insn_normal, 824 }; 825 826 int m32r_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); 827 bfd_vma m32r_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); 828 829 /* Getting values from cgen_fields is handled by a collection of functions. 830 They are distinguished by the type of the VALUE argument they return. 831 TODO: floating point, inlining support, remove cases where result type 832 not appropriate. */ 833 834 int 835 m32r_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 836 int opindex, 837 const CGEN_FIELDS * fields) 838 { 839 int value; 840 841 switch (opindex) 842 { 843 case M32R_OPERAND_ACC : 844 value = fields->f_acc; 845 break; 846 case M32R_OPERAND_ACCD : 847 value = fields->f_accd; 848 break; 849 case M32R_OPERAND_ACCS : 850 value = fields->f_accs; 851 break; 852 case M32R_OPERAND_DCR : 853 value = fields->f_r1; 854 break; 855 case M32R_OPERAND_DISP16 : 856 value = fields->f_disp16; 857 break; 858 case M32R_OPERAND_DISP24 : 859 value = fields->f_disp24; 860 break; 861 case M32R_OPERAND_DISP8 : 862 value = fields->f_disp8; 863 break; 864 case M32R_OPERAND_DR : 865 value = fields->f_r1; 866 break; 867 case M32R_OPERAND_HASH : 868 value = 0; 869 break; 870 case M32R_OPERAND_HI16 : 871 value = fields->f_hi16; 872 break; 873 case M32R_OPERAND_IMM1 : 874 value = fields->f_imm1; 875 break; 876 case M32R_OPERAND_SCR : 877 value = fields->f_r2; 878 break; 879 case M32R_OPERAND_SIMM16 : 880 value = fields->f_simm16; 881 break; 882 case M32R_OPERAND_SIMM8 : 883 value = fields->f_simm8; 884 break; 885 case M32R_OPERAND_SLO16 : 886 value = fields->f_simm16; 887 break; 888 case M32R_OPERAND_SR : 889 value = fields->f_r2; 890 break; 891 case M32R_OPERAND_SRC1 : 892 value = fields->f_r1; 893 break; 894 case M32R_OPERAND_SRC2 : 895 value = fields->f_r2; 896 break; 897 case M32R_OPERAND_UIMM16 : 898 value = fields->f_uimm16; 899 break; 900 case M32R_OPERAND_UIMM24 : 901 value = fields->f_uimm24; 902 break; 903 case M32R_OPERAND_UIMM3 : 904 value = fields->f_uimm3; 905 break; 906 case M32R_OPERAND_UIMM4 : 907 value = fields->f_uimm4; 908 break; 909 case M32R_OPERAND_UIMM5 : 910 value = fields->f_uimm5; 911 break; 912 case M32R_OPERAND_UIMM8 : 913 value = fields->f_uimm8; 914 break; 915 case M32R_OPERAND_ULO16 : 916 value = fields->f_uimm16; 917 break; 918 919 default : 920 /* xgettext:c-format */ 921 fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"), 922 opindex); 923 abort (); 924 } 925 926 return value; 927 } 928 929 bfd_vma 930 m32r_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 931 int opindex, 932 const CGEN_FIELDS * fields) 933 { 934 bfd_vma value; 935 936 switch (opindex) 937 { 938 case M32R_OPERAND_ACC : 939 value = fields->f_acc; 940 break; 941 case M32R_OPERAND_ACCD : 942 value = fields->f_accd; 943 break; 944 case M32R_OPERAND_ACCS : 945 value = fields->f_accs; 946 break; 947 case M32R_OPERAND_DCR : 948 value = fields->f_r1; 949 break; 950 case M32R_OPERAND_DISP16 : 951 value = fields->f_disp16; 952 break; 953 case M32R_OPERAND_DISP24 : 954 value = fields->f_disp24; 955 break; 956 case M32R_OPERAND_DISP8 : 957 value = fields->f_disp8; 958 break; 959 case M32R_OPERAND_DR : 960 value = fields->f_r1; 961 break; 962 case M32R_OPERAND_HASH : 963 value = 0; 964 break; 965 case M32R_OPERAND_HI16 : 966 value = fields->f_hi16; 967 break; 968 case M32R_OPERAND_IMM1 : 969 value = fields->f_imm1; 970 break; 971 case M32R_OPERAND_SCR : 972 value = fields->f_r2; 973 break; 974 case M32R_OPERAND_SIMM16 : 975 value = fields->f_simm16; 976 break; 977 case M32R_OPERAND_SIMM8 : 978 value = fields->f_simm8; 979 break; 980 case M32R_OPERAND_SLO16 : 981 value = fields->f_simm16; 982 break; 983 case M32R_OPERAND_SR : 984 value = fields->f_r2; 985 break; 986 case M32R_OPERAND_SRC1 : 987 value = fields->f_r1; 988 break; 989 case M32R_OPERAND_SRC2 : 990 value = fields->f_r2; 991 break; 992 case M32R_OPERAND_UIMM16 : 993 value = fields->f_uimm16; 994 break; 995 case M32R_OPERAND_UIMM24 : 996 value = fields->f_uimm24; 997 break; 998 case M32R_OPERAND_UIMM3 : 999 value = fields->f_uimm3; 1000 break; 1001 case M32R_OPERAND_UIMM4 : 1002 value = fields->f_uimm4; 1003 break; 1004 case M32R_OPERAND_UIMM5 : 1005 value = fields->f_uimm5; 1006 break; 1007 case M32R_OPERAND_UIMM8 : 1008 value = fields->f_uimm8; 1009 break; 1010 case M32R_OPERAND_ULO16 : 1011 value = fields->f_uimm16; 1012 break; 1013 1014 default : 1015 /* xgettext:c-format */ 1016 fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"), 1017 opindex); 1018 abort (); 1019 } 1020 1021 return value; 1022 } 1023 1024 void m32r_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int); 1025 void m32r_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma); 1026 1027 /* Stuffing values in cgen_fields is handled by a collection of functions. 1028 They are distinguished by the type of the VALUE argument they accept. 1029 TODO: floating point, inlining support, remove cases where argument type 1030 not appropriate. */ 1031 1032 void 1033 m32r_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 1034 int opindex, 1035 CGEN_FIELDS * fields, 1036 int value) 1037 { 1038 switch (opindex) 1039 { 1040 case M32R_OPERAND_ACC : 1041 fields->f_acc = value; 1042 break; 1043 case M32R_OPERAND_ACCD : 1044 fields->f_accd = value; 1045 break; 1046 case M32R_OPERAND_ACCS : 1047 fields->f_accs = value; 1048 break; 1049 case M32R_OPERAND_DCR : 1050 fields->f_r1 = value; 1051 break; 1052 case M32R_OPERAND_DISP16 : 1053 fields->f_disp16 = value; 1054 break; 1055 case M32R_OPERAND_DISP24 : 1056 fields->f_disp24 = value; 1057 break; 1058 case M32R_OPERAND_DISP8 : 1059 fields->f_disp8 = value; 1060 break; 1061 case M32R_OPERAND_DR : 1062 fields->f_r1 = value; 1063 break; 1064 case M32R_OPERAND_HASH : 1065 break; 1066 case M32R_OPERAND_HI16 : 1067 fields->f_hi16 = value; 1068 break; 1069 case M32R_OPERAND_IMM1 : 1070 fields->f_imm1 = value; 1071 break; 1072 case M32R_OPERAND_SCR : 1073 fields->f_r2 = value; 1074 break; 1075 case M32R_OPERAND_SIMM16 : 1076 fields->f_simm16 = value; 1077 break; 1078 case M32R_OPERAND_SIMM8 : 1079 fields->f_simm8 = value; 1080 break; 1081 case M32R_OPERAND_SLO16 : 1082 fields->f_simm16 = value; 1083 break; 1084 case M32R_OPERAND_SR : 1085 fields->f_r2 = value; 1086 break; 1087 case M32R_OPERAND_SRC1 : 1088 fields->f_r1 = value; 1089 break; 1090 case M32R_OPERAND_SRC2 : 1091 fields->f_r2 = value; 1092 break; 1093 case M32R_OPERAND_UIMM16 : 1094 fields->f_uimm16 = value; 1095 break; 1096 case M32R_OPERAND_UIMM24 : 1097 fields->f_uimm24 = value; 1098 break; 1099 case M32R_OPERAND_UIMM3 : 1100 fields->f_uimm3 = value; 1101 break; 1102 case M32R_OPERAND_UIMM4 : 1103 fields->f_uimm4 = value; 1104 break; 1105 case M32R_OPERAND_UIMM5 : 1106 fields->f_uimm5 = value; 1107 break; 1108 case M32R_OPERAND_UIMM8 : 1109 fields->f_uimm8 = value; 1110 break; 1111 case M32R_OPERAND_ULO16 : 1112 fields->f_uimm16 = value; 1113 break; 1114 1115 default : 1116 /* xgettext:c-format */ 1117 fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"), 1118 opindex); 1119 abort (); 1120 } 1121 } 1122 1123 void 1124 m32r_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 1125 int opindex, 1126 CGEN_FIELDS * fields, 1127 bfd_vma value) 1128 { 1129 switch (opindex) 1130 { 1131 case M32R_OPERAND_ACC : 1132 fields->f_acc = value; 1133 break; 1134 case M32R_OPERAND_ACCD : 1135 fields->f_accd = value; 1136 break; 1137 case M32R_OPERAND_ACCS : 1138 fields->f_accs = value; 1139 break; 1140 case M32R_OPERAND_DCR : 1141 fields->f_r1 = value; 1142 break; 1143 case M32R_OPERAND_DISP16 : 1144 fields->f_disp16 = value; 1145 break; 1146 case M32R_OPERAND_DISP24 : 1147 fields->f_disp24 = value; 1148 break; 1149 case M32R_OPERAND_DISP8 : 1150 fields->f_disp8 = value; 1151 break; 1152 case M32R_OPERAND_DR : 1153 fields->f_r1 = value; 1154 break; 1155 case M32R_OPERAND_HASH : 1156 break; 1157 case M32R_OPERAND_HI16 : 1158 fields->f_hi16 = value; 1159 break; 1160 case M32R_OPERAND_IMM1 : 1161 fields->f_imm1 = value; 1162 break; 1163 case M32R_OPERAND_SCR : 1164 fields->f_r2 = value; 1165 break; 1166 case M32R_OPERAND_SIMM16 : 1167 fields->f_simm16 = value; 1168 break; 1169 case M32R_OPERAND_SIMM8 : 1170 fields->f_simm8 = value; 1171 break; 1172 case M32R_OPERAND_SLO16 : 1173 fields->f_simm16 = value; 1174 break; 1175 case M32R_OPERAND_SR : 1176 fields->f_r2 = value; 1177 break; 1178 case M32R_OPERAND_SRC1 : 1179 fields->f_r1 = value; 1180 break; 1181 case M32R_OPERAND_SRC2 : 1182 fields->f_r2 = value; 1183 break; 1184 case M32R_OPERAND_UIMM16 : 1185 fields->f_uimm16 = value; 1186 break; 1187 case M32R_OPERAND_UIMM24 : 1188 fields->f_uimm24 = value; 1189 break; 1190 case M32R_OPERAND_UIMM3 : 1191 fields->f_uimm3 = value; 1192 break; 1193 case M32R_OPERAND_UIMM4 : 1194 fields->f_uimm4 = value; 1195 break; 1196 case M32R_OPERAND_UIMM5 : 1197 fields->f_uimm5 = value; 1198 break; 1199 case M32R_OPERAND_UIMM8 : 1200 fields->f_uimm8 = value; 1201 break; 1202 case M32R_OPERAND_ULO16 : 1203 fields->f_uimm16 = value; 1204 break; 1205 1206 default : 1207 /* xgettext:c-format */ 1208 fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"), 1209 opindex); 1210 abort (); 1211 } 1212 } 1213 1214 /* Function to call before using the instruction builder tables. */ 1215 1216 void 1217 m32r_cgen_init_ibld_table (CGEN_CPU_DESC cd) 1218 { 1219 cd->insert_handlers = & m32r_cgen_insert_handlers[0]; 1220 cd->extract_handlers = & m32r_cgen_extract_handlers[0]; 1221 1222 cd->insert_operand = m32r_cgen_insert_operand; 1223 cd->extract_operand = m32r_cgen_extract_operand; 1224 1225 cd->get_int_operand = m32r_cgen_get_int_operand; 1226 cd->set_int_operand = m32r_cgen_set_int_operand; 1227 cd->get_vma_operand = m32r_cgen_get_vma_operand; 1228 cd->set_vma_operand = m32r_cgen_set_vma_operand; 1229 } 1230
