1 /* Print instructions for the Texas TMS320C[34]X, for GDB and GNU Binutils. 2 3 Copyright (C) 2002-2016 Free Software Foundation, Inc. 4 5 Contributed by Michael P. Hayes (m.hayes (at) elec.canterbury.ac.nz) 6 7 This file is part of the GNU opcodes library. 8 9 This library is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 3, or (at your option) 12 any later version. 13 14 It is distributed in the hope that it will be useful, but WITHOUT 15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 17 License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with this program; if not, write to the Free Software 21 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 22 MA 02110-1301, USA. */ 23 24 #include "sysdep.h" 25 #include <math.h> 26 #include "libiberty.h" 27 #include "dis-asm.h" 28 #include "opcode/tic4x.h" 29 30 #define TIC4X_DEBUG 0 31 32 #define TIC4X_HASH_SIZE 11 /* 11 (bits) and above should give unique entries. */ 33 #define TIC4X_SPESOP_SIZE 8 /* Max 8. ops for special instructions. */ 34 35 typedef enum 36 { 37 IMMED_SINT, 38 IMMED_SUINT, 39 IMMED_SFLOAT, 40 IMMED_INT, 41 IMMED_UINT, 42 IMMED_FLOAT 43 } 44 immed_t; 45 46 typedef enum 47 { 48 INDIRECT_SHORT, 49 INDIRECT_LONG, 50 INDIRECT_TIC4X 51 } 52 indirect_t; 53 54 static int tic4x_version = 0; 55 static int tic4x_dp = 0; 56 57 static int 58 tic4x_pc_offset (unsigned int op) 59 { 60 /* Determine the PC offset for a C[34]x instruction. 61 This could be simplified using some boolean algebra 62 but at the expense of readability. */ 63 switch (op >> 24) 64 { 65 case 0x60: /* br */ 66 case 0x62: /* call (C4x) */ 67 case 0x64: /* rptb (C4x) */ 68 return 1; 69 case 0x61: /* brd */ 70 case 0x63: /* laj */ 71 case 0x65: /* rptbd (C4x) */ 72 return 3; 73 case 0x66: /* swi */ 74 case 0x67: 75 return 0; 76 default: 77 break; 78 } 79 80 switch ((op & 0xffe00000) >> 20) 81 { 82 case 0x6a0: /* bB */ 83 case 0x720: /* callB */ 84 case 0x740: /* trapB */ 85 return 1; 86 87 case 0x6a2: /* bBd */ 88 case 0x6a6: /* bBat */ 89 case 0x6aa: /* bBaf */ 90 case 0x722: /* lajB */ 91 case 0x748: /* latB */ 92 case 0x798: /* rptbd */ 93 return 3; 94 95 default: 96 break; 97 } 98 99 switch ((op & 0xfe200000) >> 20) 100 { 101 case 0x6e0: /* dbB */ 102 return 1; 103 104 case 0x6e2: /* dbBd */ 105 return 3; 106 107 default: 108 break; 109 } 110 111 return 0; 112 } 113 114 static int 115 tic4x_print_char (struct disassemble_info * info, char ch) 116 { 117 if (info != NULL) 118 (*info->fprintf_func) (info->stream, "%c", ch); 119 return 1; 120 } 121 122 static int 123 tic4x_print_str (struct disassemble_info *info, const char *str) 124 { 125 if (info != NULL) 126 (*info->fprintf_func) (info->stream, "%s", str); 127 return 1; 128 } 129 130 static int 131 tic4x_print_register (struct disassemble_info *info, unsigned long regno) 132 { 133 static tic4x_register_t ** registertable = NULL; 134 unsigned int i; 135 136 if (registertable == NULL) 137 { 138 registertable = xmalloc (sizeof (tic4x_register_t *) * REG_TABLE_SIZE); 139 for (i = 0; i < tic3x_num_registers; i++) 140 registertable[tic3x_registers[i].regno] = (tic4x_register_t *) (tic3x_registers + i); 141 if (IS_CPU_TIC4X (tic4x_version)) 142 { 143 /* Add C4x additional registers, overwriting 144 any C3x registers if necessary. */ 145 for (i = 0; i < tic4x_num_registers; i++) 146 registertable[tic4x_registers[i].regno] = 147 (tic4x_register_t *)(tic4x_registers + i); 148 } 149 } 150 if ((int) regno > (IS_CPU_TIC4X (tic4x_version) ? TIC4X_REG_MAX : TIC3X_REG_MAX)) 151 return 0; 152 if (info != NULL) 153 (*info->fprintf_func) (info->stream, "%s", registertable[regno]->name); 154 return 1; 155 } 156 157 static int 158 tic4x_print_addr (struct disassemble_info *info, unsigned long addr) 159 { 160 if (info != NULL) 161 (*info->print_address_func)(addr, info); 162 return 1; 163 } 164 165 static int 166 tic4x_print_relative (struct disassemble_info *info, 167 unsigned long pc, 168 long offset, 169 unsigned long opcode) 170 { 171 return tic4x_print_addr (info, pc + offset + tic4x_pc_offset (opcode)); 172 } 173 174 static int 175 tic4x_print_direct (struct disassemble_info *info, unsigned long arg) 176 { 177 if (info != NULL) 178 { 179 (*info->fprintf_func) (info->stream, "@"); 180 tic4x_print_addr (info, arg + (tic4x_dp << 16)); 181 } 182 return 1; 183 } 184 #if 0 185 /* FIXME: make the floating point stuff not rely on host 186 floating point arithmetic. */ 187 188 static void 189 tic4x_print_ftoa (unsigned int val, FILE *stream, fprintf_ftype pfunc) 190 { 191 int e; 192 int s; 193 int f; 194 double num = 0.0; 195 196 e = EXTRS (val, 31, 24); /* Exponent. */ 197 if (e != -128) 198 { 199 s = EXTRU (val, 23, 23); /* Sign bit. */ 200 f = EXTRU (val, 22, 0); /* Mantissa. */ 201 if (s) 202 f += -2 * (1 << 23); 203 else 204 f += (1 << 23); 205 num = f / (double)(1 << 23); 206 num = ldexp (num, e); 207 } 208 (*pfunc)(stream, "%.9g", num); 209 } 210 #endif 211 212 static int 213 tic4x_print_immed (struct disassemble_info *info, 214 immed_t type, 215 unsigned long arg) 216 { 217 int s; 218 int f; 219 int e; 220 double num = 0.0; 221 222 if (info == NULL) 223 return 1; 224 switch (type) 225 { 226 case IMMED_SINT: 227 case IMMED_INT: 228 (*info->fprintf_func) (info->stream, "%ld", (long) arg); 229 break; 230 231 case IMMED_SUINT: 232 case IMMED_UINT: 233 (*info->fprintf_func) (info->stream, "%lu", arg); 234 break; 235 236 case IMMED_SFLOAT: 237 e = EXTRS (arg, 15, 12); 238 if (e != -8) 239 { 240 s = EXTRU (arg, 11, 11); 241 f = EXTRU (arg, 10, 0); 242 if (s) 243 f += -2 * (1 << 11); 244 else 245 f += (1 << 11); 246 num = f / (double)(1 << 11); 247 num = ldexp (num, e); 248 } 249 (*info->fprintf_func) (info->stream, "%f", num); 250 break; 251 case IMMED_FLOAT: 252 e = EXTRS (arg, 31, 24); 253 if (e != -128) 254 { 255 s = EXTRU (arg, 23, 23); 256 f = EXTRU (arg, 22, 0); 257 if (s) 258 f += -2 * (1 << 23); 259 else 260 f += (1 << 23); 261 num = f / (double)(1 << 23); 262 num = ldexp (num, e); 263 } 264 (*info->fprintf_func) (info->stream, "%f", num); 265 break; 266 } 267 return 1; 268 } 269 270 static int 271 tic4x_print_cond (struct disassemble_info *info, unsigned int cond) 272 { 273 static tic4x_cond_t **condtable = NULL; 274 unsigned int i; 275 276 if (condtable == NULL) 277 { 278 condtable = xmalloc (sizeof (tic4x_cond_t *) * 32); 279 for (i = 0; i < tic4x_num_conds; i++) 280 condtable[tic4x_conds[i].cond] = (tic4x_cond_t *)(tic4x_conds + i); 281 } 282 if (cond > 31 || condtable[cond] == NULL) 283 return 0; 284 if (info != NULL) 285 (*info->fprintf_func) (info->stream, "%s", condtable[cond]->name); 286 return 1; 287 } 288 289 static int 290 tic4x_print_indirect (struct disassemble_info *info, 291 indirect_t type, 292 unsigned long arg) 293 { 294 unsigned int aregno; 295 unsigned int modn; 296 unsigned int disp; 297 const char *a; 298 299 aregno = 0; 300 modn = 0; 301 disp = 1; 302 switch(type) 303 { 304 case INDIRECT_TIC4X: /* *+ARn(disp) */ 305 disp = EXTRU (arg, 7, 3); 306 aregno = EXTRU (arg, 2, 0) + REG_AR0; 307 modn = 0; 308 break; 309 case INDIRECT_SHORT: 310 disp = 1; 311 aregno = EXTRU (arg, 2, 0) + REG_AR0; 312 modn = EXTRU (arg, 7, 3); 313 break; 314 case INDIRECT_LONG: 315 disp = EXTRU (arg, 7, 0); 316 aregno = EXTRU (arg, 10, 8) + REG_AR0; 317 modn = EXTRU (arg, 15, 11); 318 if (modn > 7 && disp != 0) 319 return 0; 320 break; 321 default: 322 (*info->fprintf_func)(info->stream, "# internal error: Unknown indirect type %d", type); 323 return 0; 324 } 325 if (modn > TIC3X_MODN_MAX) 326 return 0; 327 a = tic4x_indirects[modn].name; 328 while (*a) 329 { 330 switch (*a) 331 { 332 case 'a': 333 tic4x_print_register (info, aregno); 334 break; 335 case 'd': 336 tic4x_print_immed (info, IMMED_UINT, disp); 337 break; 338 case 'y': 339 tic4x_print_str (info, "ir0"); 340 break; 341 case 'z': 342 tic4x_print_str (info, "ir1"); 343 break; 344 default: 345 tic4x_print_char (info, *a); 346 break; 347 } 348 a++; 349 } 350 return 1; 351 } 352 353 static int 354 tic4x_print_op (struct disassemble_info *info, 355 unsigned long instruction, 356 tic4x_inst_t *p, 357 unsigned long pc) 358 { 359 int val; 360 const char *s; 361 const char *parallel = NULL; 362 363 /* Print instruction name. */ 364 s = p->name; 365 while (*s && parallel == NULL) 366 { 367 switch (*s) 368 { 369 case 'B': 370 if (! tic4x_print_cond (info, EXTRU (instruction, 20, 16))) 371 return 0; 372 break; 373 case 'C': 374 if (! tic4x_print_cond (info, EXTRU (instruction, 27, 23))) 375 return 0; 376 break; 377 case '_': 378 parallel = s + 1; /* Skip past `_' in name. */ 379 break; 380 default: 381 tic4x_print_char (info, *s); 382 break; 383 } 384 s++; 385 } 386 387 /* Print arguments. */ 388 s = p->args; 389 if (*s) 390 tic4x_print_char (info, ' '); 391 392 while (*s) 393 { 394 switch (*s) 395 { 396 case '*': /* Indirect 0--15. */ 397 if (! tic4x_print_indirect (info, INDIRECT_LONG, 398 EXTRU (instruction, 15, 0))) 399 return 0; 400 break; 401 402 case '#': /* Only used for ldp, ldpk. */ 403 tic4x_print_immed (info, IMMED_UINT, EXTRU (instruction, 15, 0)); 404 break; 405 406 case '@': /* Direct 0--15. */ 407 tic4x_print_direct (info, EXTRU (instruction, 15, 0)); 408 break; 409 410 case 'A': /* Address register 24--22. */ 411 if (! tic4x_print_register (info, EXTRU (instruction, 24, 22) + 412 REG_AR0)) 413 return 0; 414 break; 415 416 case 'B': /* 24-bit unsigned int immediate br(d)/call/rptb 417 address 0--23. */ 418 if (IS_CPU_TIC4X (tic4x_version)) 419 tic4x_print_relative (info, pc, EXTRS (instruction, 23, 0), 420 p->opcode); 421 else 422 tic4x_print_addr (info, EXTRU (instruction, 23, 0)); 423 break; 424 425 case 'C': /* Indirect (short C4x) 0--7. */ 426 if (! IS_CPU_TIC4X (tic4x_version)) 427 return 0; 428 if (! tic4x_print_indirect (info, INDIRECT_TIC4X, 429 EXTRU (instruction, 7, 0))) 430 return 0; 431 break; 432 433 case 'D': 434 /* Cockup if get here... */ 435 break; 436 437 case 'E': /* Register 0--7. */ 438 case 'e': 439 if (! tic4x_print_register (info, EXTRU (instruction, 7, 0))) 440 return 0; 441 break; 442 443 case 'F': /* 16-bit float immediate 0--15. */ 444 tic4x_print_immed (info, IMMED_SFLOAT, 445 EXTRU (instruction, 15, 0)); 446 break; 447 448 case 'i': /* Extended indirect 0--7. */ 449 if (EXTRU (instruction, 7, 5) == 7) 450 { 451 if (!tic4x_print_register (info, EXTRU (instruction, 4, 0))) 452 return 0; 453 break; 454 } 455 /* Fallthrough */ 456 457 case 'I': /* Indirect (short) 0--7. */ 458 if (! tic4x_print_indirect (info, INDIRECT_SHORT, 459 EXTRU (instruction, 7, 0))) 460 return 0; 461 break; 462 463 case 'j': /* Extended indirect 8--15 */ 464 if (EXTRU (instruction, 15, 13) == 7) 465 { 466 if (! tic4x_print_register (info, EXTRU (instruction, 12, 8))) 467 return 0; 468 break; 469 } 470 471 case 'J': /* Indirect (short) 8--15. */ 472 if (! tic4x_print_indirect (info, INDIRECT_SHORT, 473 EXTRU (instruction, 15, 8))) 474 return 0; 475 break; 476 477 case 'G': /* Register 8--15. */ 478 case 'g': 479 if (! tic4x_print_register (info, EXTRU (instruction, 15, 8))) 480 return 0; 481 break; 482 483 case 'H': /* Register 16--18. */ 484 if (! tic4x_print_register (info, EXTRU (instruction, 18, 16))) 485 return 0; 486 break; 487 488 case 'K': /* Register 19--21. */ 489 if (! tic4x_print_register (info, EXTRU (instruction, 21, 19))) 490 return 0; 491 break; 492 493 case 'L': /* Register 22--24. */ 494 if (! tic4x_print_register (info, EXTRU (instruction, 24, 22))) 495 return 0; 496 break; 497 498 case 'M': /* Register 22--22. */ 499 tic4x_print_register (info, EXTRU (instruction, 22, 22) + REG_R2); 500 break; 501 502 case 'N': /* Register 23--23. */ 503 tic4x_print_register (info, EXTRU (instruction, 23, 23) + REG_R0); 504 break; 505 506 case 'O': /* Indirect (short C4x) 8--15. */ 507 if (! IS_CPU_TIC4X (tic4x_version)) 508 return 0; 509 if (! tic4x_print_indirect (info, INDIRECT_TIC4X, 510 EXTRU (instruction, 15, 8))) 511 return 0; 512 break; 513 514 case 'P': /* Displacement 0--15 (used by Bcond and BcondD). */ 515 tic4x_print_relative (info, pc, EXTRS (instruction, 15, 0), 516 p->opcode); 517 break; 518 519 case 'Q': /* Register 0--15. */ 520 case 'q': 521 if (! tic4x_print_register (info, EXTRU (instruction, 15, 0))) 522 return 0; 523 break; 524 525 case 'R': /* Register 16--20. */ 526 case 'r': 527 if (! tic4x_print_register (info, EXTRU (instruction, 20, 16))) 528 return 0; 529 break; 530 531 case 'S': /* 16-bit signed immediate 0--15. */ 532 tic4x_print_immed (info, IMMED_SINT, 533 EXTRS (instruction, 15, 0)); 534 break; 535 536 case 'T': /* 5-bit signed immediate 16--20 (C4x stik). */ 537 if (! IS_CPU_TIC4X (tic4x_version)) 538 return 0; 539 if (! tic4x_print_immed (info, IMMED_SUINT, 540 EXTRU (instruction, 20, 16))) 541 return 0; 542 break; 543 544 case 'U': /* 16-bit unsigned int immediate 0--15. */ 545 tic4x_print_immed (info, IMMED_SUINT, EXTRU (instruction, 15, 0)); 546 break; 547 548 case 'V': /* 5/9-bit unsigned vector 0--4/8. */ 549 tic4x_print_immed (info, IMMED_SUINT, 550 IS_CPU_TIC4X (tic4x_version) ? 551 EXTRU (instruction, 8, 0) : 552 EXTRU (instruction, 4, 0) & ~0x20); 553 break; 554 555 case 'W': /* 8-bit signed immediate 0--7. */ 556 if (! IS_CPU_TIC4X (tic4x_version)) 557 return 0; 558 tic4x_print_immed (info, IMMED_SINT, EXTRS (instruction, 7, 0)); 559 break; 560 561 case 'X': /* Expansion register 4--0. */ 562 val = EXTRU (instruction, 4, 0) + REG_IVTP; 563 if (val < REG_IVTP || val > REG_TVTP) 564 return 0; 565 if (! tic4x_print_register (info, val)) 566 return 0; 567 break; 568 569 case 'Y': /* Address register 16--20. */ 570 val = EXTRU (instruction, 20, 16); 571 if (val < REG_AR0 || val > REG_SP) 572 return 0; 573 if (! tic4x_print_register (info, val)) 574 return 0; 575 break; 576 577 case 'Z': /* Expansion register 16--20. */ 578 val = EXTRU (instruction, 20, 16) + REG_IVTP; 579 if (val < REG_IVTP || val > REG_TVTP) 580 return 0; 581 if (! tic4x_print_register (info, val)) 582 return 0; 583 break; 584 585 case '|': /* Parallel instruction. */ 586 tic4x_print_str (info, " || "); 587 tic4x_print_str (info, parallel); 588 tic4x_print_char (info, ' '); 589 break; 590 591 case ';': 592 tic4x_print_char (info, ','); 593 break; 594 595 default: 596 tic4x_print_char (info, *s); 597 break; 598 } 599 s++; 600 } 601 return 1; 602 } 603 604 static void 605 tic4x_hash_opcode_special (tic4x_inst_t **optable_special, 606 const tic4x_inst_t *inst) 607 { 608 int i; 609 610 for (i = 0;i < TIC4X_SPESOP_SIZE; i++) 611 if (optable_special[i] != NULL 612 && optable_special[i]->opcode == inst->opcode) 613 { 614 /* Collision (we have it already) - overwrite. */ 615 optable_special[i] = (tic4x_inst_t *) inst; 616 return; 617 } 618 619 for (i = 0; i < TIC4X_SPESOP_SIZE; i++) 620 if (optable_special[i] == NULL) 621 { 622 /* Add the new opcode. */ 623 optable_special[i] = (tic4x_inst_t *) inst; 624 return; 625 } 626 627 /* This should never occur. This happens if the number of special 628 instructions exceeds TIC4X_SPESOP_SIZE. Please increase the variable 629 of this variable */ 630 #if TIC4X_DEBUG 631 printf ("optable_special[] is full, please increase TIC4X_SPESOP_SIZE!\n"); 632 #endif 633 } 634 635 static void 636 tic4x_hash_opcode (tic4x_inst_t **optable, 637 tic4x_inst_t **optable_special, 638 const tic4x_inst_t *inst, 639 const unsigned long tic4x_oplevel) 640 { 641 int j; 642 int opcode = inst->opcode >> (32 - TIC4X_HASH_SIZE); 643 int opmask = inst->opmask >> (32 - TIC4X_HASH_SIZE); 644 645 /* Use a TIC4X_HASH_SIZE bit index as a hash index. We should 646 have unique entries so there's no point having a linked list 647 for each entry? */ 648 for (j = opcode; j < opmask; j++) 649 if ((j & opmask) == opcode 650 && inst->oplevel & tic4x_oplevel) 651 { 652 #if TIC4X_DEBUG 653 /* We should only have collisions for synonyms like 654 ldp for ldi. */ 655 if (optable[j] != NULL) 656 printf ("Collision at index %d, %s and %s\n", 657 j, optable[j]->name, inst->name); 658 #endif 659 /* Catch those ops that collide with others already inside the 660 hash, and have a opmask greater than the one we use in the 661 hash. Store them in a special-list, that will handle full 662 32-bit INSN, not only the first 11-bit (or so). */ 663 if (optable[j] != NULL 664 && inst->opmask & ~(opmask << (32 - TIC4X_HASH_SIZE))) 665 { 666 /* Add the instruction already on the list. */ 667 tic4x_hash_opcode_special (optable_special, optable[j]); 668 669 /* Add the new instruction. */ 670 tic4x_hash_opcode_special (optable_special, inst); 671 } 672 673 optable[j] = (tic4x_inst_t *) inst; 674 } 675 } 676 677 /* Disassemble the instruction in 'instruction'. 678 'pc' should be the address of this instruction, it will 679 be used to print the target address if this is a relative jump or call 680 the disassembled instruction is written to 'info'. 681 The function returns the length of this instruction in words. */ 682 683 static int 684 tic4x_disassemble (unsigned long pc, 685 unsigned long instruction, 686 struct disassemble_info *info) 687 { 688 static tic4x_inst_t **optable = NULL; 689 static tic4x_inst_t **optable_special = NULL; 690 tic4x_inst_t *p; 691 int i; 692 unsigned long tic4x_oplevel; 693 694 tic4x_version = info->mach; 695 696 tic4x_oplevel = (IS_CPU_TIC4X (tic4x_version)) ? OP_C4X : 0; 697 tic4x_oplevel |= OP_C3X | OP_LPWR | OP_IDLE2 | OP_ENH; 698 699 if (optable == NULL) 700 { 701 optable = xcalloc (sizeof (tic4x_inst_t *), (1 << TIC4X_HASH_SIZE)); 702 703 optable_special = xcalloc (sizeof (tic4x_inst_t *), TIC4X_SPESOP_SIZE); 704 705 /* Install opcodes in reverse order so that preferred 706 forms overwrite synonyms. */ 707 for (i = tic4x_num_insts - 1; i >= 0; i--) 708 tic4x_hash_opcode (optable, optable_special, &tic4x_insts[i], 709 tic4x_oplevel); 710 711 /* We now need to remove the insn that are special from the 712 "normal" optable, to make the disasm search this extra list 713 for them. */ 714 for (i = 0; i < TIC4X_SPESOP_SIZE; i++) 715 if (optable_special[i] != NULL) 716 optable[optable_special[i]->opcode >> (32 - TIC4X_HASH_SIZE)] = NULL; 717 } 718 719 /* See if we can pick up any loading of the DP register... */ 720 if ((instruction >> 16) == 0x5070 || (instruction >> 16) == 0x1f70) 721 tic4x_dp = EXTRU (instruction, 15, 0); 722 723 p = optable[instruction >> (32 - TIC4X_HASH_SIZE)]; 724 if (p != NULL) 725 { 726 if (((instruction & p->opmask) == p->opcode) 727 && tic4x_print_op (NULL, instruction, p, pc)) 728 tic4x_print_op (info, instruction, p, pc); 729 else 730 (*info->fprintf_func) (info->stream, "%08lx", instruction); 731 } 732 else 733 { 734 for (i = 0; i<TIC4X_SPESOP_SIZE; i++) 735 if (optable_special[i] != NULL 736 && optable_special[i]->opcode == instruction) 737 { 738 (*info->fprintf_func)(info->stream, "%s", optable_special[i]->name); 739 break; 740 } 741 if (i == TIC4X_SPESOP_SIZE) 742 (*info->fprintf_func) (info->stream, "%08lx", instruction); 743 } 744 745 /* Return size of insn in words. */ 746 return 1; 747 } 748 749 /* The entry point from objdump and gdb. */ 750 int 751 print_insn_tic4x (bfd_vma memaddr, struct disassemble_info *info) 752 { 753 int status; 754 unsigned long pc; 755 unsigned long op; 756 bfd_byte buffer[4]; 757 758 status = (*info->read_memory_func) (memaddr, buffer, 4, info); 759 if (status != 0) 760 { 761 (*info->memory_error_func) (status, memaddr, info); 762 return -1; 763 } 764 765 pc = memaddr; 766 op = bfd_getl32 (buffer); 767 info->bytes_per_line = 4; 768 info->bytes_per_chunk = 4; 769 info->octets_per_byte = 4; 770 info->display_endian = BFD_ENDIAN_LITTLE; 771 return tic4x_disassemble (pc, op, info) * 4; 772 } 773
