1 /* Assemble V850 instructions. 2 Copyright (C) 1996-2016 Free Software Foundation, Inc. 3 4 This file is part of the GNU opcodes library. 5 6 This library is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 3, or (at your option) 9 any later version. 10 11 It is distributed in the hope that it will be useful, but WITHOUT 12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 14 License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with this program; if not, write to the Free Software 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 19 MA 02110-1301, USA. */ 20 21 #include "sysdep.h" 22 #include <stdio.h> 23 #include "opcode/v850.h" 24 #include "bfd.h" 25 #include "opintl.h" 26 27 /* Regular opcodes. */ 28 #define OP(x) ((x & 0x3f) << 5) 29 #define OP_MASK OP (0x3f) 30 31 /* Conditional branch opcodes (Format III). */ 32 #define BOP(x) ((0x58 << 4) | (x & 0x0f)) 33 #define BOP_MASK ((0x78 << 4) | 0x0f) 34 35 /* Conditional branch opcodes (Format VII). */ 36 #define BOP7(x) (0x107e0 | (x & 0xf)) 37 #define BOP7_MASK (0x1ffe0 | 0xf) 38 39 /* One-word opcodes. */ 40 #define one(x) ((unsigned int) (x)) 41 42 /* Two-word opcodes. */ 43 #define two(x,y) ((unsigned int) (x) | ((unsigned int) (y) << 16)) 44 45 46 /* The functions used to insert and extract complicated operands. */ 48 49 /* Note: There is a conspiracy between these functions and 50 v850_insert_operand() in gas/config/tc-v850.c. Error messages 51 containing the string 'out of range' will be ignored unless a 52 specific command line option is given to GAS. */ 53 54 static const char * not_valid = N_ ("displacement value is not in range and is not aligned"); 55 static const char * out_of_range = N_ ("displacement value is out of range"); 56 static const char * not_aligned = N_ ("displacement value is not aligned"); 57 58 static const char * immediate_out_of_range = N_ ("immediate value is out of range"); 59 static const char * branch_out_of_range = N_ ("branch value out of range"); 60 static const char * branch_out_of_range_and_odd_offset = N_ ("branch value not in range and to odd offset"); 61 static const char * branch_to_odd_offset = N_ ("branch to odd offset"); 62 static const char * pos_out_of_range = N_ ("position value is out of range"); 63 static const char * width_out_of_range = N_ ("width value is out of range"); 64 static const char * selid_out_of_range = N_ ("SelID is out of range"); 65 static const char * vector8_out_of_range = N_ ("vector8 is out of range"); 66 static const char * vector5_out_of_range = N_ ("vector5 is out of range"); 67 static const char * imm10_out_of_range = N_ ("imm10 is out of range"); 68 static const char * sr_selid_out_of_range = N_ ("SR/SelID is out of range"); 69 70 int 71 v850_msg_is_out_of_range (const char* msg) 72 { 73 return msg == out_of_range 74 || msg == immediate_out_of_range 75 || msg == branch_out_of_range; 76 } 77 78 static unsigned long 79 insert_i5div1 (unsigned long insn, long value, const char ** errmsg) 80 { 81 if (value > 30 || value < 2) 82 { 83 if (value & 1) 84 * errmsg = _(not_valid); 85 else 86 * errmsg = _(out_of_range); 87 } 88 else if (value & 1) 89 * errmsg = _(not_aligned); 90 91 value = (32 - value)/2; 92 93 return (insn | ((value << (2+16)) & 0x3c0000)); 94 } 95 96 static unsigned long 97 extract_i5div1 (unsigned long insn, int * invalid) 98 { 99 unsigned long ret = (insn & 0x003c0000) >> (16+2); 100 ret = 32 - (ret * 2); 101 102 if (invalid != 0) 103 *invalid = (ret > 30 || ret < 2) ? 1 : 0; 104 return ret; 105 } 106 107 static unsigned long 108 insert_i5div2 (unsigned long insn, long value, const char ** errmsg) 109 { 110 if (value > 30 || value < 4) 111 { 112 if (value & 1) 113 * errmsg = _(not_valid); 114 else 115 * errmsg = _(out_of_range); 116 } 117 else if (value & 1) 118 * errmsg = _(not_aligned); 119 120 value = (32 - value)/2; 121 122 return insn | ((value << (2 + 16)) & 0x3c0000); 123 } 124 125 static unsigned long 126 extract_i5div2 (unsigned long insn, int * invalid) 127 { 128 unsigned long ret = (insn & 0x003c0000) >> (16+2); 129 ret = 32 - (ret * 2); 130 131 if (invalid != 0) 132 *invalid = (ret > 30 || ret < 4) ? 1 : 0; 133 return ret; 134 } 135 136 static unsigned long 137 insert_i5div3 (unsigned long insn, long value, const char ** errmsg) 138 { 139 if (value > 32 || value < 2) 140 { 141 if (value & 1) 142 * errmsg = _(not_valid); 143 else 144 * errmsg = _(out_of_range); 145 } 146 else if (value & 1) 147 * errmsg = _(not_aligned); 148 149 value = (32 - value)/2; 150 151 return insn | ((value << (2+16)) & 0x3c0000); 152 } 153 154 static unsigned long 155 extract_i5div3 (unsigned long insn, int * invalid) 156 { 157 unsigned long ret = (insn & 0x003c0000) >> (16+2); 158 ret = 32 - (ret * 2); 159 160 if (invalid != 0) 161 *invalid = (ret > 32 || ret < 2) ? 1 : 0; 162 return ret; 163 } 164 165 static unsigned long 166 insert_d5_4 (unsigned long insn, long value, const char ** errmsg) 167 { 168 if (value > 0x1f || value < 0) 169 { 170 if (value & 1) 171 * errmsg = _(not_valid); 172 else 173 * errmsg = _(out_of_range); 174 } 175 else if (value & 1) 176 * errmsg = _(not_aligned); 177 178 value >>= 1; 179 180 return insn | (value & 0x0f); 181 } 182 183 static unsigned long 184 extract_d5_4 (unsigned long insn, int * invalid) 185 { 186 unsigned long ret = (insn & 0x0f); 187 188 ret <<= 1; 189 190 if (invalid != 0) 191 *invalid = 0; 192 return ret; 193 } 194 195 static unsigned long 196 insert_d8_6 (unsigned long insn, long value, const char ** errmsg) 197 { 198 if (value > 0xff || value < 0) 199 { 200 if ((value % 4) != 0) 201 * errmsg = _(not_valid); 202 else 203 * errmsg = _(out_of_range); 204 } 205 else if ((value % 4) != 0) 206 * errmsg = _(not_aligned); 207 208 value >>= 1; 209 210 return insn | (value & 0x7e); 211 } 212 213 static unsigned long 214 extract_d8_6 (unsigned long insn, int * invalid) 215 { 216 unsigned long ret = (insn & 0x7e); 217 218 ret <<= 1; 219 220 if (invalid != 0) 221 *invalid = 0; 222 return ret; 223 } 224 225 static unsigned long 226 insert_d8_7 (unsigned long insn, long value, const char ** errmsg) 227 { 228 if (value > 0xff || value < 0) 229 { 230 if ((value % 2) != 0) 231 * errmsg = _(not_valid); 232 else 233 * errmsg = _(out_of_range); 234 } 235 else if ((value % 2) != 0) 236 * errmsg = _(not_aligned); 237 238 value >>= 1; 239 240 return insn | (value & 0x7f); 241 } 242 243 static unsigned long 244 extract_d8_7 (unsigned long insn, int * invalid) 245 { 246 unsigned long ret = (insn & 0x7f); 247 248 ret <<= 1; 249 250 if (invalid != 0) 251 *invalid = 0; 252 return ret; 253 } 254 255 static unsigned long 256 insert_v8 (unsigned long insn, long value, const char ** errmsg) 257 { 258 if (value > 0xff || value < 0) 259 * errmsg = _(immediate_out_of_range); 260 261 return insn | (value & 0x1f) | ((value & 0xe0) << (27-5)); 262 } 263 264 static unsigned long 265 extract_v8 (unsigned long insn, int * invalid) 266 { 267 unsigned long ret = (insn & 0x1f) | ((insn >> (27-5)) & 0xe0); 268 269 if (invalid != 0) 270 *invalid = 0; 271 return ret; 272 } 273 274 static unsigned long 275 insert_d9 (unsigned long insn, long value, const char ** errmsg) 276 { 277 if (value > 0xff || value < -0x100) 278 { 279 if ((value % 2) != 0) 280 * errmsg = branch_out_of_range_and_odd_offset; 281 else 282 * errmsg = branch_out_of_range; 283 } 284 else if ((value % 2) != 0) 285 * errmsg = branch_to_odd_offset; 286 287 return insn | ((value & 0x1f0) << 7) | ((value & 0x0e) << 3); 288 } 289 290 static unsigned long 291 extract_d9 (unsigned long insn, int * invalid) 292 { 293 signed long ret = ((insn >> 7) & 0x1f0) | ((insn >> 3) & 0x0e); 294 295 ret = (ret ^ 0x100) - 0x100; 296 297 if (invalid != 0) 298 *invalid = 0; 299 return ret; 300 } 301 302 static unsigned long 303 insert_u16_loop (unsigned long insn, long value, const char ** errmsg) 304 { 305 /* Loop displacement is encoded as a positive value, 306 even though the instruction branches backwards. */ 307 if (value < 0 || value > 0xffff) 308 { 309 if ((value % 2) != 0) 310 * errmsg = branch_out_of_range_and_odd_offset; 311 else 312 * errmsg = branch_out_of_range; 313 } 314 else if ((value % 2) != 0) 315 * errmsg = branch_to_odd_offset; 316 317 return insn | ((value & 0xfffe) << 16); 318 } 319 320 static unsigned long 321 extract_u16_loop (unsigned long insn, int * invalid) 322 { 323 long ret = (insn >> 16) & 0xfffe; 324 325 if (invalid != 0) 326 *invalid = 0; 327 return ret; 328 } 329 330 static unsigned long 331 insert_d16_15 (unsigned long insn, long value, const char ** errmsg) 332 { 333 if (value > 0x7fff || value < -0x8000) 334 { 335 if ((value % 2) != 0) 336 * errmsg = _(not_valid); 337 else 338 * errmsg = _(out_of_range); 339 } 340 else if ((value % 2) != 0) 341 * errmsg = _(not_aligned); 342 343 return insn | ((value & 0xfffe) << 16); 344 } 345 346 static unsigned long 347 extract_d16_15 (unsigned long insn, int * invalid) 348 { 349 signed long ret = (insn >> 16) & 0xfffe; 350 351 ret = (ret ^ 0x8000) - 0x8000; 352 353 if (invalid != 0) 354 *invalid = 0; 355 return ret; 356 } 357 358 static unsigned long 359 insert_d16_16 (unsigned long insn, signed long value, const char ** errmsg) 360 { 361 if (value > 0x7fff || value < -0x8000) 362 * errmsg = _(out_of_range); 363 364 return insn | ((value & 0xfffe) << 16) | ((value & 1) << 5); 365 } 366 367 static unsigned long 368 extract_d16_16 (unsigned long insn, int * invalid) 369 { 370 signed long ret = ((insn >> 16) & 0xfffe) | ((insn >> 5) & 1); 371 372 ret = (ret ^ 0x8000) - 0x8000; 373 374 if (invalid != 0) 375 *invalid = 0; 376 return ret; 377 } 378 379 static unsigned long 380 insert_d17_16 (unsigned long insn, long value, const char ** errmsg) 381 { 382 if (value > 0xffff || value < -0x10000) 383 * errmsg = _(out_of_range); 384 385 return insn | ((value & 0xfffe) << 16) | ((value & 0x10000) >> (16 - 4)); 386 } 387 388 static unsigned long 389 extract_d17_16 (unsigned long insn, int * invalid) 390 { 391 signed long ret = ((insn >> 16) & 0xfffe) | ((insn << (16 - 4)) & 0x10000); 392 393 ret = (ret ^ 0x10000) - 0x10000; 394 395 if (invalid != 0) 396 *invalid = 0; 397 return (unsigned long)ret; 398 } 399 400 static unsigned long 401 insert_d22 (unsigned long insn, long value, const char ** errmsg) 402 { 403 if (value > 0x1fffff || value < -0x200000) 404 { 405 if ((value % 2) != 0) 406 * errmsg = branch_out_of_range_and_odd_offset; 407 else 408 * errmsg = branch_out_of_range; 409 } 410 else if ((value % 2) != 0) 411 * errmsg = branch_to_odd_offset; 412 413 return insn | ((value & 0xfffe) << 16) | ((value & 0x3f0000) >> 16); 414 } 415 416 static unsigned long 417 extract_d22 (unsigned long insn, int * invalid) 418 { 419 signed long ret = ((insn >> 16) & 0xfffe) | ((insn << 16) & 0x3f0000); 420 421 ret = (ret ^ 0x200000) - 0x200000; 422 423 if (invalid != 0) 424 *invalid = 0; 425 return (unsigned long) ret; 426 } 427 428 static unsigned long 429 insert_d23 (unsigned long insn, long value, const char ** errmsg) 430 { 431 if (value > 0x3fffff || value < -0x400000) 432 * errmsg = out_of_range; 433 434 return insn | ((value & 0x7f) << 4) | ((value & 0x7fff80) << (16-7)); 435 } 436 437 static unsigned long 438 insert_d23_align1 (unsigned long insn, long value, const char ** errmsg) 439 { 440 if (value > 0x3fffff || value < -0x400000) 441 { 442 if (value & 0x1) 443 * errmsg = _(not_valid); 444 else 445 * errmsg = _(out_of_range); 446 } 447 else if (value & 0x1) 448 * errmsg = _(not_aligned); 449 450 return insn | ((value & 0x7e) << 4) | ((value & 0x7fff80) << (16 - 7)); 451 } 452 453 static unsigned long 454 extract_d23 (unsigned long insn, int * invalid) 455 { 456 signed long ret = ((insn >> 4) & 0x7f) | ((insn >> (16-7)) & 0x7fff80); 457 458 ret = (ret ^ 0x400000) - 0x400000; 459 460 if (invalid != 0) 461 *invalid = 0; 462 return (unsigned long) ret; 463 } 464 465 static unsigned long 466 insert_i9 (unsigned long insn, signed long value, const char ** errmsg) 467 { 468 if (value > 0xff || value < -0x100) 469 * errmsg = _(immediate_out_of_range); 470 471 return insn | ((value & 0x1e0) << 13) | (value & 0x1f); 472 } 473 474 static unsigned long 475 extract_i9 (unsigned long insn, int * invalid) 476 { 477 signed long ret = ((insn >> 13) & 0x1e0) | (insn & 0x1f); 478 479 ret = (ret ^ 0x100) - 0x100; 480 481 if (invalid != 0) 482 *invalid = 0; 483 return ret; 484 } 485 486 static unsigned long 487 insert_u9 (unsigned long insn, long v, const char ** errmsg) 488 { 489 unsigned long value = (unsigned long) v; 490 491 if (value > 0x1ff) 492 * errmsg = _(immediate_out_of_range); 493 494 return insn | ((value & 0x1e0) << 13) | (value & 0x1f); 495 } 496 497 static unsigned long 498 extract_u9 (unsigned long insn, int * invalid) 499 { 500 unsigned long ret = ((insn >> 13) & 0x1e0) | (insn & 0x1f); 501 502 if (invalid != 0) 503 *invalid = 0; 504 return ret; 505 } 506 507 static unsigned long 508 insert_spe (unsigned long insn, long v, const char ** errmsg) 509 { 510 unsigned long value = (unsigned long) v; 511 512 if (value != 3) 513 * errmsg = _("invalid register for stack adjustment"); 514 515 return insn & ~0x180000; 516 } 517 518 static unsigned long 519 extract_spe (unsigned long insn ATTRIBUTE_UNUSED, int * invalid) 520 { 521 if (invalid != 0) 522 *invalid = 0; 523 524 return 3; 525 } 526 527 static unsigned long 528 insert_r4 (unsigned long insn, long v, const char ** errmsg) 529 { 530 unsigned long value = (unsigned long) v; 531 532 if (value >= 32) 533 * errmsg = _("invalid register name"); 534 535 return insn | ((value & 0x01) << 23) | ((value & 0x1e) << 16); 536 } 537 538 static unsigned long 539 extract_r4 (unsigned long insn, int * invalid) 540 { 541 unsigned long r4; 542 unsigned long insn2; 543 544 insn2 = insn >> 16; 545 r4 = (((insn2 & 0x0080) >> 7) | (insn2 & 0x001e)); 546 547 if (invalid != 0) 548 *invalid = 0; 549 550 return r4; 551 } 552 553 static unsigned long G_pos; 554 555 static unsigned long 556 insert_POS (unsigned long insn, long pos, const char ** errmsg) 557 { 558 if (pos > 0x1f || pos < 0) 559 * errmsg = _(pos_out_of_range); 560 561 G_pos = (unsigned long) pos; 562 563 return insn; /* Not an oparaton until WIDTH. */ 564 } 565 566 static unsigned long 567 extract_POS_U (unsigned long insn, int * invalid) 568 { 569 unsigned long pos,lsb; 570 unsigned long insn2; 571 insn2 = insn >> 16; 572 573 lsb = ((insn2 & 0x0800) >> 8) 574 | ((insn2 & 0x000e) >> 1); 575 lsb += 16; 576 pos = lsb; 577 578 if (invalid != 0) 579 *invalid = 0; 580 581 return pos; 582 } 583 584 static unsigned long 585 extract_POS_L (unsigned long insn, int * invalid) 586 { 587 unsigned long pos,lsb; 588 unsigned long insn2; 589 insn2 = insn >> 16; 590 591 lsb = ((insn2 & 0x0800) >> 8) 592 | ((insn2 & 0x000e) >> 1); 593 pos = lsb; 594 595 if (invalid != 0) 596 *invalid = 0; 597 598 return pos; 599 } 600 601 static unsigned long 602 insert_WIDTH (unsigned long insn, long width, const char ** errmsg) 603 { 604 unsigned long msb, lsb, opc, ret; 605 unsigned long msb_expand, lsb_expand; 606 607 msb = (unsigned long)width + G_pos - 1; 608 lsb = G_pos; 609 opc = 0; 610 G_pos = 0; 611 612 if (width > 0x20 || width < 0) 613 * errmsg = _(width_out_of_range); 614 615 if ((msb >= 16) && (lsb >= 16)) 616 opc = 0x0090; 617 else if ((msb >= 16) && (lsb < 16)) 618 opc = 0x00b0; 619 else if ((msb < 16) && (lsb < 16)) 620 opc = 0x00d0; 621 else 622 * errmsg = _(width_out_of_range); 623 624 msb &= 0x0f; 625 msb_expand = msb << 12; 626 lsb &= 0x0f; 627 lsb_expand = ((lsb & 0x8) << 8)|((lsb & 0x7) << 1); 628 629 ret = (insn & 0x0000ffff) | ((opc | msb_expand | lsb_expand) << 16); 630 631 return ret; 632 } 633 634 static unsigned long 635 extract_WIDTH_U (unsigned long insn, int * invalid) 636 { 637 unsigned long width, msb, lsb; 638 unsigned long insn2; 639 insn2 = insn >> 16; 640 641 msb = ((insn2 & 0xf000) >> 12); 642 msb += 16; 643 lsb = ((insn2 & 0x0800) >> 8) 644 | ((insn2 & 0x000e) >> 1); 645 lsb += 16; 646 647 if (invalid != 0) 648 *invalid = 0; 649 650 width = msb - lsb + 1; 651 652 return width; 653 } 654 655 static unsigned long 656 extract_WIDTH_M (unsigned long insn, int * invalid) 657 { 658 unsigned long width, msb, lsb; 659 unsigned long insn2; 660 insn2 = insn >> 16; 661 662 msb = ((insn2 & 0xf000) >> 12) ; 663 msb += 16; 664 lsb = ((insn2 & 0x0800) >> 8) 665 | ((insn2 & 0x000e) >> 1); 666 667 if (invalid != 0) 668 *invalid = 0; 669 670 width = msb - lsb + 1; 671 672 return width; 673 } 674 675 static unsigned long 676 extract_WIDTH_L (unsigned long insn, int * invalid) 677 { 678 unsigned long width, msb, lsb; 679 unsigned long insn2; 680 insn2 = insn >> 16; 681 682 msb = ((insn2 & 0xf000) >> 12) ; 683 lsb = ((insn2 & 0x0800) >> 8) 684 | ((insn2 & 0x000e) >> 1); 685 686 if (invalid != 0) 687 *invalid = 0; 688 689 width = msb - lsb + 1; 690 691 return width; 692 } 693 694 static unsigned long 695 insert_SELID (unsigned long insn, long selid, const char ** errmsg) 696 { 697 unsigned long ret; 698 699 if (selid > 0x1f || selid < 0) 700 * errmsg = _(selid_out_of_range); 701 702 ret = (insn | ((selid & 0x1f) << 27)); 703 704 return ret; 705 } 706 707 static unsigned long 708 extract_SELID (unsigned long insn, int * invalid) 709 { 710 unsigned long selid; 711 unsigned long insn2; 712 713 insn2 = insn >> 16; 714 715 selid = ((insn2 & 0xf800) >> 11); 716 717 if (invalid != 0) 718 *invalid = 0; 719 720 return selid; 721 } 722 723 static unsigned long 724 insert_VECTOR8 (unsigned long insn, long vector8, const char ** errmsg) 725 { 726 unsigned long ret; 727 unsigned long VVV,vvvvv; 728 729 if (vector8 > 0xff || vector8 < 0) 730 * errmsg = _(vector8_out_of_range); 731 732 VVV = (vector8 & 0xe0) >> 5; 733 vvvvv = (vector8 & 0x1f); 734 735 ret = (insn | (VVV << 27) | vvvvv); 736 737 return ret; 738 } 739 740 static unsigned long 741 extract_VECTOR8 (unsigned long insn, int * invalid) 742 { 743 unsigned long vector8; 744 unsigned long VVV,vvvvv; 745 unsigned long insn2; 746 747 insn2 = insn >> 16; 748 VVV = ((insn2 & 0x3800) >> 11); 749 vvvvv = (insn & 0x001f); 750 vector8 = VVV << 5 | vvvvv; 751 752 if (invalid != 0) 753 *invalid = 0; 754 755 return vector8; 756 } 757 758 static unsigned long 759 insert_VECTOR5 (unsigned long insn, long vector5, const char ** errmsg) 760 { 761 unsigned long ret; 762 unsigned long vvvvv; 763 764 if (vector5 > 0x1f || vector5 < 0) 765 * errmsg = _(vector5_out_of_range); 766 767 vvvvv = (vector5 & 0x1f); 768 769 ret = (insn | vvvvv); 770 771 return ret; 772 } 773 774 static unsigned long 775 extract_VECTOR5 (unsigned long insn, int * invalid) 776 { 777 unsigned long vector5; 778 779 vector5 = (insn & 0x001f); 780 781 if (invalid != 0) 782 *invalid = 0; 783 784 return vector5; 785 } 786 787 static unsigned long 788 insert_CACHEOP (unsigned long insn, long cacheop, const char ** errmsg ATTRIBUTE_UNUSED) 789 { 790 unsigned long ret; 791 unsigned long pp,PPPPP; 792 793 pp = (cacheop & 0x60) >> 5; 794 PPPPP = (cacheop & 0x1f); 795 796 ret = insn | (pp << 11) | (PPPPP << 27); 797 798 return ret; 799 } 800 801 static unsigned long 802 extract_CACHEOP (unsigned long insn, int * invalid) 803 { 804 unsigned long ret; 805 unsigned long pp,PPPPP; 806 unsigned long insn2; 807 808 insn2 = insn >> 16; 809 810 PPPPP = ((insn2 & 0xf800) >> 11); 811 pp = ((insn & 0x1800) >> 11); 812 813 ret = (pp << 5) | PPPPP; 814 815 if (invalid != 0) 816 *invalid = 0; 817 818 return ret; 819 } 820 821 static unsigned long 822 insert_PREFOP (unsigned long insn, long prefop, const char ** errmsg ATTRIBUTE_UNUSED) 823 { 824 unsigned long ret; 825 unsigned long PPPPP; 826 827 PPPPP = (prefop & 0x1f); 828 829 ret = insn | (PPPPP << 27); 830 831 return ret; 832 } 833 834 static unsigned long 835 extract_PREFOP (unsigned long insn, int * invalid) 836 { 837 unsigned long ret; 838 unsigned long PPPPP; 839 unsigned long insn2; 840 841 insn2 = insn >> 16; 842 843 PPPPP = (insn2 & 0xf800) >> 11; 844 845 ret = PPPPP; 846 847 if (invalid != 0) 848 *invalid = 0; 849 850 return ret; 851 } 852 853 static unsigned long 854 insert_IMM10U (unsigned long insn, long value, const char ** errmsg) 855 { 856 unsigned long imm10, ret; 857 unsigned long iiiii,IIIII; 858 859 if (value > 0x3ff || value < 0) 860 * errmsg = _(imm10_out_of_range); 861 862 imm10 = ((unsigned long) value) & 0x3ff; 863 IIIII = (imm10 >> 5) & 0x1f; 864 iiiii = imm10 & 0x1f; 865 866 ret = insn | IIIII << 27 | iiiii; 867 868 return ret; 869 } 870 871 static unsigned long 872 extract_IMM10U (unsigned long insn, int * invalid) 873 { 874 unsigned long ret; 875 unsigned long iiiii,IIIII; 876 unsigned long insn2; 877 insn2 = insn >> 16; 878 879 IIIII = ((insn2 & 0xf800) >> 11); 880 iiiii = (insn & 0x001f); 881 882 ret = (IIIII << 5) | iiiii; 883 884 if (invalid != 0) 885 *invalid = 0; 886 887 return ret; 888 } 889 890 static unsigned long 891 insert_SRSEL1 (unsigned long insn, long value, const char ** errmsg) 892 { 893 unsigned long imm10, ret; 894 unsigned long sr,selid; 895 896 if (value > 0x3ff || value < 0) 897 * errmsg = _(sr_selid_out_of_range); 898 899 imm10 = (unsigned long) value; 900 selid = (imm10 & 0x3e0) >> 5; 901 sr = imm10 & 0x1f; 902 903 ret = insn | selid << 27 | sr; 904 905 return ret; 906 } 907 908 static unsigned long 909 extract_SRSEL1 (unsigned long insn, int * invalid) 910 { 911 unsigned long ret; 912 unsigned long sr, selid; 913 unsigned long insn2; 914 915 insn2 = insn >> 16; 916 917 selid = ((insn2 & 0xf800) >> 11); 918 sr = (insn & 0x001f); 919 920 ret = (selid << 5) | sr; 921 922 if (invalid != 0) 923 *invalid = 0; 924 925 return ret; 926 } 927 928 static unsigned long 929 insert_SRSEL2 (unsigned long insn, long value, const char ** errmsg) 930 { 931 unsigned long imm10, ret; 932 unsigned long sr, selid; 933 934 if (value > 0x3ff || value < 0) 935 * errmsg = _(sr_selid_out_of_range); 936 937 imm10 = (unsigned long) value; 938 selid = (imm10 & 0x3e0) >> 5; 939 sr = imm10 & 0x1f; 940 941 ret = insn | selid << 27 | sr << 11; 942 943 return ret; 944 } 945 946 static unsigned long 947 extract_SRSEL2 (unsigned long insn, int * invalid) 948 { 949 unsigned long ret; 950 unsigned long sr, selid; 951 unsigned long insn2; 952 953 insn2 = insn >> 16; 954 955 selid = ((insn2 & 0xf800) >> 11); 956 sr = ((insn & 0xf800) >> 11); 957 958 ret = (selid << 5) | sr; 959 960 if (invalid != 0) 961 *invalid = 0; 962 963 return ret; 964 } 965 966 /* Warning: code in gas/config/tc-v850.c examines the contents of this array. 968 If you change any of the values here, be sure to look for side effects in 969 that code. */ 970 const struct v850_operand v850_operands[] = 971 { 972 #define UNUSED 0 973 { 0, 0, NULL, NULL, 0, BFD_RELOC_NONE }, 974 975 /* The R1 field in a format 1, 6, 7, 9, C insn. */ 976 #define R1 (UNUSED + 1) 977 { 5, 0, NULL, NULL, V850_OPERAND_REG, BFD_RELOC_NONE }, 978 979 /* As above, but register 0 is not allowed. */ 980 #define R1_NOTR0 (R1 + 1) 981 { 5, 0, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0, BFD_RELOC_NONE }, 982 983 /* Even register is allowed. */ 984 #define R1_EVEN (R1_NOTR0 + 1) 985 { 4, 1, NULL, NULL, V850_OPERAND_REG | V850_REG_EVEN, BFD_RELOC_NONE }, 986 987 /* Bang (bit reverse). */ 988 #define R1_BANG (R1_EVEN + 1) 989 { 5, 0, NULL, NULL, V850_OPERAND_REG | V850_OPERAND_BANG, BFD_RELOC_NONE }, 990 991 /* Percent (modulo). */ 992 #define R1_PERCENT (R1_BANG + 1) 993 { 5, 0, NULL, NULL, V850_OPERAND_REG | V850_OPERAND_PERCENT, BFD_RELOC_NONE }, 994 995 /* The R2 field in a format 1, 2, 4, 5, 6, 7, 9, C insn. */ 996 #define R2 (R1_PERCENT + 1) 997 { 5, 11, NULL, NULL, V850_OPERAND_REG, BFD_RELOC_NONE }, 998 999 /* As above, but register 0 is not allowed. */ 1000 #define R2_NOTR0 (R2 + 1) 1001 { 5, 11, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0, BFD_RELOC_NONE }, 1002 1003 /* Even register is allowed. */ 1004 #define R2_EVEN (R2_NOTR0 + 1) 1005 { 4, 12, NULL, NULL, V850_OPERAND_REG | V850_REG_EVEN, BFD_RELOC_NONE }, 1006 1007 /* Reg2 in dispose instruction. */ 1008 #define R2_DISPOSE (R2_EVEN + 1) 1009 { 5, 16, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0, BFD_RELOC_NONE }, 1010 1011 /* The R3 field in a format 11, 12, C insn. */ 1012 #define R3 (R2_DISPOSE + 1) 1013 { 5, 27, NULL, NULL, V850_OPERAND_REG, BFD_RELOC_NONE }, 1014 1015 /* As above, but register 0 is not allowed. */ 1016 #define R3_NOTR0 (R3 + 1) 1017 { 5, 27, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0, BFD_RELOC_NONE }, 1018 1019 /* As above, but odd number registers are not allowed. */ 1020 #define R3_EVEN (R3_NOTR0 + 1) 1021 { 4, 28, NULL, NULL, V850_OPERAND_REG | V850_REG_EVEN, BFD_RELOC_NONE }, 1022 1023 /* As above, but register 0 is not allowed. */ 1024 #define R3_EVEN_NOTR0 (R3_EVEN + 1) 1025 { 4, 28, NULL, NULL, V850_OPERAND_REG | V850_REG_EVEN | V850_NOT_R0, BFD_RELOC_NONE }, 1026 1027 /* Forth register in FPU Instruction. */ 1028 #define R4 (R3_EVEN_NOTR0 + 1) 1029 { 5, 0, insert_r4, extract_r4, V850_OPERAND_REG, BFD_RELOC_NONE }, 1030 1031 /* As above, but odd number registers are not allowed. */ 1032 #define R4_EVEN (R4 + 1) 1033 { 4, 17, NULL, NULL, V850_OPERAND_REG | V850_REG_EVEN, BFD_RELOC_NONE }, 1034 1035 /* Stack pointer in prepare instruction. */ 1036 #define SP (R4_EVEN + 1) 1037 { 2, 0, insert_spe, extract_spe, V850_OPERAND_REG, BFD_RELOC_NONE }, 1038 1039 /* EP Register. */ 1040 #define EP (SP + 1) 1041 { 0, 0, NULL, NULL, V850_OPERAND_EP, BFD_RELOC_NONE }, 1042 1043 /* A list of registers in a prepare/dispose instruction. */ 1044 #define LIST12 (EP + 1) 1045 { -1, 0xffe00001, NULL, NULL, V850E_OPERAND_REG_LIST, BFD_RELOC_NONE }, 1046 1047 /* System register operands. */ 1048 #define OLDSR1 (LIST12 + 1) 1049 { 5, 0, NULL, NULL, V850_OPERAND_SRG, BFD_RELOC_NONE }, 1050 1051 #define SR1 (OLDSR1 + 1) 1052 { 0, 0, insert_SRSEL1, extract_SRSEL1, V850_OPERAND_SRG, BFD_RELOC_NONE }, 1053 1054 /* The R2 field as a system register. */ 1055 #define OLDSR2 (SR1 + 1) 1056 { 5, 11, NULL, NULL, V850_OPERAND_SRG, BFD_RELOC_NONE }, 1057 1058 #define SR2 (OLDSR2 + 1) 1059 { 0, 0, insert_SRSEL2, extract_SRSEL2, V850_OPERAND_SRG, BFD_RELOC_NONE }, 1060 1061 /* FPU CC bit position. */ 1062 #define FFF (SR2 + 1) 1063 { 3, 17, NULL, NULL, 0, BFD_RELOC_NONE }, 1064 1065 /* The 4 bit condition code in a setf instruction. */ 1066 #define CCCC (FFF + 1) 1067 { 4, 0, NULL, NULL, V850_OPERAND_CC, BFD_RELOC_NONE }, 1068 1069 /* Condition code in adf,sdf. */ 1070 #define CCCC_NOTSA (CCCC + 1) 1071 { 4, 17, NULL, NULL, V850_OPERAND_CC|V850_NOT_SA, BFD_RELOC_NONE }, 1072 1073 /* Condition code in conditional moves. */ 1074 #define MOVCC (CCCC_NOTSA + 1) 1075 { 4, 17, NULL, NULL, V850_OPERAND_CC, BFD_RELOC_NONE }, 1076 1077 /* Condition code in FPU. */ 1078 #define FLOAT_CCCC (MOVCC + 1) 1079 { 4, 27, NULL, NULL, V850_OPERAND_FLOAT_CC, BFD_RELOC_NONE }, 1080 1081 /* The 1 bit immediate field in format C insn. */ 1082 #define VI1 (FLOAT_CCCC + 1) 1083 { 1, 3, NULL, NULL, 0, BFD_RELOC_NONE }, 1084 1085 /* The 1 bit immediate field in format C insn. */ 1086 #define VC1 (VI1 + 1) 1087 { 1, 0, NULL, NULL, 0, BFD_RELOC_NONE }, 1088 1089 /* The 2 bit immediate field in format C insn. */ 1090 #define DI2 (VC1 + 1) 1091 { 2, 17, NULL, NULL, 0, BFD_RELOC_NONE }, 1092 1093 /* The 2 bit immediate field in format C insn. */ 1094 #define VI2 (DI2 + 1) 1095 { 2, 0, NULL, NULL, 0, BFD_RELOC_NONE }, 1096 1097 /* The 2 bit immediate field in format C - DUP insn. */ 1098 #define VI2DUP (VI2 + 1) 1099 { 2, 2, NULL, NULL, 0, BFD_RELOC_NONE }, 1100 1101 /* The 3 bit immediate field in format 8 insn. */ 1102 #define B3 (VI2DUP + 1) 1103 { 3, 11, NULL, NULL, 0, BFD_RELOC_NONE }, 1104 1105 /* The 3 bit immediate field in format C insn. */ 1106 #define DI3 (B3 + 1) 1107 { 3, 17, NULL, NULL, 0, BFD_RELOC_NONE }, 1108 1109 /* The 3 bit immediate field in format C insn. */ 1110 #define I3U (DI3 + 1) 1111 { 3, 0, NULL, NULL, 0, BFD_RELOC_NONE }, 1112 1113 /* The 4 bit immediate field in format C insn. */ 1114 #define I4U (I3U + 1) 1115 { 4, 0, NULL, NULL, 0, BFD_RELOC_NONE }, 1116 1117 /* The 4 bit immediate field in fetrap. */ 1118 #define I4U_NOTIMM0 (I4U + 1) 1119 { 4, 11, NULL, NULL, V850_NOT_IMM0, BFD_RELOC_NONE }, 1120 1121 /* The unsigned disp4 field in a sld.bu. */ 1122 #define D4U (I4U_NOTIMM0 + 1) 1123 { 4, 0, NULL, NULL, V850_OPERAND_DISP, BFD_RELOC_V850_TDA_4_4_OFFSET }, 1124 1125 /* The imm5 field in a format 2 insn. */ 1126 #define I5 (D4U + 1) 1127 { 5, 0, NULL, NULL, V850_OPERAND_SIGNED, BFD_RELOC_NONE }, 1128 1129 /* The imm5 field in a format 11 insn. */ 1130 #define I5DIV1 (I5 + 1) 1131 { 5, 0, insert_i5div1, extract_i5div1, 0, BFD_RELOC_NONE }, 1132 1133 #define I5DIV2 (I5DIV1 + 1) 1134 { 5, 0, insert_i5div2, extract_i5div2, 0, BFD_RELOC_NONE }, 1135 1136 #define I5DIV3 (I5DIV2 + 1) 1137 { 5, 0, insert_i5div3, extract_i5div3, 0, BFD_RELOC_NONE }, 1138 1139 /* The unsigned imm5 field in a format 2 insn. */ 1140 #define I5U (I5DIV3 + 1) 1141 { 5, 0, NULL, NULL, 0, BFD_RELOC_NONE }, 1142 1143 /* The imm5 field in a prepare/dispose instruction. */ 1144 #define IMM5 (I5U + 1) 1145 { 5, 1, NULL, NULL, 0, BFD_RELOC_NONE }, 1146 1147 /* The unsigned disp5 field in a sld.hu. */ 1148 #define D5_4U (IMM5 + 1) 1149 { 5, 0, insert_d5_4, extract_d5_4, V850_OPERAND_DISP, BFD_RELOC_V850_TDA_4_5_OFFSET }, 1150 1151 /* The IMM6 field in a callt instruction. */ 1152 #define IMM6 (D5_4U + 1) 1153 { 6, 0, NULL, NULL, 0, BFD_RELOC_V850_CALLT_6_7_OFFSET }, 1154 1155 /* The signed disp7 field in a format 4 insn. */ 1156 #define D7U (IMM6 + 1) 1157 { 7, 0, NULL, NULL, V850_OPERAND_DISP, BFD_RELOC_V850_TDA_7_7_OFFSET }, 1158 1159 /* The unsigned DISP8 field in a format 4 insn. */ 1160 #define D8_7U (D7U + 1) 1161 { 8, 0, insert_d8_7, extract_d8_7, V850_OPERAND_DISP, BFD_RELOC_V850_TDA_7_8_OFFSET }, 1162 1163 /* The unsigned DISP8 field in a format 4 insn. */ 1164 #define D8_6U (D8_7U + 1) 1165 { 8, 0, insert_d8_6, extract_d8_6, V850_OPERAND_DISP, BFD_RELOC_V850_TDA_6_8_OFFSET }, 1166 1167 /* The unsigned DISP8 field in a format 4 insn. */ 1168 #define V8 (D8_6U + 1) 1169 { 8, 0, insert_v8, extract_v8, 0, BFD_RELOC_NONE }, 1170 1171 /* The imm9 field in a multiply word. */ 1172 #define I9 (V8 + 1) 1173 { 9, 0, insert_i9, extract_i9, V850_OPERAND_SIGNED, BFD_RELOC_NONE }, 1174 1175 /* The unsigned imm9 field in a multiply word. */ 1176 #define U9 (I9 + 1) 1177 { 9, 0, insert_u9, extract_u9, 0, BFD_RELOC_NONE }, 1178 1179 /* The DISP9 field in a format 3 insn. */ 1180 #define D9 (U9 + 1) 1181 { 9, 0, insert_d9, extract_d9, V850_OPERAND_SIGNED | V850_OPERAND_DISP | V850_PCREL, BFD_RELOC_V850_9_PCREL }, 1182 1183 /* The DISP9 field in a format 3 insn, relaxable. */ 1184 #define D9_RELAX (D9 + 1) 1185 { 9, 0, insert_d9, extract_d9, V850_OPERAND_RELAX | V850_OPERAND_SIGNED | V850_OPERAND_DISP | V850_PCREL, BFD_RELOC_V850_9_PCREL }, 1186 1187 /* The imm16 field in a format 6 insn. */ 1188 #define I16 (D9_RELAX + 1) 1189 { 16, 16, NULL, NULL, V850_OPERAND_SIGNED, BFD_RELOC_16 }, 1190 1191 /* The signed 16 bit immediate following a prepare instruction. */ 1192 #define IMM16LO (I16 + 1) 1193 { 16, 32, NULL, NULL, V850E_IMMEDIATE16 | V850_OPERAND_SIGNED, BFD_RELOC_LO16 }, 1194 1195 /* The hi 16 bit immediate following a 32 bit instruction. */ 1196 #define IMM16HI (IMM16LO + 1) 1197 { 16, 16, NULL, NULL, V850E_IMMEDIATE16HI, BFD_RELOC_HI16 }, 1198 1199 /* The unsigned imm16 in a format 6 insn. */ 1200 #define I16U (IMM16HI + 1) 1201 { 16, 16, NULL, NULL, 0, BFD_RELOC_16 }, 1202 1203 /* The disp16 field in a format 8 insn. */ 1204 #define D16 (I16U + 1) 1205 { 16, 16, NULL, NULL, V850_OPERAND_SIGNED | V850_OPERAND_DISP, BFD_RELOC_16 }, 1206 1207 /* The disp16 field in an format 7 unsigned byte load insn. */ 1208 #define D16_16 (D16 + 1) 1209 { 16, 0, insert_d16_16, extract_d16_16, V850_OPERAND_SIGNED | V850_OPERAND_DISP, BFD_RELOC_V850_16_SPLIT_OFFSET }, 1210 1211 /* The disp16 field in a format 6 insn. */ 1212 #define D16_15 (D16_16 + 1) 1213 { 16, 0, insert_d16_15, extract_d16_15, V850_OPERAND_SIGNED | V850_OPERAND_DISP , BFD_RELOC_V850_16_S1 }, 1214 1215 /* The unsigned DISP16 field in a format 7 insn. */ 1216 #define D16_LOOP (D16_15 + 1) 1217 { 16, 0, insert_u16_loop, extract_u16_loop, V850_OPERAND_RELAX | V850_OPERAND_DISP | V850_PCREL | V850_INVERSE_PCREL, BFD_RELOC_V850_16_PCREL }, 1218 1219 /* The DISP17 field in a format 7 insn. */ 1220 #define D17_16 (D16_LOOP + 1) 1221 { 17, 0, insert_d17_16, extract_d17_16, V850_OPERAND_SIGNED | V850_OPERAND_DISP | V850_PCREL, BFD_RELOC_V850_17_PCREL }, 1222 1223 /* The DISP22 field in a format 4 insn, relaxable. 1224 This _must_ follow D9_RELAX; the assembler assumes that the longer 1225 version immediately follows the shorter version for relaxing. */ 1226 #define D22 (D17_16 + 1) 1227 { 22, 0, insert_d22, extract_d22, V850_OPERAND_SIGNED | V850_OPERAND_DISP | V850_PCREL, BFD_RELOC_V850_22_PCREL }, 1228 1229 #define D23 (D22 + 1) 1230 { 23, 0, insert_d23, extract_d23, V850E_IMMEDIATE23 | V850_OPERAND_SIGNED | V850_OPERAND_DISP, BFD_RELOC_V850_23 }, 1231 1232 #define D23_ALIGN1 (D23 + 1) 1233 { 23, 0, insert_d23_align1, extract_d23, V850E_IMMEDIATE23 | V850_OPERAND_SIGNED | V850_OPERAND_DISP, BFD_RELOC_V850_23 }, 1234 1235 /* The 32 bit immediate following a 32 bit instruction. */ 1236 #define IMM32 (D23_ALIGN1 + 1) 1237 { 32, 32, NULL, NULL, V850E_IMMEDIATE32, BFD_RELOC_32 }, 1238 1239 #define D32_31 (IMM32 + 1) 1240 { 32, 32, NULL, NULL, V850E_IMMEDIATE32 | V850_OPERAND_SIGNED | V850_OPERAND_DISP, BFD_RELOC_V850_32_ABS }, 1241 1242 #define D32_31_PCREL (D32_31 + 1) 1243 { 32, 32, NULL, NULL, V850E_IMMEDIATE32 | V850_OPERAND_SIGNED | V850_OPERAND_DISP | V850_PCREL, BFD_RELOC_V850_32_PCREL }, 1244 1245 #define POS_U (D32_31_PCREL + 1) 1246 { 0, 0, insert_POS, extract_POS_U, 0, BFD_RELOC_NONE }, 1247 1248 #define POS_M (POS_U + 1) 1249 { 0, 0, insert_POS, extract_POS_L, 0, BFD_RELOC_NONE }, 1250 1251 #define POS_L (POS_M + 1) 1252 { 0, 0, insert_POS, extract_POS_L, 0, BFD_RELOC_NONE }, 1253 1254 #define WIDTH_U (POS_L + 1) 1255 { 0, 0, insert_WIDTH, extract_WIDTH_U, 0, BFD_RELOC_NONE }, 1256 1257 #define WIDTH_M (WIDTH_U + 1) 1258 { 0, 0, insert_WIDTH, extract_WIDTH_M, 0, BFD_RELOC_NONE }, 1259 1260 #define WIDTH_L (WIDTH_M + 1) 1261 { 0, 0, insert_WIDTH, extract_WIDTH_L, 0, BFD_RELOC_NONE }, 1262 1263 #define SELID (WIDTH_L + 1) 1264 { 5, 27, insert_SELID, extract_SELID, 0, BFD_RELOC_NONE }, 1265 1266 #define RIE_IMM5 (SELID + 1) 1267 { 5, 11, NULL, NULL, 0, BFD_RELOC_NONE }, 1268 1269 #define RIE_IMM4 (RIE_IMM5 + 1) 1270 { 4, 0, NULL, NULL, 0, BFD_RELOC_NONE }, 1271 1272 #define VECTOR8 (RIE_IMM4 + 1) 1273 { 0, 0, insert_VECTOR8, extract_VECTOR8, 0, BFD_RELOC_NONE }, 1274 1275 #define VECTOR5 (VECTOR8 + 1) 1276 { 0, 0, insert_VECTOR5, extract_VECTOR5, 0, BFD_RELOC_NONE }, 1277 1278 #define VR1 (VECTOR5 + 1) 1279 { 5, 0, NULL, NULL, V850_OPERAND_VREG, BFD_RELOC_NONE }, 1280 1281 #define VR2 (VR1 + 1) 1282 { 5, 11, NULL, NULL, V850_OPERAND_VREG, BFD_RELOC_NONE }, 1283 1284 #define CACHEOP (VR2 + 1) 1285 { 0, 0, insert_CACHEOP, extract_CACHEOP, V850_OPERAND_CACHEOP, BFD_RELOC_NONE }, 1286 1287 #define PREFOP (CACHEOP + 1) 1288 { 0, 0, insert_PREFOP, extract_PREFOP, V850_OPERAND_PREFOP, BFD_RELOC_NONE }, 1289 1290 #define IMM10U (PREFOP + 1) 1291 { 0, 0, insert_IMM10U, extract_IMM10U, 0, BFD_RELOC_NONE }, 1292 }; 1293 1294 1295 /* Reg - Reg instruction format (Format I). */ 1297 #define IF1 {R1, R2} 1298 1299 /* Imm - Reg instruction format (Format II). */ 1300 #define IF2 {I5, R2} 1301 1302 /* Conditional branch instruction format (Format III). */ 1303 #define IF3 {D9_RELAX} 1304 1305 /* 3 operand instruction (Format VI). */ 1306 #define IF6 {I16, R1, R2} 1307 1308 /* 3 operand instruction (Format VI). */ 1309 #define IF6U {I16U, R1, R2} 1310 1311 /* Conditional branch instruction format (Format VII). */ 1312 #define IF7 {D17_16} 1313 1314 1315 /* The opcode table. 1317 1318 The format of the opcode table is: 1319 1320 NAME OPCODE MASK { OPERANDS } MEMOP PROCESSOR 1321 1322 NAME is the name of the instruction. 1323 OPCODE is the instruction opcode. 1324 MASK is the opcode mask; this is used to tell the disassembler 1325 which bits in the actual opcode must match OPCODE. 1326 OPERANDS is the list of operands. 1327 MEMOP specifies which operand (if any) is a memory operand. 1328 PROCESSORS specifies which CPU(s) support the opcode. 1329 1330 The disassembler reads the table in order and prints the first 1331 instruction which matches, so this table is sorted to put more 1332 specific instructions before more general instructions. It is also 1333 sorted by major opcode. 1334 1335 The table is also sorted by name. This is used by the assembler. 1336 When parsing an instruction the assembler finds the first occurance 1337 of the name of the instruciton in this table and then attempts to 1338 match the instruction's arguments with description of the operands 1339 associated with the entry it has just found in this table. If the 1340 match fails the assembler looks at the next entry in this table. 1341 If that entry has the same name as the previous entry, then it 1342 tries to match the instruction against that entry and so on. This 1343 is how the assembler copes with multiple, different formats of the 1344 same instruction. */ 1345 1346 const struct v850_opcode v850_opcodes[] = 1347 { 1348 /* Standard instructions. */ 1349 { "add", OP (0x0e), OP_MASK, IF1, 0, PROCESSOR_ALL }, 1350 { "add", OP (0x12), OP_MASK, IF2, 0, PROCESSOR_ALL }, 1351 1352 { "addi", OP (0x30), OP_MASK, IF6, 0, PROCESSOR_ALL }, 1353 1354 { "adf", two (0x07e0, 0x03a0), two (0x07e0, 0x07e1), {CCCC_NOTSA, R1, R2, R3}, 0, PROCESSOR_V850E2_UP }, 1355 1356 { "and", OP (0x0a), OP_MASK, IF1, 0, PROCESSOR_ALL }, 1357 1358 { "andi", OP (0x36), OP_MASK, IF6U, 0, PROCESSOR_ALL }, 1359 1360 /* Signed integer. */ 1361 { "bge", BOP (0xe), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 1362 { "bgt", BOP (0xf), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 1363 { "ble", BOP (0x7), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 1364 { "blt", BOP (0x6), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 1365 /* Unsigned integer. */ 1366 { "bh", BOP (0xb), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 1367 { "bl", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 1368 { "bnh", BOP (0x3), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 1369 { "bnl", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 1370 /* Common. */ 1371 { "be", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 1372 { "bne", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 1373 /* Others. */ 1374 { "bc", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 1375 { "bf", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 1376 { "bn", BOP (0x4), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 1377 { "bnc", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 1378 { "bnv", BOP (0x8), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 1379 { "bnz", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 1380 { "bp", BOP (0xc), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 1381 { "br", BOP (0x5), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 1382 { "bsa", BOP (0xd), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 1383 { "bt", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 1384 { "bv", BOP (0x0), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 1385 { "bz", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 1386 1387 /* Signed integer. */ 1388 { "bge", two (0x07ee, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, 1389 { "bgt", two (0x07ef, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, 1390 { "ble", two (0x07e7, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, 1391 { "blt", two (0x07e6, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, 1392 /* Unsigned integer. */ 1393 { "bh", two (0x07eb, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, 1394 { "bl", two (0x07e1, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, 1395 { "bnh", two (0x07e3, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, 1396 { "bnl", two (0x07e9, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, 1397 /* Common. */ 1398 { "be", two (0x07e2, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, 1399 { "bne", two (0x07ea, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, 1400 /* Others. */ 1401 { "bc", two (0x07e1, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, 1402 { "bf", two (0x07ea, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, 1403 { "bn", two (0x07e4, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, 1404 { "bnc", two (0x07e9, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, 1405 { "bnv", two (0x07e8, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, 1406 { "bnz", two (0x07ea, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, 1407 { "bp", two (0x07ec, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, 1408 { "br", two (0x07e5, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, 1409 { "bsa", two (0x07ed, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, 1410 { "bt", two (0x07e2, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, 1411 { "bv", two (0x07e0, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, 1412 { "bz", two (0x07e2, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, 1413 /* Bcond disp17 Gas local alias(not defined in spec). */ 1414 1415 /* Signed integer. */ 1416 { "bge17", two (0x07ee, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, 1417 { "bgt17", two (0x07ef, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, 1418 { "ble17", two (0x07e7, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, 1419 { "blt17", two (0x07e6, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, 1420 /* Unsigned integer. */ 1421 { "bh17", two (0x07eb, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, 1422 { "bl17", two (0x07e1, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, 1423 { "bnh17", two (0x07e3, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, 1424 { "bnl17", two (0x07e9, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, 1425 /* Common. */ 1426 { "be17", two (0x07e2, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, 1427 { "bne17", two (0x07ea, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, 1428 /* Others. */ 1429 { "bc17", two (0x07e1, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, 1430 { "bf17", two (0x07ea, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, 1431 { "bn17", two (0x07e4, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, 1432 { "bnc17", two (0x07e9, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, 1433 { "bnv17", two (0x07e8, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, 1434 { "bnz17", two (0x07ea, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, 1435 { "bp17", two (0x07ec, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, 1436 { "br17", two (0x07e5, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, 1437 { "bsa17", two (0x07ed, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, 1438 { "bt17", two (0x07e2, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, 1439 { "bv17", two (0x07e0, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, 1440 { "bz17", two (0x07e2, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, 1441 1442 { "bsh", two (0x07e0, 0x0342), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 }, 1443 1444 { "bsw", two (0x07e0, 0x0340), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 }, 1445 1446 /* v850e3v5 bitfield instructions. */ 1447 { "bins", two (0x07e0, 0x0090), two (0x07e0, 0x07f1), {R1, POS_U, WIDTH_U, R2}, 0, PROCESSOR_V850E3V5_UP }, 1448 { "bins", two (0x07e0, 0x00b0), two (0x07e0, 0x07f1), {R1, POS_M, WIDTH_M, R2}, 0, PROCESSOR_V850E3V5_UP }, 1449 { "bins", two (0x07e0, 0x00d0), two (0x07e0, 0x07f1), {R1, POS_L, WIDTH_L, R2}, 0, PROCESSOR_V850E3V5_UP }, 1450 /* Gas local alias(not defined in spec). */ 1451 { "binsu",two (0x07e0, 0x0090), two (0x07e0, 0x07f1), {R1, POS_U, WIDTH_U, R2}, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, 1452 { "binsm",two (0x07e0, 0x00b0), two (0x07e0, 0x07f1), {R1, POS_M, WIDTH_M, R2}, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, 1453 { "binsl",two (0x07e0, 0x00d0), two (0x07e0, 0x07f1), {R1, POS_L, WIDTH_L, R2}, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, 1454 1455 { "cache", two (0xe7e0, 0x0160), two (0xe7e0, 0x07ff), {CACHEOP, R1}, 2, PROCESSOR_V850E3V5_UP }, 1456 1457 { "callt", one (0x0200), one (0xffc0), {IMM6}, 0, PROCESSOR_NOT_V850 }, 1458 1459 { "caxi", two (0x07e0, 0x00ee), two (0x07e0, 0x07ff), {R1, R2, R3}, 1, PROCESSOR_V850E2_UP }, 1460 1461 { "clr1", two (0x87c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 3, PROCESSOR_ALL }, 1462 { "clr1", two (0x07e0, 0x00e4), two (0x07e0, 0xffff), {R2, R1}, 3, PROCESSOR_NOT_V850 }, 1463 1464 { "cmov", two (0x07e0, 0x0320), two (0x07e0, 0x07e1), {MOVCC, R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, 1465 { "cmov", two (0x07e0, 0x0300), two (0x07e0, 0x07e1), {MOVCC, I5, R2, R3}, 0, PROCESSOR_NOT_V850 }, 1466 1467 { "cmp", OP (0x0f), OP_MASK, IF1, 0, PROCESSOR_ALL }, 1468 { "cmp", OP (0x13), OP_MASK, IF2, 0, PROCESSOR_ALL }, 1469 1470 { "ctret", two (0x07e0, 0x0144), two (0xffff, 0xffff), {0}, 0, PROCESSOR_NOT_V850 }, 1471 1472 { "dbcp", one (0xe840), one (0xffff), {0}, 0, PROCESSOR_V850E3V5_UP }, 1473 1474 { "dbhvtrap", one (0xe040), one (0xffff), {0}, 0, PROCESSOR_V850E3V5_UP }, 1475 1476 { "dbpush", two (0x5fe0, 0x0160), two (0xffe0, 0x07ff), {R1, R3}, 0, PROCESSOR_V850E3V5_UP }, 1477 1478 { "dbret", two (0x07e0, 0x0146), two (0xffff, 0xffff), {0}, 0, PROCESSOR_NOT_V850 }, 1479 1480 { "dbtag", two (0xcfe0, 0x0160), two (0xffe0, 0x07ff), {IMM10U}, 0, PROCESSOR_V850E3V5_UP }, 1481 1482 { "dbtrap", one (0xf840), one (0xffff), {0}, 0, PROCESSOR_NOT_V850 }, 1483 1484 { "di", two (0x07e0, 0x0160), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL }, 1485 1486 { "dispose", two (0x0640, 0x0000), two (0xffc0, 0x0000), {IMM5, LIST12, R2_DISPOSE},3, PROCESSOR_NOT_V850 }, 1487 { "dispose", two (0x0640, 0x0000), two (0xffc0, 0x001f), {IMM5, LIST12}, 0, PROCESSOR_NOT_V850 }, 1488 1489 { "div", two (0x07e0, 0x02c0), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, 1490 1491 { "divh", two (0x07e0, 0x0280), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, 1492 { "divh", OP (0x02), OP_MASK, {R1_NOTR0, R2_NOTR0}, 0, PROCESSOR_ALL }, 1493 1494 { "divhn", two (0x07e0, 0x0280), two (0x07e0, 0x07c3), {I5DIV1, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION }, 1495 1496 { "divhu", two (0x07e0, 0x0282), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, 1497 1498 { "divhun", two (0x07e0, 0x0282), two (0x07e0, 0x07c3), {I5DIV1, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION }, 1499 { "divn", two (0x07e0, 0x02c0), two (0x07e0, 0x07c3), {I5DIV2, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION }, 1500 1501 { "divq", two (0x07e0, 0x02fc), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_UP }, 1502 1503 { "divqu", two (0x07e0, 0x02fe), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_UP }, 1504 1505 { "divu", two (0x07e0, 0x02c2), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, 1506 1507 { "divun", two (0x07e0, 0x02c2), two (0x07e0, 0x07c3), {I5DIV2, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION }, 1508 1509 { "dst", two (0x07e0, 0x0134), two (0xfffff, 0xffff), {0}, 0, PROCESSOR_V850E3V5_UP }, 1510 1511 { "ei", two (0x87e0, 0x0160), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL }, 1512 1513 { "eiret", two (0x07e0, 0x0148), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E2_UP }, 1514 1515 { "est", two (0x07e0, 0x0132), two (0xfffff, 0xffff), {0}, 0, PROCESSOR_V850E3V5_UP }, 1516 1517 { "feret", two (0x07e0, 0x014a), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E2_UP }, 1518 1519 { "fetrap", one (0x0040), one (0x87ff), {I4U_NOTIMM0}, 0, PROCESSOR_V850E2_UP }, 1520 1521 { "halt", two (0x07e0, 0x0120), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL }, 1522 1523 { "hsh", two (0x07e0, 0x0346), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2_UP }, 1524 1525 { "hsw", two (0x07e0, 0x0344), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 }, 1526 1527 { "hvcall", two (0xd7e0, 0x4160), two (0xffe0, 0x41ff), {VECTOR8}, 0, PROCESSOR_V850E3V5_UP }, 1528 { "hvtrap", two (0x07e0, 0x0110), two (0xffe0, 0xffff), {VECTOR5}, 0, PROCESSOR_V850E3V5_UP }, 1529 1530 { "jarl", two (0xc7e0, 0x0160), two (0xffe0, 0x07ff), {R1, R3_NOTR0}, 1, PROCESSOR_V850E3V5_UP}, 1531 { "jarl", two (0x0780, 0x0000), two (0x07c0, 0x0001), {D22, R2_NOTR0}, 0, PROCESSOR_ALL}, 1532 { "jarl", one (0x02e0), one (0xffe0), {D32_31_PCREL, R1_NOTR0}, 0, PROCESSOR_V850E2_UP }, 1533 /* Gas local alias (not defined in spec). */ 1534 { "jarlr", two (0xc7e0, 0x0160), two (0xffe0, 0x07ff), {R1, R3_NOTR0}, 1, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS}, 1535 /* Gas local alias of jarl imm22 (not defined in spec). */ 1536 { "jarl22", two (0x0780, 0x0000), two (0x07c0, 0x0001), {D22, R2_NOTR0}, 0, PROCESSOR_ALL | PROCESSOR_OPTION_ALIAS}, 1537 /* Gas local alias of jarl imm32 (not defined in spec). */ 1538 { "jarl32", one (0x02e0), one (0xffe0), {D32_31_PCREL, R1_NOTR0}, 0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS }, 1539 { "jarlw", one (0x02e0), one (0xffe0), {D32_31_PCREL, R1_NOTR0}, 0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS }, 1540 1541 { "jmp", two (0x06e0, 0x0000), two (0xffe0, 0x0001), {D32_31, R1}, 2, PROCESSOR_V850E3V5_UP }, 1542 { "jmp", one (0x06e0), one (0xffe0), {D32_31, R1}, 2, PROCESSOR_V850E2 | PROCESSOR_V850E2V3 }, 1543 { "jmp", one (0x0060), one (0xffe0), {R1}, 1, PROCESSOR_ALL }, 1544 /* Gas local alias of jmp disp22(not defined in spec). */ 1545 { "jmp22", one (0x0060), one (0xffe0), {R1}, 1, PROCESSOR_ALL | PROCESSOR_OPTION_ALIAS }, 1546 /* Gas local alias of jmp disp32(not defined in spec). */ 1547 { "jmp32", one (0x06e0), one (0xffe0), {D32_31, R1}, 2, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS }, 1548 { "jmpw", one (0x06e0), one (0xffe0), {D32_31, R1}, 2, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS }, 1549 1550 { "jr", two (0x0780, 0x0000), two (0xffc0, 0x0001), {D22}, 0, PROCESSOR_ALL }, 1551 { "jr", one (0x02e0), one (0xffff), {D32_31_PCREL}, 0, PROCESSOR_V850E2_UP }, 1552 /* Gas local alias of mov imm22(not defined in spec). */ 1553 { "jr22", two (0x0780, 0x0000), two (0xffc0, 0x0001), {D22}, 0, PROCESSOR_ALL | PROCESSOR_OPTION_ALIAS }, 1554 /* Gas local alias of mov imm32(not defined in spec). */ 1555 { "jr32", one (0x02e0), one (0xffff), {D32_31_PCREL}, 0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS }, 1556 1557 /* Alias of bcond (same as CA850). */ 1558 { "jgt", BOP (0xf), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 1559 { "jge", BOP (0xe), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 1560 { "jlt", BOP (0x6), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 1561 { "jle", BOP (0x7), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 1562 /* Unsigned integer. */ 1563 { "jh", BOP (0xb), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 1564 { "jnh", BOP (0x3), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 1565 { "jl", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 1566 { "jnl", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 1567 /* Common. */ 1568 { "je", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 1569 { "jne", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 1570 /* Others. */ 1571 { "jv", BOP (0x0), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 1572 { "jnv", BOP (0x8), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 1573 { "jn", BOP (0x4), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 1574 { "jp", BOP (0xc), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 1575 { "jc", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 1576 { "jnc", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 1577 { "jz", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 1578 { "jnz", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 1579 { "jbr", BOP (0x5), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 1580 1581 1582 { "ldacc", two (0x07e0, 0x0bc4), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_EXTENSION }, 1583 1584 { "ld.b", two (0x0700, 0x0000), two (0x07e0, 0x0000), {D16, R1, R2}, 2, PROCESSOR_ALL }, 1585 { "ld.b", two (0x0780, 0x0005), two (0xffe0, 0x000f), {D23, R1, R3}, 2, PROCESSOR_V850E2_UP }, 1586 { "ld.b23", two (0x0780, 0x0005), two (0x07e0, 0x000f), {D23, R1, R3}, 2, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS }, 1587 1588 { "ld.bu", two (0x0780, 0x0001), two (0x07c0, 0x0001), {D16_16, R1, R2_NOTR0}, 2, PROCESSOR_NOT_V850 }, 1589 { "ld.bu", two (0x07a0, 0x0005), two (0xffe0, 0x000f), {D23, R1, R3}, 2, PROCESSOR_V850E2_UP }, 1590 { "ld.bu23", two (0x07a0, 0x0005), two (0x07e0, 0x000f), {D23, R1, R3}, 2, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS }, 1591 1592 { "ld.dw", two (0x07a0, 0x0009), two (0xffe0, 0x001f), {D23_ALIGN1, R1, R3_EVEN}, 2, PROCESSOR_V850E3V5_UP }, 1593 { "ld.dw23", two (0x07a0, 0x0009), two (0xffe0, 0x001f), {D23_ALIGN1, R1, R3_EVEN}, 2, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, 1594 1595 { "ld.h", two (0x0720, 0x0000), two (0x07e0, 0x0001), {D16_15, R1, R2}, 2, PROCESSOR_ALL }, 1596 { "ld.h", two (0x0780, 0x0007), two (0x07e0, 0x000f), {D23_ALIGN1, R1, R3}, 2, PROCESSOR_V850E2_UP }, 1597 { "ld.h23", two (0x0780, 0x0007), two (0x07e0, 0x000f), {D23_ALIGN1, R1, R3}, 2, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS }, 1598 1599 { "ld.hu", two (0x07e0, 0x0001), two (0x07e0, 0x0001), {D16_15, R1, R2_NOTR0}, 2, PROCESSOR_NOT_V850 }, 1600 { "ld.hu", two (0x07a0, 0x0007), two (0x07e0, 0x000f), {D23_ALIGN1, R1, R3}, 2, PROCESSOR_V850E2_UP }, 1601 { "ld.hu23", two (0x07a0, 0x0007), two (0x07e0, 0x000f), {D23_ALIGN1, R1, R3}, 2, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS }, 1602 1603 { "ld.w", two (0x0720, 0x0001), two (0x07e0, 0x0001), {D16_15, R1, R2}, 2, PROCESSOR_ALL }, 1604 { "ld.w", two (0x0780, 0x0009), two (0xffe0, 0x001f), {D23_ALIGN1, R1, R3}, 2, PROCESSOR_V850E2_UP }, 1605 { "ld.w23", two (0x0780, 0x0009), two (0x07e0, 0x001f), {D23_ALIGN1, R1, R3}, 2, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS }, 1606 1607 { "ldl.w", two (0x07e0, 0x0378), two (0xffe0, 0x07ff), {R1, R3}, 1, PROCESSOR_V850E3V5_UP }, 1608 1609 { "ldsr", two (0x07e0, 0x0020), two (0x07e0, 0x07ff), {R1, SR2, SELID}, 0, PROCESSOR_V850E3V5_UP }, 1610 { "ldsr", two (0x07e0, 0x0020), two (0x07e0, 0x07ff), {R1, SR2}, 0, PROCESSOR_V850E3V5_UP }, 1611 { "ldsr", two (0x07e0, 0x0020), two (0x07e0, 0x07ff), {R1, OLDSR2}, 0, (PROCESSOR_ALL & (~ PROCESSOR_V850E3V5_UP)) }, 1612 1613 { "ldtc.gr", two (0x07e0, 0x0032), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_V850E3V5_UP }, 1614 { "ldtc.sr", two (0x07e0, 0x0030), two (0x07e0, 0x07ff), {R1, SR2, SELID}, 0, PROCESSOR_V850E3V5_UP }, 1615 { "ldtc.sr", two (0x07e0, 0x0030), two (0x07e0, 0x07ff), {R1, SR2}, 0, PROCESSOR_V850E3V5_UP }, 1616 1617 { "ldtc.vr", two (0x07e0, 0x0832), two (0x07e0, 0xffff), {R1, VR2}, 0, PROCESSOR_V850E3V5_UP }, 1618 { "ldtc.pc", two (0x07e0, 0xf832), two (0x07e0, 0xffff), {R1}, 0, PROCESSOR_V850E3V5_UP }, 1619 1620 { "ldvc.sr", two (0x07e0, 0x0034), two (0x07e0, 0x07ff), {R1, SR2, SELID}, 0, PROCESSOR_V850E3V5_UP }, 1621 { "ldvc.sr", two (0x07e0, 0x0034), two (0x07e0, 0x07ff), {R1, SR2}, 0, PROCESSOR_V850E3V5_UP }, 1622 1623 { "loop", two (0x06e0, 0x0001), two (0xffe0, 0x0001), {R1, D16_LOOP}, 0, PROCESSOR_V850E3V5_UP }, 1624 1625 { "macacc", two (0x07e0, 0x0bc0), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_EXTENSION }, 1626 1627 { "mac", two (0x07e0, 0x03c0), two (0x07e0, 0x0fe1), {R1, R2, R3_EVEN, R4_EVEN}, 0, PROCESSOR_V850E2_UP }, 1628 1629 { "macu", two (0x07e0, 0x03e0), two (0x07e0, 0x0fe1), {R1, R2, R3_EVEN, R4_EVEN}, 0, PROCESSOR_V850E2_UP }, 1630 1631 { "macuacc", two (0x07e0, 0x0bc2), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_EXTENSION }, 1632 1633 { "mov", OP (0x00), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, 1634 { "mov", OP (0x10), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL }, 1635 { "mov", one (0x0620), one (0xffe0), {IMM32, R1}, 0, PROCESSOR_NOT_V850 }, 1636 /* Gas local alias of mov imm32(not defined in spec). */ 1637 { "movl", one (0x0620), one (0xffe0), {IMM32, R1}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_ALIAS }, 1638 1639 { "movea", OP (0x31), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL }, 1640 1641 { "movhi", OP (0x32), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL }, 1642 1643 { "mul", two (0x07e0, 0x0220), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, 1644 { "mul", two (0x07e0, 0x0240), two (0x07e0, 0x07c3), {I9, R2, R3}, 0, PROCESSOR_NOT_V850 }, 1645 1646 { "mulh", OP (0x17), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL }, 1647 { "mulh", OP (0x07), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, 1648 1649 { "mulhi", OP (0x37), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL }, 1650 1651 { "mulu", two (0x07e0, 0x0222), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, 1652 { "mulu", two (0x07e0, 0x0242), two (0x07e0, 0x07c3), {U9, R2, R3}, 0, PROCESSOR_NOT_V850 }, 1653 1654 { "nop", one (0x00), one (0xffff), {0}, 0, PROCESSOR_ALL }, 1655 1656 { "not", OP (0x01), OP_MASK, IF1, 0, PROCESSOR_ALL }, 1657 1658 { "not1", two (0x47c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 3, PROCESSOR_ALL }, 1659 { "not1", two (0x07e0, 0x00e2), two (0x07e0, 0xffff), {R2, R1}, 3, PROCESSOR_NOT_V850 }, 1660 1661 { "or", OP (0x08), OP_MASK, IF1, 0, PROCESSOR_ALL }, 1662 1663 { "ori", OP (0x34), OP_MASK, IF6U, 0, PROCESSOR_ALL }, 1664 1665 { "popsp", two (0x67e0, 0x0160), two (0xffe0, 0x07ff), {R1, R3}, 0, PROCESSOR_V850E3V5_UP }, 1666 1667 { "pref", two (0xdfe0, 0x0160), two (0xffe0, 0x07ff), {PREFOP, R1}, 2, PROCESSOR_V850E3V5_UP }, 1668 1669 { "prepare", two (0x0780, 0x0003), two (0xffc0, 0x001f), {LIST12, IMM5, SP}, 0, PROCESSOR_NOT_V850 }, 1670 { "prepare", two (0x0780, 0x000b), two (0xffc0, 0x001f), {LIST12, IMM5, IMM16LO},0, PROCESSOR_NOT_V850 }, 1671 { "prepare", two (0x0780, 0x0013), two (0xffc0, 0x001f), {LIST12, IMM5, IMM16HI},0, PROCESSOR_NOT_V850 }, 1672 { "prepare", two (0x0780, 0x001b), two (0xffc0, 0x001f), {LIST12, IMM5, IMM32}, 0, PROCESSOR_NOT_V850 }, 1673 { "prepare", two (0x0780, 0x0001), two (0xffc0, 0x001f), {LIST12, IMM5}, 0, PROCESSOR_NOT_V850 }, 1674 1675 { "pushsp", two (0x47e0, 0x0160), two (0xffe0, 0x07ff), {R1, R3}, 0, PROCESSOR_V850E3V5_UP }, 1676 1677 { "rotl", two (0x07e0, 0x00c6), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E3V5_UP }, 1678 { "rotl", two (0x07e0, 0x00c4), two (0x07e0, 0x07ff), {I5U, R2, R3}, 0, PROCESSOR_V850E3V5_UP }, 1679 1680 { "reti", two (0x07e0, 0x0140), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL }, 1681 1682 { "sar", two (0x07e0, 0x00a2), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_UP }, 1683 { "sar", OP (0x15), OP_MASK, {I5U, R2}, 0, PROCESSOR_ALL }, 1684 { "sar", two (0x07e0, 0x00a0), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_ALL }, 1685 1686 { "sasf", two (0x07e0, 0x0200), two (0x07f0, 0xffff), {CCCC, R2}, 0, PROCESSOR_NOT_V850 }, 1687 1688 { "satadd", two (0x07e0, 0x03ba), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_UP }, 1689 { "satadd", OP (0x11), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL }, 1690 { "satadd", OP (0x06), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, 1691 1692 { "satsub", two (0x07e0, 0x039a), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_UP }, 1693 { "satsub", OP (0x05), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, 1694 1695 { "satsubi", OP (0x33), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL }, 1696 1697 { "satsubr", OP (0x04), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, 1698 1699 { "sbf", two (0x07e0, 0x0380), two (0x07e0, 0x07e1), {CCCC_NOTSA, R1, R2, R3}, 0, PROCESSOR_V850E2_UP }, 1700 1701 { "sch0l", two (0x07e0, 0x0364), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2_UP }, 1702 1703 { "sch0r", two (0x07e0, 0x0360), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2_UP }, 1704 1705 { "sch1l", two (0x07e0, 0x0366), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2_UP }, 1706 1707 { "sch1r", two (0x07e0, 0x0362), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2_UP }, 1708 1709 { "sdivhn", two (0x07e0, 0x0180), two (0x07e0, 0x07c3), {I5DIV3, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION }, 1710 { "sdivhun", two (0x07e0, 0x0182), two (0x07e0, 0x07c3), {I5DIV3, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION }, 1711 { "sdivn", two (0x07e0, 0x01c0), two (0x07e0, 0x07c3), {I5DIV3, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION }, 1712 { "sdivun", two (0x07e0, 0x01c2), two (0x07e0, 0x07c3), {I5DIV3, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION }, 1713 1714 { "set1", two (0x07c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 3, PROCESSOR_ALL }, 1715 { "set1", two (0x07e0, 0x00e0), two (0x07e0, 0xffff), {R2, R1}, 3, PROCESSOR_NOT_V850 }, 1716 1717 { "setf", two (0x07e0, 0x0000), two (0x07f0, 0xffff), {CCCC, R2}, 0, PROCESSOR_ALL }, 1718 1719 { "shl", two (0x07e0, 0x00c2), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_UP }, 1720 { "shl", OP (0x16), OP_MASK, {I5U, R2}, 0, PROCESSOR_ALL }, 1721 { "shl", two (0x07e0, 0x00c0), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_ALL }, 1722 1723 { "shr", two (0x07e0, 0x0082), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_UP }, 1724 { "shr", OP (0x14), OP_MASK, {I5U, R2}, 0, PROCESSOR_ALL }, 1725 { "shr", two (0x07e0, 0x0080), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_ALL }, 1726 1727 { "sld.b", one (0x0300), one (0x0780), {D7U, EP, R2}, 2, PROCESSOR_ALL }, 1728 1729 { "sld.bu", one (0x0060), one (0x07f0), {D4U, EP, R2_NOTR0}, 2, PROCESSOR_NOT_V850 }, 1730 1731 { "sld.h", one (0x0400), one (0x0780), {D8_7U,EP, R2}, 2, PROCESSOR_ALL }, 1732 1733 { "sld.hu", one (0x0070), one (0x07f0), {D5_4U,EP, R2_NOTR0}, 2, PROCESSOR_NOT_V850 }, 1734 1735 { "sld.w", one (0x0500), one (0x0781), {D8_6U,EP, R2}, 2, PROCESSOR_ALL }, 1736 1737 { "snooze", two (0x0fe0, 0x0120), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E3V5_UP }, 1738 1739 { "sst.b", one (0x0380), one (0x0780), {R2, D7U, EP}, 3, PROCESSOR_ALL }, 1740 1741 { "sst.h", one (0x0480), one (0x0780), {R2, D8_7U,EP}, 3, PROCESSOR_ALL }, 1742 1743 { "sst.w", one (0x0501), one (0x0781), {R2, D8_6U,EP}, 3, PROCESSOR_ALL }, 1744 1745 { "stacch", two (0x07e0, 0x0bca), two (0x07ff, 0xffff), {R2}, 0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_EXTENSION }, 1746 { "staccl", two (0x07e0, 0x0bc8), two (0x07ff, 0xffff), {R2}, 0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_EXTENSION }, 1747 1748 { "st.b", two (0x0740, 0x0000), two (0x07e0, 0x0000), {R2, D16, R1}, 3, PROCESSOR_ALL }, 1749 { "st.b", two (0x0780, 0x000d), two (0x07e0, 0x000f), {R3, D23, R1}, 3, PROCESSOR_V850E2_UP }, 1750 { "st.b23", two (0x0780, 0x000d), two (0x07e0, 0x000f), {R3, D23, R1}, 3, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS }, 1751 1752 { "st.dw", two (0x07a0, 0x000f), two (0xffe0, 0x001f), {R3_EVEN, D23_ALIGN1, R1}, 3, PROCESSOR_V850E3V5_UP }, 1753 { "st.dw23", two (0x07a0, 0x000f), two (0xffe0, 0x001f), {R3_EVEN, D23_ALIGN1, R1}, 3, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, 1754 1755 { "st.h", two (0x0760, 0x0000), two (0x07e0, 0x0001), {R2, D16_15, R1}, 3, PROCESSOR_ALL }, 1756 { "st.h", two (0x07a0, 0x000d), two (0x07e0, 0x000f), {R3, D23_ALIGN1, R1}, 3, PROCESSOR_V850E2_UP }, 1757 { "st.h23", two (0x07a0, 0x000d), two (0x07e0, 0x000f), {R3, D23_ALIGN1, R1}, 3, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS }, 1758 1759 { "st.w", two (0x0760, 0x0001), two (0x07e0, 0x0001), {R2, D16_15, R1}, 3, PROCESSOR_ALL }, 1760 { "st.w", two (0x0780, 0x000f), two (0x07e0, 0x000f), {R3, D23_ALIGN1, R1}, 3, PROCESSOR_V850E2_UP }, 1761 { "st.w23", two (0x0780, 0x000f), two (0x07e0, 0x000f), {R3, D23_ALIGN1, R1}, 3, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS }, 1762 1763 { "stc.w", two (0x07e0, 0x037a), two (0xffe0, 0x07ff), {R3, R1}, 2, PROCESSOR_V850E3V5_UP }, 1764 1765 { "stsr", two (0x07e0, 0x0040), two (0x07e0, 0x07ff), {SR1, R2, SELID}, 0, PROCESSOR_V850E3V5_UP }, 1766 { "stsr", two (0x07e0, 0x0040), two (0x07e0, 0x07ff), {SR1, R2}, 0, PROCESSOR_V850E3V5_UP }, 1767 { "stsr", two (0x07e0, 0x0040), two (0x07e0, 0x07ff), {OLDSR1, R2}, 0, (PROCESSOR_ALL & (~ PROCESSOR_V850E3V5_UP)) }, 1768 1769 { "sttc.gr", two (0x07e0, 0x0052), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_V850E3V5_UP }, 1770 { "sttc.sr", two (0x07e0, 0x0050), two (0x07e0, 0x07ff), {SR1, R2, SELID}, 0, PROCESSOR_V850E3V5_UP }, 1771 { "sttc.sr", two (0x07e0, 0x0050), two (0x07e0, 0x07ff), {SR1, R2}, 0, PROCESSOR_V850E3V5_UP }, 1772 { "sttc.vr", two (0x07e0, 0x0852), two (0x07e0, 0xffff), {VR1, R2}, 0, PROCESSOR_V850E3V5_UP }, 1773 { "sttc.pc", two (0x07e0, 0xf852), two (0x07e0, 0xffff), {R2}, 0, PROCESSOR_V850E3V5_UP }, 1774 1775 { "stvc.sr", two (0x07e0, 0x0054), two (0x07e0, 0x07ff), {SR1, R2, SELID}, 0, PROCESSOR_V850E3V5_UP }, 1776 { "stvc.sr", two (0x07e0, 0x0054), two (0x07e0, 0x07ff), {SR1, R2}, 0, PROCESSOR_V850E3V5_UP }, 1777 1778 { "sub", OP (0x0d), OP_MASK, IF1, 0, PROCESSOR_ALL }, 1779 1780 { "subr", OP (0x0c), OP_MASK, IF1, 0, PROCESSOR_ALL }, 1781 1782 { "switch", one (0x0040), one (0xffe0), {R1_NOTR0}, 0, PROCESSOR_NOT_V850 }, 1783 1784 { "sxb", one (0x00a0), one (0xffe0), {R1}, 0, PROCESSOR_NOT_V850 }, 1785 1786 { "sxh", one (0x00e0), one (0xffe0), {R1}, 0, PROCESSOR_NOT_V850 }, 1787 1788 { "tlbai", two (0x87e0, 0x8960), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E3V5_UP }, 1789 { "tlbr", two (0x87e0, 0xe960), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E3V5_UP }, 1790 { "tlbs", two (0x87e0, 0xc160), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E3V5_UP }, 1791 { "tlbvi", two (0x87e0, 0x8160), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E3V5_UP }, 1792 { "tlbw", two (0x87e0, 0xe160), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E3V5_UP }, 1793 1794 { "trap", two (0x07e0, 0x0100), two (0xffe0, 0xffff), {I5U}, 0, PROCESSOR_ALL }, 1795 1796 { "tst", OP (0x0b), OP_MASK, IF1, 0, PROCESSOR_ALL }, 1797 1798 { "tst1", two (0xc7c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 3, PROCESSOR_ALL }, 1799 { "tst1", two (0x07e0, 0x00e6), two (0x07e0, 0xffff), {R2, R1}, 3, PROCESSOR_NOT_V850 }, 1800 1801 { "xor", OP (0x09), OP_MASK, IF1, 0, PROCESSOR_ALL }, 1802 1803 { "xori", OP (0x35), OP_MASK, IF6U, 0, PROCESSOR_ALL }, 1804 1805 { "zxb", one (0x0080), one (0xffe0), {R1}, 0, PROCESSOR_NOT_V850 }, 1806 1807 { "zxh", one (0x00c0), one (0xffe0), {R1}, 0, PROCESSOR_NOT_V850 }, 1808 1809 /* Floating point operation. */ 1810 { "absf.d", two (0x07e0, 0x0458), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, 1811 { "absf.s", two (0x07e0, 0x0448), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, 1812 { "addf.d", two (0x07e0, 0x0470), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, 1813 { "addf.s", two (0x07e0, 0x0460), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2V3_UP }, 1814 { "ceilf.dl", two (0x07e2, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, 1815 { "ceilf.dul", two (0x07f2, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, 1816 { "ceilf.duw", two (0x07f2, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP }, 1817 { "ceilf.dw", two (0x07e2, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP }, 1818 { "ceilf.sl", two (0x07e2, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, 1819 { "ceilf.sul", two (0x07f2, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, 1820 { "ceilf.suw", two (0x07f2, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, 1821 { "ceilf.sw", two (0x07e2, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, 1822 { "cmovf.d", two (0x07e0, 0x0410), two (0x0fe1, 0x0ff1), {FFF, R1_EVEN, R2_EVEN, R3_EVEN_NOTR0}, 0, PROCESSOR_V850E2V3_UP }, 1823 /* Default value for FFF is 0(not defined in spec). */ 1824 { "cmovf.d", two (0x07e0, 0x0410), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN_NOTR0}, 0, PROCESSOR_V850E2V3_UP }, 1825 { "cmovf.s", two (0x07e0, 0x0400), two (0x07e0, 0x07f1), {FFF, R1, R2, R3_NOTR0}, 0, PROCESSOR_V850E2V3_UP }, 1826 /* Default value for FFF is 0(not defined in spec). */ 1827 { "cmovf.s", two (0x07e0, 0x0400), two (0x07e0, 0x07ff), {R1, R2, R3_NOTR0}, 0, PROCESSOR_V850E2V3_UP }, 1828 { "cmpf.d", two (0x07e0, 0x0430), two (0x0fe1, 0x87f1), {FLOAT_CCCC, R2_EVEN, R1_EVEN, FFF}, 0, PROCESSOR_V850E2V3_UP }, 1829 { "cmpf.d", two (0x07e0, 0x0430), two (0x0fe1, 0x87ff), {FLOAT_CCCC, R2_EVEN, R1_EVEN}, 0, PROCESSOR_V850E2V3_UP }, 1830 { "cmpf.s", two (0x07e0, 0x0420), two (0x07e0, 0x87f1), {FLOAT_CCCC, R2, R1, FFF}, 0, PROCESSOR_V850E2V3_UP }, 1831 { "cmpf.s", two (0x07e0, 0x0420), two (0x07e0, 0x87ff), {FLOAT_CCCC, R2, R1}, 0, PROCESSOR_V850E2V3_UP }, 1832 { "cvtf.dl", two (0x07e4, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, 1833 { "cvtf.ds", two (0x07e3, 0x0452), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP }, 1834 { "cvtf.dul", two (0x07f4, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, 1835 { "cvtf.duw", two (0x07f4, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP }, 1836 { "cvtf.dw", two (0x07e4, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP }, 1837 { "cvtf.hs", two (0x07e2, 0x0442), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E3V5_UP }, 1838 { "cvtf.ld", two (0x07e1, 0x0452), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, 1839 { "cvtf.ls", two (0x07e1, 0x0442), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP }, 1840 { "cvtf.sd", two (0x07e2, 0x0452), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, 1841 { "cvtf.sl", two (0x07e4, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, 1842 { "cvtf.sh", two (0x07e3, 0x0442), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E3V5_UP }, 1843 { "cvtf.sul", two (0x07f4, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, 1844 { "cvtf.suw", two (0x07f4, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, 1845 { "cvtf.sw", two (0x07e4, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, 1846 { "cvtf.uld", two (0x07f1, 0x0452), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, 1847 { "cvtf.uls", two (0x07f1, 0x0442), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP }, 1848 { "cvtf.uwd", two (0x07f0, 0x0452), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, 1849 { "cvtf.uws", two (0x07f0, 0x0442), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, 1850 { "cvtf.wd", two (0x07e0, 0x0452), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, 1851 { "cvtf.ws", two (0x07e0, 0x0442), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, 1852 { "divf.d", two (0x07e0, 0x047e), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, 1853 { "divf.s", two (0x07e0, 0x046e), two (0x07e0, 0x07ff), {R1_NOTR0, R2, R3}, 0, PROCESSOR_V850E2V3_UP }, 1854 { "floorf.dl", two (0x07e3, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, 1855 { "floorf.dul", two (0x07f3, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, 1856 { "floorf.duw", two (0x07f3, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP }, 1857 { "floorf.dw", two (0x07e3, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP }, 1858 { "floorf.sl", two (0x07e3, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, 1859 { "floorf.sul", two (0x07f3, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, 1860 { "floorf.suw", two (0x07f3, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, 1861 { "floorf.sw", two (0x07e3, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, 1862 { "maddf.s", two (0x07e0, 0x0500), two (0x07e0, 0x0761), {R1, R2, R3, R4}, 0, PROCESSOR_V850E2V3 }, 1863 { "fmaf.s", two (0x07e0, 0x04e0), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E3V5_UP }, 1864 { "maxf.d", two (0x07e0, 0x0478), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, 1865 { "maxf.s", two (0x07e0, 0x0468), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2V3_UP }, 1866 { "minf.d", two (0x07e0, 0x047a), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, 1867 { "minf.s", two (0x07e0, 0x046a), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2V3_UP }, 1868 { "msubf.s", two (0x07e0, 0x0520), two (0x07e0, 0x0761), {R1, R2, R3, R4}, 0, PROCESSOR_V850E2V3 }, 1869 { "fmsf.s", two (0x07e0, 0x04e2), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E3V5_UP }, 1870 { "mulf.d", two (0x07e0, 0x0474), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, 1871 { "mulf.s", two (0x07e0, 0x0464), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2V3_UP }, 1872 { "negf.d", two (0x07e1, 0x0458), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, 1873 { "negf.s", two (0x07e1, 0x0448), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, 1874 { "nmaddf.s", two (0x07e0, 0x0540), two (0x07e0, 0x0761), {R1, R2, R3, R4}, 0, PROCESSOR_V850E2V3 }, 1875 { "fnmaf.s", two (0x07e0, 0x04e4), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E3V5_UP }, 1876 { "nmsubf.s", two (0x07e0, 0x0560), two (0x07e0, 0x0761), {R1, R2, R3, R4}, 0, PROCESSOR_V850E2V3 }, 1877 { "fnmsf.s", two (0x07e0, 0x04e6), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E3V5_UP }, 1878 { "recipf.d", two (0x07e1, 0x045e), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, 1879 { "recipf.s", two (0x07e1, 0x044e), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, 1880 1881 { "roundf.dl", two (0x07e0, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_EXTENSION }, 1882 { "roundf.dul", two (0x07f0, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_EXTENSION }, 1883 { "roundf.duw", two (0x07f0, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_EXTENSION }, 1884 { "roundf.dw", two (0x07e0, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_EXTENSION }, 1885 { "roundf.sl", two (0x07e0, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_EXTENSION }, 1886 { "roundf.sul", two (0x07f0, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_EXTENSION }, 1887 { "roundf.suw", two (0x07f0, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_EXTENSION }, 1888 { "roundf.sw", two (0x07e0, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_EXTENSION }, 1889 1890 { "rsqrtf.d", two (0x07e2, 0x045e), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, 1891 { "rsqrtf.s", two (0x07e2, 0x044e), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, 1892 { "sqrtf.d", two (0x07e0, 0x045e), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, 1893 { "sqrtf.s", two (0x07e0, 0x044e), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, 1894 { "subf.d", two (0x07e0, 0x0472), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, 1895 { "subf.s", two (0x07e0, 0x0462), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2V3_UP }, 1896 { "trfsr", two (0x07e0, 0x0400), two (0xffff, 0xfff1), {FFF}, 0, PROCESSOR_V850E2V3_UP }, 1897 { "trfsr", two (0x07e0, 0x0400), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E2V3_UP }, 1898 { "trncf.dl", two (0x07e1, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, 1899 { "trncf.dul", two (0x07f1, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, 1900 { "trncf.duw", two (0x07f1, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP }, 1901 { "trncf.dw", two (0x07e1, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP }, 1902 { "trncf.sl", two (0x07e1, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, 1903 { "trncf.sul", two (0x07f1, 0x0444), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, 1904 { "trncf.suw", two (0x07f1, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, 1905 { "trncf.sw", two (0x07e1, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, 1906 1907 /* Special instruction (from gdb) mov 1, r0. */ 1908 { "breakpoint", one (0x0001), one (0xffff), {UNUSED}, 0, PROCESSOR_ALL }, 1909 1910 { "synci", one (0x001c), one (0xffff), {0}, 0, PROCESSOR_V850E3V5_UP }, 1911 1912 { "synce", one (0x001d), one (0xffff), {0}, 0, PROCESSOR_V850E2V3_UP }, 1913 { "syncm", one (0x001e), one (0xffff), {0}, 0, PROCESSOR_V850E2V3_UP }, 1914 { "syncp", one (0x001f), one (0xffff), {0}, 0, PROCESSOR_V850E2V3_UP }, 1915 { "syscall", two (0xd7e0, 0x0160), two (0xffe0, 0xc7ff), {V8}, 0, PROCESSOR_V850E2V3_UP }, 1916 /* Alias of syncp. */ 1917 { "sync", one (0x001f), one (0xffff), {0}, 0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_ALIAS }, 1918 { "rmtrap", one (0xf040), one (0xffff), {0}, 0, PROCESSOR_V850E2V3_UP }, 1919 { "rie", one (0x0040), one (0xffff), {0}, 0, PROCESSOR_V850E2V3_UP }, 1920 { "rie", two (0x07f0, 0x0000), two (0x07f0, 0xffff), {RIE_IMM5,RIE_IMM4}, 0, PROCESSOR_V850E2V3_UP }, 1921 1922 { 0, 0, 0, {0}, 0, 0 }, 1923 } ; 1924 1925 const int v850_num_opcodes = 1926 sizeof (v850_opcodes) / sizeof (v850_opcodes[0]); 1927
