1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2014 Freescale Semiconductor, Inc. 4 */ 5 6 #include <common.h> 7 #include <i2c.h> 8 #include <asm/io.h> 9 #include <asm/arch/immap_ls102xa.h> 10 #include <asm/arch/clock.h> 11 #include <asm/arch/fsl_serdes.h> 12 #include <asm/arch/ls102xa_devdis.h> 13 #include <asm/arch/ls102xa_soc.h> 14 #include <asm/arch/ls102xa_sata.h> 15 #include <hwconfig.h> 16 #include <mmc.h> 17 #include <fsl_csu.h> 18 #include <fsl_esdhc.h> 19 #include <fsl_ifc.h> 20 #include <fsl_immap.h> 21 #include <netdev.h> 22 #include <fsl_mdio.h> 23 #include <tsec.h> 24 #include <fsl_sec.h> 25 #include <fsl_devdis.h> 26 #include <spl.h> 27 #include "../common/sleep.h" 28 #ifdef CONFIG_U_QE 29 #include <fsl_qe.h> 30 #endif 31 #include <fsl_validate.h> 32 33 34 DECLARE_GLOBAL_DATA_PTR; 35 36 #define VERSION_MASK 0x00FF 37 #define BANK_MASK 0x0001 38 #define CONFIG_RESET 0x1 39 #define INIT_RESET 0x1 40 41 #define CPLD_SET_MUX_SERDES 0x20 42 #define CPLD_SET_BOOT_BANK 0x40 43 44 #define BOOT_FROM_UPPER_BANK 0x0 45 #define BOOT_FROM_LOWER_BANK 0x1 46 47 #define LANEB_SATA (0x01) 48 #define LANEB_SGMII1 (0x02) 49 #define LANEC_SGMII1 (0x04) 50 #define LANEC_PCIEX1 (0x08) 51 #define LANED_PCIEX2 (0x10) 52 #define LANED_SGMII2 (0x20) 53 54 #define MASK_LANE_B 0x1 55 #define MASK_LANE_C 0x2 56 #define MASK_LANE_D 0x4 57 #define MASK_SGMII 0x8 58 59 #define KEEP_STATUS 0x0 60 #define NEED_RESET 0x1 61 62 #define SOFT_MUX_ON_I2C3_IFC 0x2 63 #define SOFT_MUX_ON_CAN3_USB2 0x8 64 #define SOFT_MUX_ON_QE_LCD 0x10 65 66 #define PIN_I2C3_IFC_MUX_I2C3 0x0 67 #define PIN_I2C3_IFC_MUX_IFC 0x1 68 #define PIN_CAN3_USB2_MUX_USB2 0x0 69 #define PIN_CAN3_USB2_MUX_CAN3 0x1 70 #define PIN_QE_LCD_MUX_LCD 0x0 71 #define PIN_QE_LCD_MUX_QE 0x1 72 73 struct cpld_data { 74 u8 cpld_ver; /* cpld revision */ 75 u8 cpld_ver_sub; /* cpld sub revision */ 76 u8 pcba_ver; /* pcb revision number */ 77 u8 system_rst; /* reset system by cpld */ 78 u8 soft_mux_on; /* CPLD override physical switches Enable */ 79 u8 cfg_rcw_src1; /* Reset config word 1 */ 80 u8 cfg_rcw_src2; /* Reset config word 2 */ 81 u8 vbank; /* Flash bank selection Control */ 82 u8 gpio; /* GPIO for TWR-ELEV */ 83 u8 i2c3_ifc_mux; 84 u8 mux_spi2; 85 u8 can3_usb2_mux; /* CAN3 and USB2 Selection */ 86 u8 qe_lcd_mux; /* QE and LCD Selection */ 87 u8 serdes_mux; /* Multiplexed pins for SerDes Lanes */ 88 u8 global_rst; /* reset with init CPLD reg to default */ 89 u8 rev1; /* Reserved */ 90 u8 rev2; /* Reserved */ 91 }; 92 93 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 94 static void cpld_show(void) 95 { 96 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); 97 98 printf("CPLD: V%x.%x\nPCBA: V%x.0\nVBank: %d\n", 99 in_8(&cpld_data->cpld_ver) & VERSION_MASK, 100 in_8(&cpld_data->cpld_ver_sub) & VERSION_MASK, 101 in_8(&cpld_data->pcba_ver) & VERSION_MASK, 102 in_8(&cpld_data->vbank) & BANK_MASK); 103 104 #ifdef CONFIG_DEBUG 105 printf("soft_mux_on =%x\n", 106 in_8(&cpld_data->soft_mux_on)); 107 printf("cfg_rcw_src1 =%x\n", 108 in_8(&cpld_data->cfg_rcw_src1)); 109 printf("cfg_rcw_src2 =%x\n", 110 in_8(&cpld_data->cfg_rcw_src2)); 111 printf("vbank =%x\n", 112 in_8(&cpld_data->vbank)); 113 printf("gpio =%x\n", 114 in_8(&cpld_data->gpio)); 115 printf("i2c3_ifc_mux =%x\n", 116 in_8(&cpld_data->i2c3_ifc_mux)); 117 printf("mux_spi2 =%x\n", 118 in_8(&cpld_data->mux_spi2)); 119 printf("can3_usb2_mux =%x\n", 120 in_8(&cpld_data->can3_usb2_mux)); 121 printf("qe_lcd_mux =%x\n", 122 in_8(&cpld_data->qe_lcd_mux)); 123 printf("serdes_mux =%x\n", 124 in_8(&cpld_data->serdes_mux)); 125 #endif 126 } 127 #endif 128 129 int checkboard(void) 130 { 131 puts("Board: LS1021ATWR\n"); 132 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 133 cpld_show(); 134 #endif 135 136 return 0; 137 } 138 139 void ddrmc_init(void) 140 { 141 struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR; 142 u32 temp_sdram_cfg, tmp; 143 144 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG); 145 146 out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS); 147 out_be32(&ddr->cs0_config, DDR_CS0_CONFIG); 148 149 out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0); 150 out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1); 151 out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2); 152 out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3); 153 out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4); 154 out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5); 155 156 #ifdef CONFIG_DEEP_SLEEP 157 if (is_warm_boot()) { 158 out_be32(&ddr->sdram_cfg_2, 159 DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT); 160 out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE); 161 out_be32(&ddr->init_ext_addr, (1 << 31)); 162 163 /* DRAM VRef will not be trained */ 164 out_be32(&ddr->ddr_cdr2, 165 DDR_DDR_CDR2 & ~DDR_CDR2_VREF_TRAIN_EN); 166 } else 167 #endif 168 { 169 out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2); 170 out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2); 171 } 172 173 out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE); 174 out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2); 175 176 out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL); 177 178 out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL); 179 180 out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2); 181 out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3); 182 183 out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1); 184 185 out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL); 186 out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL); 187 188 out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2); 189 190 /* DDR erratum A-009942 */ 191 tmp = in_be32(&ddr->debug[28]); 192 out_be32(&ddr->debug[28], tmp | 0x0070006f); 193 194 udelay(1); 195 196 #ifdef CONFIG_DEEP_SLEEP 197 if (is_warm_boot()) { 198 /* enter self-refresh */ 199 temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2); 200 temp_sdram_cfg |= SDRAM_CFG2_FRC_SR; 201 out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg); 202 203 temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN | SDRAM_CFG_BI); 204 } else 205 #endif 206 temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI); 207 208 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg); 209 210 #ifdef CONFIG_DEEP_SLEEP 211 if (is_warm_boot()) { 212 /* exit self-refresh */ 213 temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2); 214 temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR; 215 out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg); 216 } 217 #endif 218 } 219 220 int dram_init(void) 221 { 222 #if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)) 223 ddrmc_init(); 224 #endif 225 226 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); 227 228 #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD) 229 fsl_dp_resume(); 230 #endif 231 232 return 0; 233 } 234 235 #ifdef CONFIG_FSL_ESDHC 236 struct fsl_esdhc_cfg esdhc_cfg[1] = { 237 {CONFIG_SYS_FSL_ESDHC_ADDR}, 238 }; 239 240 int board_mmc_init(bd_t *bis) 241 { 242 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 243 244 return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); 245 } 246 #endif 247 248 int board_eth_init(bd_t *bis) 249 { 250 #ifdef CONFIG_TSEC_ENET 251 struct fsl_pq_mdio_info mdio_info; 252 struct tsec_info_struct tsec_info[4]; 253 int num = 0; 254 255 #ifdef CONFIG_TSEC1 256 SET_STD_TSEC_INFO(tsec_info[num], 1); 257 if (is_serdes_configured(SGMII_TSEC1)) { 258 puts("eTSEC1 is in sgmii mode.\n"); 259 tsec_info[num].flags |= TSEC_SGMII; 260 } 261 num++; 262 #endif 263 #ifdef CONFIG_TSEC2 264 SET_STD_TSEC_INFO(tsec_info[num], 2); 265 if (is_serdes_configured(SGMII_TSEC2)) { 266 puts("eTSEC2 is in sgmii mode.\n"); 267 tsec_info[num].flags |= TSEC_SGMII; 268 } 269 num++; 270 #endif 271 #ifdef CONFIG_TSEC3 272 SET_STD_TSEC_INFO(tsec_info[num], 3); 273 tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID; 274 num++; 275 #endif 276 if (!num) { 277 printf("No TSECs initialized\n"); 278 return 0; 279 } 280 281 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; 282 mdio_info.name = DEFAULT_MII_NAME; 283 fsl_pq_mdio_init(bis, &mdio_info); 284 285 tsec_eth_init(bis, tsec_info, num); 286 #endif 287 288 return pci_eth_init(bis); 289 } 290 291 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 292 static void convert_serdes_mux(int type, int need_reset) 293 { 294 char current_serdes; 295 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); 296 297 current_serdes = cpld_data->serdes_mux; 298 299 switch (type) { 300 case LANEB_SATA: 301 current_serdes &= ~MASK_LANE_B; 302 break; 303 case LANEB_SGMII1: 304 current_serdes |= (MASK_LANE_B | MASK_SGMII | MASK_LANE_C); 305 break; 306 case LANEC_SGMII1: 307 current_serdes &= ~(MASK_LANE_B | MASK_SGMII | MASK_LANE_C); 308 break; 309 case LANED_SGMII2: 310 current_serdes |= MASK_LANE_D; 311 break; 312 case LANEC_PCIEX1: 313 current_serdes |= MASK_LANE_C; 314 break; 315 case (LANED_PCIEX2 | LANEC_PCIEX1): 316 current_serdes |= MASK_LANE_C; 317 current_serdes &= ~MASK_LANE_D; 318 break; 319 default: 320 printf("CPLD serdes MUX: unsupported MUX type 0x%x\n", type); 321 return; 322 } 323 324 cpld_data->soft_mux_on |= CPLD_SET_MUX_SERDES; 325 cpld_data->serdes_mux = current_serdes; 326 327 if (need_reset == 1) { 328 printf("Reset board to enable configuration\n"); 329 cpld_data->system_rst = CONFIG_RESET; 330 } 331 } 332 333 int config_serdes_mux(void) 334 { 335 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 336 u32 protocol = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK; 337 338 protocol >>= RCWSR4_SRDS1_PRTCL_SHIFT; 339 switch (protocol) { 340 case 0x10: 341 convert_serdes_mux(LANEB_SATA, KEEP_STATUS); 342 convert_serdes_mux(LANED_PCIEX2 | 343 LANEC_PCIEX1, KEEP_STATUS); 344 break; 345 case 0x20: 346 convert_serdes_mux(LANEB_SGMII1, KEEP_STATUS); 347 convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS); 348 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS); 349 break; 350 case 0x30: 351 convert_serdes_mux(LANEB_SATA, KEEP_STATUS); 352 convert_serdes_mux(LANEC_SGMII1, KEEP_STATUS); 353 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS); 354 break; 355 case 0x70: 356 convert_serdes_mux(LANEB_SATA, KEEP_STATUS); 357 convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS); 358 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS); 359 break; 360 } 361 362 return 0; 363 } 364 #endif 365 366 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 367 int config_board_mux(void) 368 { 369 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); 370 int conflict_flag; 371 372 conflict_flag = 0; 373 if (hwconfig("i2c3")) { 374 conflict_flag++; 375 cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC; 376 cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_I2C3; 377 } 378 379 if (hwconfig("ifc")) { 380 conflict_flag++; 381 /* some signals can not enable simultaneous*/ 382 if (conflict_flag > 1) 383 goto conflict; 384 cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC; 385 cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_IFC; 386 } 387 388 conflict_flag = 0; 389 if (hwconfig("usb2")) { 390 conflict_flag++; 391 cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2; 392 cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_USB2; 393 } 394 395 if (hwconfig("can3")) { 396 conflict_flag++; 397 /* some signals can not enable simultaneous*/ 398 if (conflict_flag > 1) 399 goto conflict; 400 cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2; 401 cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_CAN3; 402 } 403 404 conflict_flag = 0; 405 if (hwconfig("lcd")) { 406 conflict_flag++; 407 cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD; 408 cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_LCD; 409 } 410 411 if (hwconfig("qe")) { 412 conflict_flag++; 413 /* some signals can not enable simultaneous*/ 414 if (conflict_flag > 1) 415 goto conflict; 416 cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD; 417 cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_QE; 418 } 419 420 return 0; 421 422 conflict: 423 printf("WARNING: pin conflict! MUX setting may failed!\n"); 424 return 0; 425 } 426 #endif 427 428 int board_early_init_f(void) 429 { 430 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 431 432 #ifdef CONFIG_TSEC_ENET 433 /* clear BD & FR bits for BE BD's and frame data */ 434 clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); 435 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125); 436 #endif 437 438 #ifdef CONFIG_FSL_IFC 439 init_early_memctl_regs(); 440 #endif 441 442 arch_soc_init(); 443 444 #if defined(CONFIG_DEEP_SLEEP) 445 if (is_warm_boot()) { 446 timer_init(); 447 dram_init(); 448 } 449 #endif 450 451 return 0; 452 } 453 454 #ifdef CONFIG_SPL_BUILD 455 void board_init_f(ulong dummy) 456 { 457 void (*second_uboot)(void); 458 459 /* Clear the BSS */ 460 memset(__bss_start, 0, __bss_end - __bss_start); 461 462 get_clocks(); 463 464 #if defined(CONFIG_DEEP_SLEEP) 465 if (is_warm_boot()) 466 fsl_dp_disable_console(); 467 #endif 468 469 preloader_console_init(); 470 471 dram_init(); 472 473 /* Allow OCRAM access permission as R/W */ 474 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS 475 enable_layerscape_ns_access(); 476 #endif 477 478 /* 479 * if it is woken up from deep sleep, then jump to second 480 * stage uboot and continue executing without recopying 481 * it from SD since it has already been reserved in memeory 482 * in last boot. 483 */ 484 if (is_warm_boot()) { 485 second_uboot = (void (*)(void))CONFIG_SYS_TEXT_BASE; 486 second_uboot(); 487 } 488 489 board_init_r(NULL, 0); 490 } 491 #endif 492 493 #ifdef CONFIG_DEEP_SLEEP 494 /* program the regulator (MC34VR500) to support deep sleep */ 495 void ls1twr_program_regulator(void) 496 { 497 unsigned int i2c_bus; 498 u8 i2c_device_id; 499 500 #define LS1TWR_I2C_BUS_MC34VR500 1 501 #define MC34VR500_ADDR 0x8 502 #define MC34VR500_DEVICEID 0x4 503 #define MC34VR500_DEVICEID_MASK 0x0f 504 505 i2c_bus = i2c_get_bus_num(); 506 i2c_set_bus_num(LS1TWR_I2C_BUS_MC34VR500); 507 i2c_device_id = i2c_reg_read(MC34VR500_ADDR, 0x0) & 508 MC34VR500_DEVICEID_MASK; 509 if (i2c_device_id != MC34VR500_DEVICEID) { 510 printf("The regulator (MC34VR500) does not exist. The device does not support deep sleep.\n"); 511 return; 512 } 513 514 i2c_reg_write(MC34VR500_ADDR, 0x31, 0x4); 515 i2c_reg_write(MC34VR500_ADDR, 0x4d, 0x4); 516 i2c_reg_write(MC34VR500_ADDR, 0x6d, 0x38); 517 i2c_reg_write(MC34VR500_ADDR, 0x6f, 0x37); 518 i2c_reg_write(MC34VR500_ADDR, 0x71, 0x30); 519 520 i2c_set_bus_num(i2c_bus); 521 } 522 #endif 523 524 int board_init(void) 525 { 526 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315 527 erratum_a010315(); 528 #endif 529 530 #ifndef CONFIG_SYS_FSL_NO_SERDES 531 fsl_serdes_init(); 532 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 533 config_serdes_mux(); 534 #endif 535 #endif 536 537 ls102xa_smmu_stream_id_init(); 538 539 #ifdef CONFIG_U_QE 540 u_qe_init(); 541 #endif 542 543 #ifdef CONFIG_DEEP_SLEEP 544 ls1twr_program_regulator(); 545 #endif 546 return 0; 547 } 548 549 #if defined(CONFIG_SPL_BUILD) 550 void spl_board_init(void) 551 { 552 ls102xa_smmu_stream_id_init(); 553 } 554 #endif 555 556 #ifdef CONFIG_BOARD_LATE_INIT 557 int board_late_init(void) 558 { 559 #ifdef CONFIG_SCSI_AHCI_PLAT 560 ls1021a_sata_init(); 561 #endif 562 #ifdef CONFIG_CHAIN_OF_TRUST 563 fsl_setenv_chain_of_trust(); 564 #endif 565 566 return 0; 567 } 568 #endif 569 570 #if defined(CONFIG_MISC_INIT_R) 571 int misc_init_r(void) 572 { 573 #ifdef CONFIG_FSL_DEVICE_DISABLE 574 device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl)); 575 #endif 576 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 577 config_board_mux(); 578 #endif 579 580 #ifdef CONFIG_FSL_CAAM 581 return sec_init(); 582 #endif 583 } 584 #endif 585 586 #if defined(CONFIG_DEEP_SLEEP) 587 void board_sleep_prepare(void) 588 { 589 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS 590 enable_layerscape_ns_access(); 591 #endif 592 } 593 #endif 594 595 int ft_board_setup(void *blob, bd_t *bd) 596 { 597 ft_cpu_setup(blob, bd); 598 599 #ifdef CONFIG_PCI 600 ft_pci_setup(blob, bd); 601 #endif 602 603 return 0; 604 } 605 606 u8 flash_read8(void *addr) 607 { 608 return __raw_readb(addr + 1); 609 } 610 611 void flash_write16(u16 val, void *addr) 612 { 613 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); 614 615 __raw_writew(shftval, addr); 616 } 617 618 u16 flash_read16(void *addr) 619 { 620 u16 val = __raw_readw(addr); 621 622 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); 623 } 624 625 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) \ 626 && !defined(CONFIG_SPL_BUILD) 627 static void convert_flash_bank(char bank) 628 { 629 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); 630 631 printf("Now switch to boot from flash bank %d.\n", bank); 632 cpld_data->soft_mux_on = CPLD_SET_BOOT_BANK; 633 cpld_data->vbank = bank; 634 635 printf("Reset board to enable configuration.\n"); 636 cpld_data->system_rst = CONFIG_RESET; 637 } 638 639 static int flash_bank_cmd(cmd_tbl_t *cmdtp, int flag, int argc, 640 char * const argv[]) 641 { 642 if (argc != 2) 643 return CMD_RET_USAGE; 644 if (strcmp(argv[1], "0") == 0) 645 convert_flash_bank(BOOT_FROM_UPPER_BANK); 646 else if (strcmp(argv[1], "1") == 0) 647 convert_flash_bank(BOOT_FROM_LOWER_BANK); 648 else 649 return CMD_RET_USAGE; 650 651 return 0; 652 } 653 654 U_BOOT_CMD( 655 boot_bank, 2, 0, flash_bank_cmd, 656 "Flash bank Selection Control", 657 "bank[0-upper bank/1-lower bank] (e.g. boot_bank 0)" 658 ); 659 660 static int cpld_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, 661 char * const argv[]) 662 { 663 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); 664 665 if (argc > 2) 666 return CMD_RET_USAGE; 667 if ((argc == 1) || (strcmp(argv[1], "conf") == 0)) 668 cpld_data->system_rst = CONFIG_RESET; 669 else if (strcmp(argv[1], "init") == 0) 670 cpld_data->global_rst = INIT_RESET; 671 else 672 return CMD_RET_USAGE; 673 674 return 0; 675 } 676 677 U_BOOT_CMD( 678 cpld_reset, 2, 0, cpld_reset_cmd, 679 "Reset via CPLD", 680 "conf\n" 681 " -reset with current CPLD configuration\n" 682 "init\n" 683 " -reset and initial CPLD configuration with default value" 684 685 ); 686 687 static void print_serdes_mux(void) 688 { 689 char current_serdes; 690 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); 691 692 current_serdes = cpld_data->serdes_mux; 693 694 printf("Serdes Lane B: "); 695 if ((current_serdes & MASK_LANE_B) == 0) 696 printf("SATA,\n"); 697 else 698 printf("SGMII 1,\n"); 699 700 printf("Serdes Lane C: "); 701 if ((current_serdes & MASK_LANE_C) == 0) 702 printf("SGMII 1,\n"); 703 else 704 printf("PCIe,\n"); 705 706 printf("Serdes Lane D: "); 707 if ((current_serdes & MASK_LANE_D) == 0) 708 printf("PCIe,\n"); 709 else 710 printf("SGMII 2,\n"); 711 712 printf("SGMII 1 is on lane "); 713 if ((current_serdes & MASK_SGMII) == 0) 714 printf("C.\n"); 715 else 716 printf("B.\n"); 717 } 718 719 static int serdes_mux_cmd(cmd_tbl_t *cmdtp, int flag, int argc, 720 char * const argv[]) 721 { 722 if (argc != 2) 723 return CMD_RET_USAGE; 724 if (strcmp(argv[1], "sata") == 0) { 725 printf("Set serdes lane B to SATA.\n"); 726 convert_serdes_mux(LANEB_SATA, NEED_RESET); 727 } else if (strcmp(argv[1], "sgmii1b") == 0) { 728 printf("Set serdes lane B to SGMII 1.\n"); 729 convert_serdes_mux(LANEB_SGMII1, NEED_RESET); 730 } else if (strcmp(argv[1], "sgmii1c") == 0) { 731 printf("Set serdes lane C to SGMII 1.\n"); 732 convert_serdes_mux(LANEC_SGMII1, NEED_RESET); 733 } else if (strcmp(argv[1], "sgmii2") == 0) { 734 printf("Set serdes lane D to SGMII 2.\n"); 735 convert_serdes_mux(LANED_SGMII2, NEED_RESET); 736 } else if (strcmp(argv[1], "pciex1") == 0) { 737 printf("Set serdes lane C to PCIe X1.\n"); 738 convert_serdes_mux(LANEC_PCIEX1, NEED_RESET); 739 } else if (strcmp(argv[1], "pciex2") == 0) { 740 printf("Set serdes lane C & lane D to PCIe X2.\n"); 741 convert_serdes_mux((LANED_PCIEX2 | LANEC_PCIEX1), NEED_RESET); 742 } else if (strcmp(argv[1], "show") == 0) { 743 print_serdes_mux(); 744 } else { 745 return CMD_RET_USAGE; 746 } 747 748 return 0; 749 } 750 751 U_BOOT_CMD( 752 lane_bank, 2, 0, serdes_mux_cmd, 753 "Multiplexed function setting for SerDes Lanes", 754 "sata\n" 755 " -change lane B to sata\n" 756 "lane_bank sgmii1b\n" 757 " -change lane B to SGMII1\n" 758 "lane_bank sgmii1c\n" 759 " -change lane C to SGMII1\n" 760 "lane_bank sgmii2\n" 761 " -change lane D to SGMII2\n" 762 "lane_bank pciex1\n" 763 " -change lane C to PCIeX1\n" 764 "lane_bank pciex2\n" 765 " -change lane C & lane D to PCIeX2\n" 766 "\nWARNING: If you aren't familiar with the setting of serdes, don't try to change anything!\n" 767 ); 768 #endif 769
