1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2007 Sergey Kubushyn <ksi (at) koi8.net> 4 * 5 * Based on: 6 * 7 * ------------------------------------------------------------------------- 8 * 9 * linux/include/asm-arm/arch-davinci/hardware.h 10 * 11 * Copyright (C) 2006 Texas Instruments. 12 */ 13 #ifndef __ASM_ARCH_HARDWARE_H 14 #define __ASM_ARCH_HARDWARE_H 15 16 #include <linux/sizes.h> 17 18 #define REG(addr) (*(volatile unsigned int *)(addr)) 19 #define REG_P(addr) ((volatile unsigned int *)(addr)) 20 21 #ifndef __ASSEMBLY__ 22 typedef volatile unsigned int dv_reg; 23 typedef volatile unsigned int * dv_reg_p; 24 #endif 25 26 /* 27 * Base register addresses 28 * 29 * NOTE: some of these DM6446-specific addresses DO NOT WORK 30 * on other DaVinci chips. Double check them before you try 31 * using the addresses ... or PSC module identifiers, etc. 32 */ 33 #ifndef CONFIG_SOC_DA8XX 34 35 #define DAVINCI_DMA_3PCC_BASE (0x01c00000) 36 #define DAVINCI_DMA_3PTC0_BASE (0x01c10000) 37 #define DAVINCI_DMA_3PTC1_BASE (0x01c10400) 38 #define DAVINCI_UART0_BASE (0x01c20000) 39 #define DAVINCI_UART1_BASE (0x01c20400) 40 #define DAVINCI_TIMER3_BASE (0x01c20800) 41 #define DAVINCI_I2C_BASE (0x01c21000) 42 #define DAVINCI_TIMER0_BASE (0x01c21400) 43 #define DAVINCI_TIMER1_BASE (0x01c21800) 44 #define DAVINCI_WDOG_BASE (0x01c21c00) 45 #define DAVINCI_PWM0_BASE (0x01c22000) 46 #define DAVINCI_PWM1_BASE (0x01c22400) 47 #define DAVINCI_PWM2_BASE (0x01c22800) 48 #define DAVINCI_TIMER4_BASE (0x01c23800) 49 #define DAVINCI_SYSTEM_MODULE_BASE (0x01c40000) 50 #define DAVINCI_PLL_CNTRL0_BASE (0x01c40800) 51 #define DAVINCI_PLL_CNTRL1_BASE (0x01c40c00) 52 #define DAVINCI_PWR_SLEEP_CNTRL_BASE (0x01c41000) 53 #define DAVINCI_ARM_INTC_BASE (0x01c48000) 54 #define DAVINCI_USB_OTG_BASE (0x01c64000) 55 #define DAVINCI_CFC_ATA_BASE (0x01c66000) 56 #define DAVINCI_SPI_BASE (0x01c66800) 57 #define DAVINCI_GPIO_BASE (0x01c67000) 58 #define DAVINCI_VPSS_REGS_BASE (0x01c70000) 59 #if !defined(CONFIG_SOC_DM646X) 60 #define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE (0x02000000) 61 #define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE (0x04000000) 62 #define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE (0x06000000) 63 #define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x08000000) 64 #endif 65 #define DAVINCI_DDR_BASE (0x80000000) 66 67 #ifdef CONFIG_SOC_DM644X 68 #define DAVINCI_UART2_BASE 0x01c20800 69 #define DAVINCI_UHPI_BASE 0x01c67800 70 #define DAVINCI_EMAC_CNTRL_REGS_BASE 0x01c80000 71 #define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE 0x01c81000 72 #define DAVINCI_EMAC_WRAPPER_RAM_BASE 0x01c82000 73 #define DAVINCI_MDIO_CNTRL_REGS_BASE 0x01c84000 74 #define DAVINCI_IMCOP_BASE 0x01cc0000 75 #define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01e00000 76 #define DAVINCI_VLYNQ_BASE 0x01e01000 77 #define DAVINCI_ASP_BASE 0x01e02000 78 #define DAVINCI_MMC_SD_BASE 0x01e10000 79 #define DAVINCI_MS_BASE 0x01e20000 80 #define DAVINCI_VLYNQ_REMOTE_BASE 0x0c000000 81 82 #elif defined(CONFIG_SOC_DM355) 83 #define DAVINCI_MMC_SD1_BASE 0x01e00000 84 #define DAVINCI_ASP0_BASE 0x01e02000 85 #define DAVINCI_ASP1_BASE 0x01e04000 86 #define DAVINCI_UART2_BASE 0x01e06000 87 #define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01e10000 88 #define DAVINCI_MMC_SD0_BASE 0x01e11000 89 90 #elif defined(CONFIG_SOC_DM365) 91 #define DAVINCI_MMC_SD1_BASE 0x01d00000 92 #define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01d10000 93 #define DAVINCI_MMC_SD0_BASE 0x01d11000 94 #define DAVINCI_DDR_EMIF_CTRL_BASE 0x20000000 95 #define DAVINCI_SPI0_BASE 0x01c66000 96 #define DAVINCI_SPI1_BASE 0x01c66800 97 98 #elif defined(CONFIG_SOC_DM646X) 99 #define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x20008000 100 #define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x42000000 101 #define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE 0x44000000 102 #define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x46000000 103 #define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 0x48000000 104 105 #endif 106 107 #else /* CONFIG_SOC_DA8XX */ 108 109 #define DAVINCI_UART0_BASE 0x01c42000 110 #define DAVINCI_UART1_BASE 0x01d0c000 111 #define DAVINCI_UART2_BASE 0x01d0d000 112 #define DAVINCI_I2C0_BASE 0x01c22000 113 #define DAVINCI_I2C1_BASE 0x01e28000 114 #define DAVINCI_TIMER0_BASE 0x01c20000 115 #define DAVINCI_TIMER1_BASE 0x01c21000 116 #define DAVINCI_WDOG_BASE 0x01c21000 117 #define DAVINCI_RTC_BASE 0x01c23000 118 #define DAVINCI_PLL_CNTRL0_BASE 0x01c11000 119 #define DAVINCI_PLL_CNTRL1_BASE 0x01e1a000 120 #define DAVINCI_PSC0_BASE 0x01c10000 121 #define DAVINCI_PSC1_BASE 0x01e27000 122 #define DAVINCI_SPI0_BASE 0x01c41000 123 #define DAVINCI_USB_OTG_BASE 0x01e00000 124 #define DAVINCI_SPI1_BASE (cpu_is_da830() ? \ 125 0x01e12000 : 0x01f0e000) 126 #define DAVINCI_GPIO_BASE 0x01e26000 127 #define DAVINCI_EMAC_CNTRL_REGS_BASE 0x01e23000 128 #define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE 0x01e22000 129 #define DAVINCI_EMAC_WRAPPER_RAM_BASE 0x01e20000 130 #define DAVINCI_MDIO_CNTRL_REGS_BASE 0x01e24000 131 #define DAVINCI_SYSCFG1_BASE 0x01e2c000 132 #define DAVINCI_MMC_SD0_BASE 0x01c40000 133 #define DAVINCI_MMC_SD1_BASE 0x01e1b000 134 #define DAVINCI_TIMER2_BASE 0x01f0c000 135 #define DAVINCI_TIMER3_BASE 0x01f0d000 136 #define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x68000000 137 #define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x40000000 138 #define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x60000000 139 #define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 0x62000000 140 #define DAVINCI_ASYNC_EMIF_DATA_CE4_BASE 0x64000000 141 #define DAVINCI_ASYNC_EMIF_DATA_CE5_BASE 0x66000000 142 #define DAVINCI_DDR_EMIF_CTRL_BASE 0xb0000000 143 #define DAVINCI_DDR_EMIF_DATA_BASE 0xc0000000 144 #define DAVINCI_INTC_BASE 0xfffee000 145 #define DAVINCI_BOOTCFG_BASE 0x01c14000 146 #define DAVINCI_LCD_CNTL_BASE 0x01e13000 147 #define DAVINCI_L3CBARAM_BASE 0x80000000 148 #define JTAG_ID_REG (DAVINCI_BOOTCFG_BASE + 0x18) 149 #define CHIP_REV_ID_REG (DAVINCI_BOOTCFG_BASE + 0x24) 150 #define HOST1CFG (DAVINCI_BOOTCFG_BASE + 0x44) 151 #define PSC0_MDCTL (DAVINCI_PSC0_BASE + 0xa00) 152 153 #define GPIO_BANK0_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x10) 154 #define GPIO_BANK0_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x14) 155 #define GPIO_BANK0_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x18) 156 #define GPIO_BANK0_REG_CLR_ADDR (DAVINCI_GPIO_BASE + 0x1c) 157 #define GPIO_BANK2_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x38) 158 #define GPIO_BANK2_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x3c) 159 #define GPIO_BANK2_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x40) 160 #define GPIO_BANK2_REG_CLR_ADDR (DAVINCI_GPIO_BASE + 0x44) 161 #define GPIO_BANK6_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x88) 162 #define GPIO_BANK6_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x8c) 163 #define GPIO_BANK6_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x90) 164 #define GPIO_BANK6_REG_CLR_ADDR (DAVINCI_GPIO_BASE + 0x94) 165 #endif /* CONFIG_SOC_DA8XX */ 166 167 /* Power and Sleep Controller (PSC) Domains */ 168 #define DAVINCI_GPSC_ARMDOMAIN 0 169 #define DAVINCI_GPSC_DSPDOMAIN 1 170 171 #ifndef CONFIG_SOC_DA8XX 172 173 #define DAVINCI_LPSC_VPSSMSTR 0 174 #define DAVINCI_LPSC_VPSSSLV 1 175 #define DAVINCI_LPSC_TPCC 2 176 #define DAVINCI_LPSC_TPTC0 3 177 #define DAVINCI_LPSC_TPTC1 4 178 #define DAVINCI_LPSC_EMAC 5 179 #define DAVINCI_LPSC_EMAC_WRAPPER 6 180 #define DAVINCI_LPSC_MDIO 7 181 #define DAVINCI_LPSC_IEEE1394 8 182 #define DAVINCI_LPSC_USB 9 183 #define DAVINCI_LPSC_ATA 10 184 #define DAVINCI_LPSC_VLYNQ 11 185 #define DAVINCI_LPSC_UHPI 12 186 #define DAVINCI_LPSC_DDR_EMIF 13 187 #define DAVINCI_LPSC_AEMIF 14 188 #define DAVINCI_LPSC_MMC_SD 15 189 #define DAVINCI_LPSC_MEMSTICK 16 190 #define DAVINCI_LPSC_McBSP 17 191 #define DAVINCI_LPSC_I2C 18 192 #define DAVINCI_LPSC_UART0 19 193 #define DAVINCI_LPSC_UART1 20 194 #define DAVINCI_LPSC_UART2 21 195 #define DAVINCI_LPSC_SPI 22 196 #define DAVINCI_LPSC_PWM0 23 197 #define DAVINCI_LPSC_PWM1 24 198 #define DAVINCI_LPSC_PWM2 25 199 #define DAVINCI_LPSC_GPIO 26 200 #define DAVINCI_LPSC_TIMER0 27 201 #define DAVINCI_LPSC_TIMER1 28 202 #define DAVINCI_LPSC_TIMER2 29 203 #define DAVINCI_LPSC_SYSTEM_SUBSYS 30 204 #define DAVINCI_LPSC_ARM 31 205 #define DAVINCI_LPSC_SCR2 32 206 #define DAVINCI_LPSC_SCR3 33 207 #define DAVINCI_LPSC_SCR4 34 208 #define DAVINCI_LPSC_CROSSBAR 35 209 #define DAVINCI_LPSC_CFG27 36 210 #define DAVINCI_LPSC_CFG3 37 211 #define DAVINCI_LPSC_CFG5 38 212 #define DAVINCI_LPSC_GEM 39 213 #define DAVINCI_LPSC_IMCOP 40 214 #define DAVINCI_LPSC_VPSSMASTER 47 215 #define DAVINCI_LPSC_MJCP 50 216 #define DAVINCI_LPSC_HDVICP 51 217 218 #define DAVINCI_DM646X_LPSC_EMAC 14 219 #define DAVINCI_DM646X_LPSC_UART0 26 220 #define DAVINCI_DM646X_LPSC_I2C 31 221 #define DAVINCI_DM646X_LPSC_TIMER0 34 222 223 #else /* CONFIG_SOC_DA8XX */ 224 225 #define DAVINCI_LPSC_TPCC 0 226 #define DAVINCI_LPSC_TPTC0 1 227 #define DAVINCI_LPSC_TPTC1 2 228 #define DAVINCI_LPSC_AEMIF 3 229 #define DAVINCI_LPSC_SPI0 4 230 #define DAVINCI_LPSC_MMC_SD 5 231 #define DAVINCI_LPSC_AINTC 6 232 #define DAVINCI_LPSC_ARM_RAM_ROM 7 233 #define DAVINCI_LPSC_SECCTL_KEYMGR 8 234 #define DAVINCI_LPSC_UART0 9 235 #define DAVINCI_LPSC_SCR0 10 236 #define DAVINCI_LPSC_SCR1 11 237 #define DAVINCI_LPSC_SCR2 12 238 #define DAVINCI_LPSC_DMAX 13 239 #define DAVINCI_LPSC_ARM 14 240 #define DAVINCI_LPSC_GEM 15 241 242 /* for LPSCs in PSC1, offset from 32 for differentiation */ 243 #define DAVINCI_LPSC_PSC1_BASE 32 244 #define DAVINCI_LPSC_USB20 (DAVINCI_LPSC_PSC1_BASE + 1) 245 #define DAVINCI_LPSC_USB11 (DAVINCI_LPSC_PSC1_BASE + 2) 246 #define DAVINCI_LPSC_GPIO (DAVINCI_LPSC_PSC1_BASE + 3) 247 #define DAVINCI_LPSC_UHPI (DAVINCI_LPSC_PSC1_BASE + 4) 248 #define DAVINCI_LPSC_EMAC (DAVINCI_LPSC_PSC1_BASE + 5) 249 #define DAVINCI_LPSC_DDR_EMIF (DAVINCI_LPSC_PSC1_BASE + 6) 250 #define DAVINCI_LPSC_McASP0 (DAVINCI_LPSC_PSC1_BASE + 7) 251 #define DAVINCI_LPSC_SPI1 (DAVINCI_LPSC_PSC1_BASE + 10) 252 #define DAVINCI_LPSC_I2C1 (DAVINCI_LPSC_PSC1_BASE + 11) 253 #define DAVINCI_LPSC_UART1 (DAVINCI_LPSC_PSC1_BASE + 12) 254 #define DAVINCI_LPSC_UART2 (DAVINCI_LPSC_PSC1_BASE + 13) 255 #define DAVINCI_LPSC_LCDC (DAVINCI_LPSC_PSC1_BASE + 16) 256 #define DAVINCI_LPSC_ePWM (DAVINCI_LPSC_PSC1_BASE + 17) 257 #define DAVINCI_LPSC_MMCSD1 (DAVINCI_LPSC_PSC1_BASE + 18) 258 #define DAVINCI_LPSC_eCAP (DAVINCI_LPSC_PSC1_BASE + 20) 259 #define DAVINCI_LPSC_L3_CBA_RAM (DAVINCI_LPSC_PSC1_BASE + 31) 260 261 /* DA830-specific peripherals */ 262 #define DAVINCI_LPSC_McASP1 (DAVINCI_LPSC_PSC1_BASE + 8) 263 #define DAVINCI_LPSC_McASP2 (DAVINCI_LPSC_PSC1_BASE + 9) 264 #define DAVINCI_LPSC_eQEP (DAVINCI_LPSC_PSC1_BASE + 21) 265 #define DAVINCI_LPSC_SCR8 (DAVINCI_LPSC_PSC1_BASE + 24) 266 #define DAVINCI_LPSC_SCR7 (DAVINCI_LPSC_PSC1_BASE + 25) 267 #define DAVINCI_LPSC_SCR12 (DAVINCI_LPSC_PSC1_BASE + 26) 268 269 /* DA850-specific peripherals */ 270 #define DAVINCI_LPSC_TPCC1 (DAVINCI_LPSC_PSC1_BASE + 0) 271 #define DAVINCI_LPSC_SATA (DAVINCI_LPSC_PSC1_BASE + 8) 272 #define DAVINCI_LPSC_VPIF (DAVINCI_LPSC_PSC1_BASE + 9) 273 #define DAVINCI_LPSC_McBSP0 (DAVINCI_LPSC_PSC1_BASE + 14) 274 #define DAVINCI_LPSC_McBSP1 (DAVINCI_LPSC_PSC1_BASE + 15) 275 #define DAVINCI_LPSC_MMC_SD1 (DAVINCI_LPSC_PSC1_BASE + 18) 276 #define DAVINCI_LPSC_uPP (DAVINCI_LPSC_PSC1_BASE + 19) 277 #define DAVINCI_LPSC_TPTC2 (DAVINCI_LPSC_PSC1_BASE + 21) 278 #define DAVINCI_LPSC_SCR_F0 (DAVINCI_LPSC_PSC1_BASE + 24) 279 #define DAVINCI_LPSC_SCR_F1 (DAVINCI_LPSC_PSC1_BASE + 25) 280 #define DAVINCI_LPSC_SCR_F2 (DAVINCI_LPSC_PSC1_BASE + 26) 281 #define DAVINCI_LPSC_SCR_F6 (DAVINCI_LPSC_PSC1_BASE + 27) 282 #define DAVINCI_LPSC_SCR_F7 (DAVINCI_LPSC_PSC1_BASE + 28) 283 #define DAVINCI_LPSC_SCR_F8 (DAVINCI_LPSC_PSC1_BASE + 29) 284 #define DAVINCI_LPSC_BR_F7 (DAVINCI_LPSC_PSC1_BASE + 30) 285 286 #endif /* CONFIG_SOC_DA8XX */ 287 288 #ifndef __ASSEMBLY__ 289 void lpsc_on(unsigned int id); 290 void lpsc_syncreset(unsigned int id); 291 void lpsc_disable(unsigned int id); 292 void dsp_on(void); 293 294 void davinci_enable_uart0(void); 295 void davinci_enable_emac(void); 296 void davinci_enable_i2c(void); 297 void davinci_errata_workarounds(void); 298 299 #ifndef CONFIG_SOC_DA8XX 300 301 /* Some PSC defines */ 302 #define PSC_CHP_SHRTSW (0x01c40038) 303 #define PSC_GBLCTL (0x01c41010) 304 #define PSC_EPCPR (0x01c41070) 305 #define PSC_EPCCR (0x01c41078) 306 #define PSC_PTCMD (0x01c41120) 307 #define PSC_PTSTAT (0x01c41128) 308 #define PSC_PDSTAT (0x01c41200) 309 #define PSC_PDSTAT1 (0x01c41204) 310 #define PSC_PDCTL (0x01c41300) 311 #define PSC_PDCTL1 (0x01c41304) 312 313 #define PSC_MDCTL_BASE (0x01c41a00) 314 #define PSC_MDSTAT_BASE (0x01c41800) 315 316 #define VDD3P3V_PWDN (0x01c40048) 317 #define UART0_PWREMU_MGMT (0x01c20030) 318 319 #define PSC_SILVER_BULLET (0x01c41a20) 320 321 #else /* CONFIG_SOC_DA8XX */ 322 323 #define PSC_ENABLE 0x3 324 #define PSC_DISABLE 0x2 325 #define PSC_SYNCRESET 0x1 326 #define PSC_SWRSTDISABLE 0x0 327 328 #define PSC_PSC0_MODULE_ID_CNT 16 329 #define PSC_PSC1_MODULE_ID_CNT 32 330 331 #define UART0_PWREMU_MGMT (0x01c42030) 332 333 struct davinci_psc_regs { 334 dv_reg revid; 335 dv_reg rsvd0[71]; 336 dv_reg ptcmd; 337 dv_reg rsvd1; 338 dv_reg ptstat; 339 dv_reg rsvd2[437]; 340 union { 341 struct { 342 dv_reg mdstat[PSC_PSC0_MODULE_ID_CNT]; 343 dv_reg rsvd3[112]; 344 dv_reg mdctl[PSC_PSC0_MODULE_ID_CNT]; 345 } psc0; 346 struct { 347 dv_reg mdstat[PSC_PSC1_MODULE_ID_CNT]; 348 dv_reg rsvd3[96]; 349 dv_reg mdctl[PSC_PSC1_MODULE_ID_CNT]; 350 } psc1; 351 }; 352 }; 353 354 #define davinci_psc0_regs ((struct davinci_psc_regs *)DAVINCI_PSC0_BASE) 355 #define davinci_psc1_regs ((struct davinci_psc_regs *)DAVINCI_PSC1_BASE) 356 357 #endif /* CONFIG_SOC_DA8XX */ 358 359 #define PSC_MDSTAT_STATE 0x3f 360 #define PSC_MDCTL_NEXT 0x07 361 362 #ifndef CONFIG_SOC_DA8XX 363 364 /* Miscellania... */ 365 #define VBPR (0x20000020) 366 367 /* NOTE: system control modules are *highly* chip-specific, both 368 * as to register content (e.g. for muxing) and which registers exist. 369 */ 370 #define PINMUX0 0x01c40000 371 #define PINMUX1 0x01c40004 372 #define PINMUX2 0x01c40008 373 #define PINMUX3 0x01c4000c 374 #define PINMUX4 0x01c40010 375 376 struct davinci_uart_ctrl_regs { 377 dv_reg revid1; 378 dv_reg res; 379 dv_reg pwremu_mgmt; 380 dv_reg mdr; 381 }; 382 383 #define DAVINCI_UART_CTRL_BASE 0x28 384 385 /* UART PWREMU_MGMT definitions */ 386 #define DAVINCI_UART_PWREMU_MGMT_FREE (1 << 0) 387 #define DAVINCI_UART_PWREMU_MGMT_URRST (1 << 13) 388 #define DAVINCI_UART_PWREMU_MGMT_UTRST (1 << 14) 389 390 #else /* CONFIG_SOC_DA8XX */ 391 392 struct davinci_pllc_regs { 393 dv_reg revid; 394 dv_reg rsvd1[56]; 395 dv_reg rstype; 396 dv_reg rsvd2[6]; 397 dv_reg pllctl; 398 dv_reg ocsel; 399 dv_reg rsvd3[2]; 400 dv_reg pllm; 401 dv_reg prediv; 402 dv_reg plldiv1; 403 dv_reg plldiv2; 404 dv_reg plldiv3; 405 dv_reg oscdiv; 406 dv_reg postdiv; 407 dv_reg rsvd4[3]; 408 dv_reg pllcmd; 409 dv_reg pllstat; 410 dv_reg alnctl; 411 dv_reg dchange; 412 dv_reg cken; 413 dv_reg ckstat; 414 dv_reg systat; 415 dv_reg rsvd5[3]; 416 dv_reg plldiv4; 417 dv_reg plldiv5; 418 dv_reg plldiv6; 419 dv_reg plldiv7; 420 dv_reg rsvd6[32]; 421 dv_reg emucnt0; 422 dv_reg emucnt1; 423 }; 424 425 #define davinci_pllc0_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL0_BASE) 426 #define davinci_pllc1_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL1_BASE) 427 #define DAVINCI_PLLC_DIV_MASK 0x1f 428 429 /* 430 * A clock ID is a 32-bit number where bit 16 represents the PLL controller 431 * (clear is PLLC0, set is PLLC1) and the low 16 bits represent the divisor, 432 * counting from 1. Clock IDs may be passed to clk_get(). 433 */ 434 435 /* flags to select PLL controller */ 436 #define DAVINCI_PLLC0_FLAG (0) 437 #define DAVINCI_PLLC1_FLAG (1 << 16) 438 439 enum davinci_clk_ids { 440 /* 441 * Clock IDs for PLL outputs. Each may be switched on/off 442 * independently, and each may map to one or more peripherals. 443 */ 444 DAVINCI_PLL0_SYSCLK2 = DAVINCI_PLLC0_FLAG | 2, 445 DAVINCI_PLL0_SYSCLK4 = DAVINCI_PLLC0_FLAG | 4, 446 DAVINCI_PLL0_SYSCLK6 = DAVINCI_PLLC0_FLAG | 6, 447 DAVINCI_PLL1_SYSCLK1 = DAVINCI_PLLC1_FLAG | 1, 448 DAVINCI_PLL1_SYSCLK2 = DAVINCI_PLLC1_FLAG | 2, 449 450 /* map peripherals to clock IDs */ 451 DAVINCI_ARM_CLKID = DAVINCI_PLL0_SYSCLK6, 452 DAVINCI_DDR_CLKID = DAVINCI_PLL1_SYSCLK1, 453 DAVINCI_MDIO_CLKID = DAVINCI_PLL0_SYSCLK4, 454 DAVINCI_MMC_CLKID = DAVINCI_PLL0_SYSCLK2, 455 DAVINCI_SPI0_CLKID = DAVINCI_PLL0_SYSCLK2, 456 DAVINCI_MMCSD_CLKID = DAVINCI_PLL0_SYSCLK2, 457 458 /* special clock ID - output of PLL multiplier */ 459 DAVINCI_PLLM_CLKID = 0x0FF, 460 461 /* special clock ID - output of PLL post divisor */ 462 DAVINCI_PLLC_CLKID = 0x100, 463 464 /* special clock ID - PLL bypass */ 465 DAVINCI_AUXCLK_CLKID = 0x101, 466 }; 467 468 #define DAVINCI_UART2_CLKID (cpu_is_da830() ? DAVINCI_PLL0_SYSCLK2 \ 469 : get_async3_src()) 470 471 #define DAVINCI_SPI1_CLKID (cpu_is_da830() ? DAVINCI_PLL0_SYSCLK2 \ 472 : get_async3_src()) 473 474 int clk_get(enum davinci_clk_ids id); 475 476 /* Boot config */ 477 struct davinci_syscfg_regs { 478 dv_reg revid; 479 dv_reg rsvd[7]; 480 dv_reg bootcfg; 481 dv_reg chiprevidr; 482 dv_reg rsvd2[4]; 483 dv_reg kick0; 484 dv_reg kick1; 485 dv_reg rsvd1[52]; 486 dv_reg mstpri[3]; 487 dv_reg rsvd3; 488 dv_reg pinmux[20]; 489 dv_reg suspsrc; 490 dv_reg chipsig; 491 dv_reg chipsig_clr; 492 dv_reg cfgchip0; 493 dv_reg cfgchip1; 494 dv_reg cfgchip2; 495 dv_reg cfgchip3; 496 dv_reg cfgchip4; 497 }; 498 499 #define davinci_syscfg_regs \ 500 ((struct davinci_syscfg_regs *)DAVINCI_BOOTCFG_BASE) 501 502 enum { 503 DAVINCI_NAND8_BOOT = 0b001110, 504 DAVINCI_NAND16_BOOT = 0b010000, 505 DAVINCI_SD_OR_MMC_BOOT = 0b011100, 506 DAVINCI_MMC_ONLY_BOOT = 0b111100, 507 DAVINCI_SPI0_FLASH_BOOT = 0b001010, 508 DAVINCI_SPI1_FLASH_BOOT = 0b001100, 509 }; 510 511 #define pinmux(x) (&davinci_syscfg_regs->pinmux[x]) 512 513 /* Emulation suspend bits */ 514 #define DAVINCI_SYSCFG_SUSPSRC_EMAC (1 << 5) 515 #define DAVINCI_SYSCFG_SUSPSRC_I2C (1 << 16) 516 #define DAVINCI_SYSCFG_SUSPSRC_SPI0 (1 << 21) 517 #define DAVINCI_SYSCFG_SUSPSRC_SPI1 (1 << 22) 518 #define DAVINCI_SYSCFG_SUSPSRC_UART0 (1 << 18) 519 #define DAVINCI_SYSCFG_SUSPSRC_UART1 (1 << 19) 520 #define DAVINCI_SYSCFG_SUSPSRC_UART2 (1 << 20) 521 #define DAVINCI_SYSCFG_SUSPSRC_TIMER0 (1 << 27) 522 523 struct davinci_syscfg1_regs { 524 dv_reg vtpio_ctl; 525 dv_reg ddr_slew; 526 dv_reg deepsleep; 527 dv_reg pupd_ena; 528 dv_reg pupd_sel; 529 dv_reg rxactive; 530 dv_reg pwrdwn; 531 }; 532 533 #define davinci_syscfg1_regs \ 534 ((struct davinci_syscfg1_regs *)DAVINCI_SYSCFG1_BASE) 535 536 #define DDR_SLEW_CMOSEN_BIT 4 537 #define DDR_SLEW_DDR_PDENA_BIT 5 538 539 #define VTP_POWERDWN (1 << 6) 540 #define VTP_LOCK (1 << 7) 541 #define VTP_CLKRZ (1 << 13) 542 #define VTP_READY (1 << 15) 543 #define VTP_IOPWRDWN (1 << 14) 544 545 #define DV_SYSCFG_KICK0_UNLOCK 0x83e70b13 546 #define DV_SYSCFG_KICK1_UNLOCK 0x95a4f1e0 547 548 /* Interrupt controller */ 549 struct davinci_aintc_regs { 550 dv_reg revid; 551 dv_reg cr; 552 dv_reg dummy0[2]; 553 dv_reg ger; 554 dv_reg dummy1[219]; 555 dv_reg ecr1; 556 dv_reg ecr2; 557 dv_reg ecr3; 558 dv_reg dummy2[1117]; 559 dv_reg hier; 560 }; 561 562 #define davinci_aintc_regs ((struct davinci_aintc_regs *)DAVINCI_INTC_BASE) 563 564 struct davinci_uart_ctrl_regs { 565 dv_reg revid1; 566 dv_reg revid2; 567 dv_reg pwremu_mgmt; 568 dv_reg mdr; 569 }; 570 571 #define DAVINCI_UART_CTRL_BASE 0x28 572 #define DAVINCI_UART0_CTRL_ADDR (DAVINCI_UART0_BASE + DAVINCI_UART_CTRL_BASE) 573 #define DAVINCI_UART1_CTRL_ADDR (DAVINCI_UART1_BASE + DAVINCI_UART_CTRL_BASE) 574 #define DAVINCI_UART2_CTRL_ADDR (DAVINCI_UART2_BASE + DAVINCI_UART_CTRL_BASE) 575 576 #define davinci_uart0_ctrl_regs \ 577 ((struct davinci_uart_ctrl_regs *)DAVINCI_UART0_CTRL_ADDR) 578 #define davinci_uart1_ctrl_regs \ 579 ((struct davinci_uart_ctrl_regs *)DAVINCI_UART1_CTRL_ADDR) 580 #define davinci_uart2_ctrl_regs \ 581 ((struct davinci_uart_ctrl_regs *)DAVINCI_UART2_CTRL_ADDR) 582 583 /* UART PWREMU_MGMT definitions */ 584 #define DAVINCI_UART_PWREMU_MGMT_FREE (1 << 0) 585 #define DAVINCI_UART_PWREMU_MGMT_URRST (1 << 13) 586 #define DAVINCI_UART_PWREMU_MGMT_UTRST (1 << 14) 587 588 static inline int cpu_is_da830(void) 589 { 590 unsigned int jtag_id = REG(JTAG_ID_REG); 591 unsigned short part_no = (jtag_id >> 12) & 0xffff; 592 593 return ((part_no == 0xb7df) ? 1 : 0); 594 } 595 static inline int cpu_is_da850(void) 596 { 597 unsigned int jtag_id = REG(JTAG_ID_REG); 598 unsigned short part_no = (jtag_id >> 12) & 0xffff; 599 600 return ((part_no == 0xb7d1) ? 1 : 0); 601 } 602 603 static inline enum davinci_clk_ids get_async3_src(void) 604 { 605 return (REG(&davinci_syscfg_regs->cfgchip3) & 0x10) ? 606 DAVINCI_PLL1_SYSCLK2 : DAVINCI_PLL0_SYSCLK2; 607 } 608 609 #endif /* CONFIG_SOC_DA8XX */ 610 611 #if defined(CONFIG_SOC_DM365) 612 #include <asm/arch/aintc_defs.h> 613 #include <asm/arch/ddr2_defs.h> 614 #include <asm/arch/gpio.h> 615 #include <asm/arch/pll_defs.h> 616 #include <asm/arch/psc_defs.h> 617 #include <asm/arch/syscfg_defs.h> 618 #include <asm/arch/timer_defs.h> 619 620 #define TMPBUF 0x00017ff8 621 #define TMPSTATUS 0x00017ff0 622 #define DV_TMPBUF_VAL 0x591b3ed7 623 #define FLAG_PORRST 0x00000001 624 #define FLAG_WDTRST 0x00000002 625 #define FLAG_FLGON 0x00000004 626 #define FLAG_FLGOFF 0x00000010 627 628 #endif 629 #endif /* !__ASSEMBLY__ */ 630 631 #endif /* __ASM_ARCH_HARDWARE_H */ 632
