/external/swiftshader/third_party/subzero/src/ |
IcePhiLoweringImpl.h | 41 auto *DestLo = llvm::cast<Variable>(Target->loOperand(Dest)); 43 auto *PhiLo = InstPhi::create(Func, Phi->getSrcSize(), DestLo);
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IceInstARM32.cpp | [all...] |
IceTargetLoweringARM32.cpp | [all...] |
IceTargetLoweringX86BaseImpl.h | [all...] |
IceTargetLoweringMIPS32.cpp | [all...] |
/external/llvm/lib/Target/Hexagon/ |
HexagonSplitConst32AndConst64.cpp | 140 unsigned DestLo = TRI->getSubReg(DestReg, Hexagon::subreg_loreg); 147 DestLo)
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
HexagonSplitConst32AndConst64.cpp | 90 unsigned DestLo = TRI->getSubReg(DestReg, Hexagon::isub_lo); 96 BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), DestLo)
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/ |
AVRInstrInfo.cpp | 56 unsigned DestLo, DestHi, SrcLo, SrcHi; 58 TRI.splitReg(DestReg, DestLo, DestHi); 62 BuildMI(MBB, MI, DL, get(AVR::MOVRdRr), DestLo)
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
AArch64ExpandPseudoInsts.cpp | 674 MachineOperand &DestLo = MI.getOperand(0); 702 .addReg(DestLo.getReg(), RegState::Define) 706 .addReg(DestLo.getReg(), getKillRegState(DestLo.isDead())) [all...] |
/external/llvm/lib/Target/ARM/ |
ARMExpandPseudoInsts.cpp | [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
ARMExpandPseudoInsts.cpp | [all...] |