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      1 //=== HexagonSplitConst32AndConst64.cpp - split CONST32/Const64 into HI/LO ===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // When the compiler is invoked with no small data, for instance, with the -G0
     11 // command line option, then all CONST* opcodes should be broken down into
     12 // appropriate LO and HI instructions. This splitting is done by this pass.
     13 // The only reason this is not done in the DAG lowering itself is that there
     14 // is no simple way of getting the register allocator to allot the same hard
     15 // register to the result of LO and HI instructions. This pass is always
     16 // scheduled after register allocation.
     17 //
     18 //===----------------------------------------------------------------------===//
     19 
     20 #include "HexagonSubtarget.h"
     21 #include "HexagonTargetMachine.h"
     22 #include "HexagonTargetObjectFile.h"
     23 #include "llvm/CodeGen/MachineFunctionPass.h"
     24 #include "llvm/CodeGen/MachineInstrBuilder.h"
     25 #include "llvm/CodeGen/Passes.h"
     26 #include "llvm/CodeGen/TargetInstrInfo.h"
     27 #include "llvm/CodeGen/TargetRegisterInfo.h"
     28 
     29 using namespace llvm;
     30 
     31 #define DEBUG_TYPE "xfer"
     32 
     33 namespace llvm {
     34   FunctionPass *createHexagonSplitConst32AndConst64();
     35   void initializeHexagonSplitConst32AndConst64Pass(PassRegistry&);
     36 }
     37 
     38 namespace {
     39   class HexagonSplitConst32AndConst64 : public MachineFunctionPass {
     40   public:
     41     static char ID;
     42     HexagonSplitConst32AndConst64() : MachineFunctionPass(ID) {
     43       PassRegistry &R = *PassRegistry::getPassRegistry();
     44       initializeHexagonSplitConst32AndConst64Pass(R);
     45     }
     46     StringRef getPassName() const override {
     47       return "Hexagon Split Const32s and Const64s";
     48     }
     49     bool runOnMachineFunction(MachineFunction &Fn) override;
     50     MachineFunctionProperties getRequiredProperties() const override {
     51       return MachineFunctionProperties().set(
     52           MachineFunctionProperties::Property::NoVRegs);
     53     }
     54   };
     55 }
     56 
     57 char HexagonSplitConst32AndConst64::ID = 0;
     58 
     59 INITIALIZE_PASS(HexagonSplitConst32AndConst64, "split-const-for-sdata",
     60       "Hexagon Split Const32s and Const64s", false, false)
     61 
     62 bool HexagonSplitConst32AndConst64::runOnMachineFunction(MachineFunction &Fn) {
     63   auto &HST = Fn.getSubtarget<HexagonSubtarget>();
     64   auto &HTM = static_cast<const HexagonTargetMachine&>(Fn.getTarget());
     65   auto &TLOF = *HTM.getObjFileLowering();
     66   if (HST.useSmallData() && TLOF.isSmallDataEnabled())
     67     return false;
     68 
     69   const TargetInstrInfo *TII = HST.getInstrInfo();
     70   const TargetRegisterInfo *TRI = HST.getRegisterInfo();
     71 
     72   // Loop over all of the basic blocks
     73   for (MachineBasicBlock &B : Fn) {
     74     for (auto I = B.begin(), E = B.end(); I != E; ) {
     75       MachineInstr &MI = *I;
     76       ++I;
     77       unsigned Opc = MI.getOpcode();
     78 
     79       if (Opc == Hexagon::CONST32) {
     80         unsigned DestReg = MI.getOperand(0).getReg();
     81         uint64_t ImmValue = MI.getOperand(1).getImm();
     82         const DebugLoc &DL = MI.getDebugLoc();
     83         BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), DestReg)
     84             .addImm(ImmValue);
     85         B.erase(&MI);
     86       } else if (Opc == Hexagon::CONST64) {
     87         unsigned DestReg = MI.getOperand(0).getReg();
     88         int64_t ImmValue = MI.getOperand(1).getImm();
     89         const DebugLoc &DL = MI.getDebugLoc();
     90         unsigned DestLo = TRI->getSubReg(DestReg, Hexagon::isub_lo);
     91         unsigned DestHi = TRI->getSubReg(DestReg, Hexagon::isub_hi);
     92 
     93         int32_t LowWord = (ImmValue & 0xFFFFFFFF);
     94         int32_t HighWord = (ImmValue >> 32) & 0xFFFFFFFF;
     95 
     96         BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), DestLo)
     97             .addImm(LowWord);
     98         BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), DestHi)
     99             .addImm(HighWord);
    100         B.erase(&MI);
    101       }
    102     }
    103   }
    104 
    105   return true;
    106 }
    107 
    108 
    109 //===----------------------------------------------------------------------===//
    110 //                         Public Constructor Functions
    111 //===----------------------------------------------------------------------===//
    112 FunctionPass *llvm::createHexagonSplitConst32AndConst64() {
    113   return new HexagonSplitConst32AndConst64();
    114 }
    115