| /external/swiftshader/third_party/subzero/src/ |
| IcePhiLoweringImpl.h | 42 auto *DestHi = llvm::cast<Variable>(Target->hiOperand(Dest));
44 auto *PhiHi = InstPhi::create(Func, Phi->getSrcSize(), DestHi);
|
| IceTargetLoweringMIPS32.cpp | [all...] |
| IceTargetLoweringARM32.cpp | [all...] |
| IceInstARM32.h | [all...] |
| IceTargetLoweringX86BaseImpl.h | [all...] |
| IceInstARM32.cpp | [all...] |
| IceTargetLoweringARM32.h | 447 // fake-def for Instr.DestHi here.
459 // fake-def for Instr.DestHi here.
835 void _umull(Variable *DestLo, Variable *DestHi, Variable *Src0,
837 // umull requires DestLo and DestHi to be assigned to different GPRs. The
842 Context.insert<InstFakeDef>(DestHi);
843 Context.insert<InstARM32Umull>(DestLo, DestHi, Src0, Src1, Pred);
844 Context.insert<InstFakeDef>(DestHi, DestLo)->setDestRedefined();
845 Context.insert<InstFakeUse>(DestHi);
[all...] |
| IceInstMIPS32.cpp | 307 DestHi = Dest64->getHi();
715 Variable *DestHi = getDestHi();
717 if (DestHi) {
719 DestHi->dump(Func);
[all...] |
| IceInstMIPS32.h | [all...] |
| IceTargetLoweringX86Base.h | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| HexagonSplitConst32AndConst64.cpp | 91 unsigned DestHi = TRI->getSubReg(DestReg, Hexagon::isub_hi);
98 BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), DestHi)
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonSplitConst32AndConst64.cpp | 141 unsigned DestHi = TRI->getSubReg(DestReg, Hexagon::subreg_hireg);
150 DestHi)
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64ExpandPseudoInsts.cpp | 679 MachineOperand &DestHi = MI.getOperand(1);
708 LoadCmpBB->addLiveIn(DestHi.getReg());
715 .addReg(DestHi.getReg(), RegState::Define)
722 .addReg(DestHi.getReg(), getKillRegState(DestHi.isDead()))
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/ |
| AVRInstrInfo.cpp | 56 unsigned DestLo, DestHi, SrcLo, SrcHi;
58 TRI.splitReg(DestReg, DestLo, DestHi);
64 BuildMI(MBB, MI, DL, get(AVR::MOVRdRr), DestHi)
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| AArch64ExpandPseudoInsts.cpp | 675 MachineOperand &DestHi = MI.getOperand(1);
703 .addReg(DestHi.getReg(), RegState::Define)
714 .addReg(DestHi.getReg(), getKillRegState(DestHi.isDead()))
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMExpandPseudoInsts.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| ARMExpandPseudoInsts.cpp | [all...] |
