1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * LayerScape Internal Memory Map 4 * 5 * Copyright (C) 2017 NXP Semiconductors 6 * Copyright 2014 Freescale Semiconductor, Inc. 7 */ 8 9 #ifndef __ARCH_FSL_LSCH3_IMMAP_H_ 10 #define __ARCH_FSL_LSCH3_IMMAP_H_ 11 12 #define CONFIG_SYS_IMMR 0x01000000 13 #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) 14 #define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000) 15 #define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000 16 #define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000) 17 #define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000) 18 #define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000) 19 #define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000) 20 #define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000) 21 #define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000) 22 #define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x010c0000) 23 #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x01140000) 24 #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000) 25 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500) 26 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600) 27 #define SYS_FSL_LS2080A_LS2085A_TIMER_ADDR 0x023d0000 28 #define CONFIG_SYS_FSL_TIMER_ADDR 0x023e0000 29 #define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \ 30 0x18A0) 31 #define FSL_PMU_PCTBENR_OFFSET (CONFIG_SYS_FSL_PMU_ADDR + 0x8A0) 32 #define FSL_LSCH3_SVR (CONFIG_SYS_FSL_GUTS_ADDR + 0xA4) 33 34 #define CONFIG_SYS_FSL_WRIOP1_ADDR (CONFIG_SYS_IMMR + 0x7B80000) 35 #define CONFIG_SYS_FSL_WRIOP1_MDIO1 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000) 36 #define CONFIG_SYS_FSL_WRIOP1_MDIO2 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x17000) 37 #define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR (CONFIG_SYS_IMMR + 0xEA0000) 38 39 #define CONFIG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL 40 #define CONFIG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL 41 #define CONFIG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL 42 #define CONFIG_SYS_FSL_DCSR_DDR4_ADDR 0x700133000ULL 43 44 #define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01000000) 45 #define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000) 46 #define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000) 47 #define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000) 48 #define GPIO4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01330000) 49 #define GPIO4_GPDIR_ADDR (GPIO4_BASE_ADDR + 0x0) 50 #define GPIO4_GPDAT_ADDR (GPIO4_BASE_ADDR + 0x8) 51 52 #define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000) 53 #define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000) 54 55 /* TZ Address Space Controller Definitions */ 56 #define TZASC1_BASE 0x01100000 /* as per CCSR map. */ 57 #define TZASC2_BASE 0x01110000 /* as per CCSR map. */ 58 #define TZASC3_BASE 0x01120000 /* as per CCSR map. */ 59 #define TZASC4_BASE 0x01130000 /* as per CCSR map. */ 60 #define TZASC_BUILD_CONFIG_REG(x) ((TZASC1_BASE + (x * 0x10000))) 61 #define TZASC_ACTION_REG(x) ((TZASC1_BASE + (x * 0x10000)) + 0x004) 62 #define TZASC_GATE_KEEPER(x) ((TZASC1_BASE + (x * 0x10000)) + 0x008) 63 #define TZASC_REGION_BASE_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x100) 64 #define TZASC_REGION_BASE_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x104) 65 #define TZASC_REGION_TOP_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x108) 66 #define TZASC_REGION_TOP_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x10C) 67 #define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110) 68 #define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114) 69 70 /* SATA */ 71 #define AHCI_BASE_ADDR1 (CONFIG_SYS_IMMR + 0x02200000) 72 #define AHCI_BASE_ADDR2 (CONFIG_SYS_IMMR + 0x02210000) 73 74 /* SFP */ 75 #define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200) 76 77 /* SEC */ 78 #define CONFIG_SYS_FSL_SEC_OFFSET 0x07000000ull 79 #define CONFIG_SYS_FSL_JR0_OFFSET 0x07010000ull 80 #define CONFIG_SYS_FSL_SEC_ADDR \ 81 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET) 82 #define CONFIG_SYS_FSL_JR0_ADDR \ 83 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET) 84 85 /* Security Monitor */ 86 #define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000) 87 88 /* MMU 500 */ 89 #define SMMU_SCR0 (SMMU_BASE + 0x0) 90 #define SMMU_SCR1 (SMMU_BASE + 0x4) 91 #define SMMU_SCR2 (SMMU_BASE + 0x8) 92 #define SMMU_SACR (SMMU_BASE + 0x10) 93 #define SMMU_IDR0 (SMMU_BASE + 0x20) 94 #define SMMU_IDR1 (SMMU_BASE + 0x24) 95 96 #define SMMU_NSCR0 (SMMU_BASE + 0x400) 97 #define SMMU_NSCR2 (SMMU_BASE + 0x408) 98 #define SMMU_NSACR (SMMU_BASE + 0x410) 99 100 #define SCR0_CLIENTPD_MASK 0x00000001 101 #define SCR0_USFCFG_MASK 0x00000400 102 103 104 /* PCIe */ 105 #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) 106 #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) 107 #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000) 108 #define CONFIG_SYS_PCIE4_ADDR (CONFIG_SYS_IMMR + 0x2700000) 109 #ifdef CONFIG_ARCH_LS1088A 110 #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x2000000000ULL 111 #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x2800000000ULL 112 #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x3000000000ULL 113 #else 114 #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x1000000000ULL 115 #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL 116 #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL 117 #define CONFIG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL 118 #endif 119 120 /* Device Configuration */ 121 #define DCFG_BASE 0x01e00000 122 #define DCFG_PORSR1 0x000 123 #define DCFG_PORSR1_RCW_SRC 0xff800000 124 #define DCFG_PORSR1_RCW_SRC_NOR 0x12f00000 125 #define DCFG_RCWSR13 0x130 126 #define DCFG_RCWSR13_DSPI (0 << 8) 127 #define DCFG_RCWSR15 0x138 128 #define DCFG_RCWSR15_IFCGRPABASE_QSPI 0x3 129 130 #define DCFG_DCSR_BASE 0X700100000ULL 131 #define DCFG_DCSR_PORCR1 0x000 132 133 /* Interrupt Sampling Control */ 134 #define ISC_BASE 0x01F70000 135 #define IRQCR_OFFSET 0x14 136 137 /* Supplemental Configuration */ 138 #define SCFG_BASE 0x01fc0000 139 #define SCFG_USB3PRM1CR 0x000 140 #define SCFG_USB3PRM1CR_INIT 0x27672b2a 141 #define SCFG_USB_TXVREFTUNE 0x9 142 #define SCFG_USB_SQRXTUNE_MASK 0x7 143 #define SCFG_QSPICLKCTLR 0x10 144 145 #define DCSR_BASE 0x700000000ULL 146 #define DCSR_USB_PHY1 0x4600000 147 #define DCSR_USB_PHY2 0x4610000 148 #define DCSR_USB_PHY_RX_OVRD_IN_HI 0x200C 149 #define USB_PHY_RX_EQ_VAL_1 0x0000 150 #define USB_PHY_RX_EQ_VAL_2 0x0080 151 #define USB_PHY_RX_EQ_VAL_3 0x0380 152 #define USB_PHY_RX_EQ_VAL_4 0x0b80 153 154 #define TP_ITYP_AV 0x00000001 /* Initiator available */ 155 #define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */ 156 #define TP_ITYP_TYPE_ARM 0x0 157 #define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */ 158 #define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */ 159 #define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */ 160 #define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */ 161 #define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */ 162 #define TY_ITYP_VER_A7 0x1 163 #define TY_ITYP_VER_A53 0x2 164 #define TY_ITYP_VER_A57 0x3 165 #define TY_ITYP_VER_A72 0x4 166 167 #define TP_CLUSTER_EOC 0x80000000 /* end of clusters */ 168 #define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */ 169 #define TP_INIT_PER_CLUSTER 4 170 /* This is chassis generation 3 */ 171 #ifndef __ASSEMBLY__ 172 struct sys_info { 173 unsigned long freq_processor[CONFIG_MAX_CPUS]; 174 /* frequency of platform PLL */ 175 unsigned long freq_systembus; 176 unsigned long freq_ddrbus; 177 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR 178 unsigned long freq_ddrbus2; 179 #endif 180 unsigned long freq_localbus; 181 unsigned long freq_qe; 182 #ifdef CONFIG_SYS_DPAA_FMAN 183 unsigned long freq_fman[CONFIG_SYS_NUM_FMAN]; 184 #endif 185 #ifdef CONFIG_SYS_DPAA_QBMAN 186 unsigned long freq_qman; 187 #endif 188 #ifdef CONFIG_SYS_DPAA_PME 189 unsigned long freq_pme; 190 #endif 191 }; 192 193 /* Global Utilities Block */ 194 struct ccsr_gur { 195 u32 porsr1; /* POR status 1 */ 196 u32 porsr2; /* POR status 2 */ 197 u8 res_008[0x20-0x8]; 198 u32 gpporcr1; /* General-purpose POR configuration */ 199 u32 gpporcr2; /* General-purpose POR configuration 2 */ 200 u32 gpporcr3; 201 u32 gpporcr4; 202 u8 res_030[0x60-0x30]; 203 #define FSL_CHASSIS3_DCFG_FUSESR_VID_MASK 0x1F 204 #define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK 0x1F 205 #if defined(CONFIG_ARCH_LS1088A) 206 #define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 25 207 #define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT 20 208 #else 209 #define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 2 210 #define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT 7 211 #endif 212 u32 dcfg_fusesr; /* Fuse status register */ 213 u8 res_064[0x70-0x64]; 214 u32 devdisr; /* Device disable control 1 */ 215 u32 devdisr2; /* Device disable control 2 */ 216 u32 devdisr3; /* Device disable control 3 */ 217 u32 devdisr4; /* Device disable control 4 */ 218 u32 devdisr5; /* Device disable control 5 */ 219 u32 devdisr6; /* Device disable control 6 */ 220 u8 res_088[0x94-0x88]; 221 u32 coredisr; /* Device disable control 7 */ 222 #define FSL_CHASSIS3_DEVDISR2_DPMAC1 0x00000001 223 #define FSL_CHASSIS3_DEVDISR2_DPMAC2 0x00000002 224 #define FSL_CHASSIS3_DEVDISR2_DPMAC3 0x00000004 225 #define FSL_CHASSIS3_DEVDISR2_DPMAC4 0x00000008 226 #define FSL_CHASSIS3_DEVDISR2_DPMAC5 0x00000010 227 #define FSL_CHASSIS3_DEVDISR2_DPMAC6 0x00000020 228 #define FSL_CHASSIS3_DEVDISR2_DPMAC7 0x00000040 229 #define FSL_CHASSIS3_DEVDISR2_DPMAC8 0x00000080 230 #define FSL_CHASSIS3_DEVDISR2_DPMAC9 0x00000100 231 #define FSL_CHASSIS3_DEVDISR2_DPMAC10 0x00000200 232 #define FSL_CHASSIS3_DEVDISR2_DPMAC11 0x00000400 233 #define FSL_CHASSIS3_DEVDISR2_DPMAC12 0x00000800 234 #define FSL_CHASSIS3_DEVDISR2_DPMAC13 0x00001000 235 #define FSL_CHASSIS3_DEVDISR2_DPMAC14 0x00002000 236 #define FSL_CHASSIS3_DEVDISR2_DPMAC15 0x00004000 237 #define FSL_CHASSIS3_DEVDISR2_DPMAC16 0x00008000 238 #define FSL_CHASSIS3_DEVDISR2_DPMAC17 0x00010000 239 #define FSL_CHASSIS3_DEVDISR2_DPMAC18 0x00020000 240 #define FSL_CHASSIS3_DEVDISR2_DPMAC19 0x00040000 241 #define FSL_CHASSIS3_DEVDISR2_DPMAC20 0x00080000 242 #define FSL_CHASSIS3_DEVDISR2_DPMAC21 0x00100000 243 #define FSL_CHASSIS3_DEVDISR2_DPMAC22 0x00200000 244 #define FSL_CHASSIS3_DEVDISR2_DPMAC23 0x00400000 245 #define FSL_CHASSIS3_DEVDISR2_DPMAC24 0x00800000 246 u8 res_098[0xa0-0x98]; 247 u32 pvr; /* Processor version */ 248 u32 svr; /* System version */ 249 u8 res_0a8[0x100-0xa8]; 250 u32 rcwsr[30]; /* Reset control word status */ 251 252 #define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT 2 253 #define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK 0x1f 254 #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT 10 255 #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK 0x3f 256 #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT 18 257 #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK 0x3f 258 259 #if defined(CONFIG_ARCH_LS2080A) 260 #define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK 0x00FF0000 261 #define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT 16 262 #define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK 0xFF000000 263 #define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT 24 264 #define FSL_CHASSIS3_SRDS1_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK 265 #define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT 266 #define FSL_CHASSIS3_SRDS2_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK 267 #define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT 268 #define FSL_CHASSIS3_SRDS1_REGSR 29 269 #define FSL_CHASSIS3_SRDS2_REGSR 29 270 #elif defined(CONFIG_ARCH_LS1088A) 271 #define FSL_CHASSIS3_EC1_REGSR 26 272 #define FSL_CHASSIS3_EC2_REGSR 26 273 #define FSL_CHASSIS3_RCWSR25_EC1_PRTCL_MASK 0x00000007 274 #define FSL_CHASSIS3_RCWSR25_EC1_PRTCL_SHIFT 0 275 #define FSL_CHASSIS3_RCWSR25_EC2_PRTCL_MASK 0x00000038 276 #define FSL_CHASSIS3_RCWSR25_EC2_PRTCL_SHIFT 3 277 #define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK 0xFFFF0000 278 #define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT 16 279 #define FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_MASK 0x0000FFFF 280 #define FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_SHIFT 0 281 #define FSL_CHASSIS3_SRDS1_PRTCL_MASK FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK 282 #define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT 283 #define FSL_CHASSIS3_SRDS2_PRTCL_MASK FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_MASK 284 #define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_SHIFT 285 #define FSL_CHASSIS3_SRDS1_REGSR 29 286 #define FSL_CHASSIS3_SRDS2_REGSR 30 287 #endif 288 #define RCW_SB_EN_REG_INDEX 9 289 #define RCW_SB_EN_MASK 0x00000400 290 291 u8 res_178[0x200-0x178]; 292 u32 scratchrw[16]; /* Scratch Read/Write */ 293 u8 res_240[0x300-0x240]; 294 u32 scratchw1r[4]; /* Scratch Read (Write once) */ 295 u8 res_310[0x400-0x310]; 296 u32 bootlocptrl; /* Boot location pointer low-order addr */ 297 u32 bootlocptrh; /* Boot location pointer high-order addr */ 298 u8 res_408[0x520-0x408]; 299 u32 usb1_amqr; 300 u32 usb2_amqr; 301 u8 res_528[0x530-0x528]; /* add more registers when needed */ 302 u32 sdmm1_amqr; 303 u8 res_534[0x550-0x534]; /* add more registers when needed */ 304 u32 sata1_amqr; 305 u32 sata2_amqr; 306 u8 res_558[0x570-0x558]; /* add more registers when needed */ 307 u32 misc1_amqr; 308 u8 res_574[0x590-0x574]; /* add more registers when needed */ 309 u32 spare1_amqr; 310 u32 spare2_amqr; 311 u8 res_598[0x620-0x598]; /* add more registers when needed */ 312 u32 gencr[7]; /* General Control Registers */ 313 u8 res_63c[0x640-0x63c]; /* add more registers when needed */ 314 u32 cgensr1; /* Core General Status Register */ 315 u8 res_644[0x660-0x644]; /* add more registers when needed */ 316 u32 cgencr1; /* Core General Control Register */ 317 u8 res_664[0x740-0x664]; /* add more registers when needed */ 318 u32 tp_ityp[64]; /* Topology Initiator Type Register */ 319 struct { 320 u32 upper; 321 u32 lower; 322 } tp_cluster[4]; /* Core cluster n Topology Register */ 323 u8 res_864[0x920-0x864]; /* add more registers when needed */ 324 u32 ioqoscr[8]; /*I/O Quality of Services Register */ 325 u32 uccr; 326 u8 res_944[0x960-0x944]; /* add more registers when needed */ 327 u32 ftmcr; 328 u8 res_964[0x990-0x964]; /* add more registers when needed */ 329 u32 coredisablesr; 330 u8 res_994[0xa00-0x994]; /* add more registers when needed */ 331 u32 sdbgcr; /*Secure Debug Confifuration Register */ 332 u8 res_a04[0xbf8-0xa04]; /* add more registers when needed */ 333 u32 ipbrr1; 334 u32 ipbrr2; 335 u8 res_858[0x1000-0xc00]; 336 }; 337 338 struct ccsr_clk_cluster_group { 339 struct { 340 u8 res_00[0x10]; 341 u32 csr; 342 u8 res_14[0x20-0x14]; 343 } hwncsr[3]; 344 u8 res_60[0x80-0x60]; 345 struct { 346 u32 gsr; 347 u8 res_84[0xa0-0x84]; 348 } pllngsr[3]; 349 u8 res_e0[0x100-0xe0]; 350 }; 351 352 struct ccsr_clk_ctrl { 353 struct { 354 u32 csr; /* core cluster n clock control status */ 355 u8 res_04[0x20-0x04]; 356 } clkcncsr[8]; 357 }; 358 359 struct ccsr_reset { 360 u32 rstcr; /* 0x000 */ 361 u32 rstcrsp; /* 0x004 */ 362 u8 res_008[0x10-0x08]; /* 0x008 */ 363 u32 rstrqmr1; /* 0x010 */ 364 u32 rstrqmr2; /* 0x014 */ 365 u32 rstrqsr1; /* 0x018 */ 366 u32 rstrqsr2; /* 0x01c */ 367 u32 rstrqwdtmrl; /* 0x020 */ 368 u32 rstrqwdtmru; /* 0x024 */ 369 u8 res_028[0x30-0x28]; /* 0x028 */ 370 u32 rstrqwdtsrl; /* 0x030 */ 371 u32 rstrqwdtsru; /* 0x034 */ 372 u8 res_038[0x60-0x38]; /* 0x038 */ 373 u32 brrl; /* 0x060 */ 374 u32 brru; /* 0x064 */ 375 u8 res_068[0x80-0x68]; /* 0x068 */ 376 u32 pirset; /* 0x080 */ 377 u32 pirclr; /* 0x084 */ 378 u8 res_088[0x90-0x88]; /* 0x088 */ 379 u32 brcorenbr; /* 0x090 */ 380 u8 res_094[0x100-0x94]; /* 0x094 */ 381 u32 rcw_reqr; /* 0x100 */ 382 u32 rcw_completion; /* 0x104 */ 383 u8 res_108[0x110-0x108]; /* 0x108 */ 384 u32 pbi_reqr; /* 0x110 */ 385 u32 pbi_completion; /* 0x114 */ 386 u8 res_118[0xa00-0x118]; /* 0x118 */ 387 u32 qmbm_warmrst; /* 0xa00 */ 388 u32 soc_warmrst; /* 0xa04 */ 389 u8 res_a08[0xbf8-0xa08]; /* 0xa08 */ 390 u32 ip_rev1; /* 0xbf8 */ 391 u32 ip_rev2; /* 0xbfc */ 392 }; 393 394 struct ccsr_serdes { 395 struct { 396 u32 rstctl; /* Reset Control Register */ 397 u32 pllcr0; /* PLL Control Register 0 */ 398 u32 pllcr1; /* PLL Control Register 1 */ 399 u32 pllcr2; /* PLL Control Register 2 */ 400 u32 pllcr3; /* PLL Control Register 3 */ 401 u32 pllcr4; /* PLL Control Register 4 */ 402 u32 pllcr5; /* PLL Control Register 5 */ 403 u8 res[0x20 - 0x1c]; 404 } bank[2]; 405 u8 res1[0x90 - 0x40]; 406 u32 srdstcalcr; /* TX Calibration Control */ 407 u32 srdstcalcr1; /* TX Calibration Control1 */ 408 u8 res2[0xa0 - 0x98]; 409 u32 srdsrcalcr; /* RX Calibration Control */ 410 u32 srdsrcalcr1; /* RX Calibration Control1 */ 411 u8 res3[0xb0 - 0xa8]; 412 u32 srdsgr0; /* General Register 0 */ 413 u8 res4[0x800 - 0xb4]; 414 struct serdes_lane { 415 u32 gcr0; /* General Control Register 0 */ 416 u32 gcr1; /* General Control Register 1 */ 417 u32 gcr2; /* General Control Register 2 */ 418 u32 ssc0; /* Speed Switch Control 0 */ 419 u32 rec0; /* Receive Equalization Control 0 */ 420 u32 rec1; /* Receive Equalization Control 1 */ 421 u32 tec0; /* Transmit Equalization Control 0 */ 422 u32 ssc1; /* Speed Switch Control 1 */ 423 u8 res1[0x840 - 0x820]; 424 } lane[8]; 425 u8 res5[0x19fc - 0xa00]; 426 }; 427 428 #endif /*__ASSEMBLY__*/ 429 #endif /* __ARCH_FSL_LSCH3_IMMAP_H_ */ 430
