/external/llvm/lib/Target/Mips/ |
Mips16RegisterInfo.cpp | 100 unsigned FrameReg; 103 FrameReg = Mips::SP; 107 FrameReg = Mips::S0; 111 FrameReg = MI.getOperand(OpNo+2).getReg(); 113 FrameReg = Mips::SP; 134 !Mips16InstrInfo::validImmediate(MI.getOpcode(), FrameReg, Offset)) { 140 FrameReg = TII.loadImmediate(FrameReg, Offset, MBB, II, DL, NewImm); 144 MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill);
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MipsSERegisterInfo.cpp | 135 unsigned FrameReg; 139 FrameReg = ABI.GetStackPtr(); 142 FrameReg = ABI.GetBasePtr(); 144 FrameReg = getFrameRegister(MF); 146 FrameReg = ABI.GetStackPtr(); 148 FrameReg = getFrameRegister(MF); 187 .addReg(FrameReg) 190 FrameReg = Reg; 204 BuildMI(MBB, II, DL, TII.get(ABI.GetPtrAdduOp()), Reg).addReg(FrameReg) 207 FrameReg = Reg [all...] |
MipsTargetStreamer.h | 183 unsigned FrameReg;
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/external/llvm/lib/Target/Sparc/ |
SparcRegisterInfo.cpp | 173 unsigned FrameReg; 175 Offset = TFI->getFrameIndexReference(MF, FrameIndex, FrameReg); 187 .addReg(FrameReg).addImm(0).addReg(SrcEvenReg); 188 replaceFI(MF, II, *StMI, dl, 0, Offset, FrameReg); 199 .addReg(FrameReg).addImm(0); 200 replaceFI(MF, II, *StMI, dl, 1, Offset, FrameReg); 208 replaceFI(MF, II, MI, dl, FIOperandNum, Offset, FrameReg);
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/ |
LanaiRegisterInfo.cpp | 157 unsigned FrameReg = getFrameRegister(MF); 160 FrameReg = getBaseRegister(); 162 FrameReg = Lanai::SP; 198 // Reg = FrameReg OP Reg 203 .addReg(FrameReg) 221 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, /*isDef=*/false); 239 .addReg(FrameReg) 243 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, /*isDef=*/false);
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
Mips16RegisterInfo.cpp | 100 unsigned FrameReg; 103 FrameReg = Mips::SP; 107 FrameReg = Mips::S0; 111 FrameReg = MI.getOperand(OpNo+2).getReg(); 113 FrameReg = Mips::SP; 134 !Mips16InstrInfo::validImmediate(MI.getOpcode(), FrameReg, Offset)) { 140 FrameReg = TII.loadImmediate(FrameReg, Offset, MBB, II, DL, NewImm); 144 MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill);
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MipsSERegisterInfo.cpp | 179 unsigned FrameReg; 183 FrameReg = ABI.GetStackPtr(); 186 FrameReg = ABI.GetBasePtr(); 188 FrameReg = getFrameRegister(MF); 190 FrameReg = ABI.GetStackPtr(); 192 FrameReg = getFrameRegister(MF); 233 .addReg(FrameReg) 236 FrameReg = Reg; 250 BuildMI(MBB, II, DL, TII.get(ABI.GetPtrAdduOp()), Reg).addReg(FrameReg) 253 FrameReg = Reg [all...] |
MipsTargetStreamer.h | 202 unsigned FrameReg;
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/ |
RISCVRegisterInfo.cpp | 80 unsigned FrameReg; 82 getFrameLowering(MF)->getFrameIndexReference(MF, FrameIndex, FrameReg) + 96 // Modify Offset and FrameReg appropriately 100 .addReg(FrameReg) 103 FrameReg = ScratchReg; 108 .ChangeToRegister(FrameReg, false, false, FrameRegIsKill);
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/ |
SparcRegisterInfo.cpp | 173 unsigned FrameReg; 175 Offset = TFI->getFrameIndexReference(MF, FrameIndex, FrameReg); 187 .addReg(FrameReg).addImm(0).addReg(SrcEvenReg); 188 replaceFI(MF, II, *StMI, dl, 0, Offset, FrameReg); 199 .addReg(FrameReg).addImm(0); 200 replaceFI(MF, II, *StMI, dl, 1, Offset, FrameReg); 208 replaceFI(MF, II, MI, dl, FIOperandNum, Offset, FrameReg);
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/external/llvm/lib/Target/Lanai/ |
LanaiRegisterInfo.cpp | 157 unsigned FrameReg = getFrameRegister(MF); 160 FrameReg = getBaseRegister(); 162 FrameReg = Lanai::SP; 198 // Reg = FrameReg OP Reg 203 .addReg(FrameReg) 221 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, /*isDef=*/false); 239 .addReg(FrameReg) 243 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, /*isDef=*/false);
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/external/llvm/lib/Target/XCore/ |
XCoreRegisterInfo.cpp | 64 unsigned Reg, unsigned FrameReg, int Offset ) { 72 .addReg(FrameReg) 79 .addReg(FrameReg) 85 .addReg(FrameReg) 95 unsigned Reg, unsigned FrameReg, 108 .addReg(FrameReg) 115 .addReg(FrameReg) 121 .addReg(FrameReg) 289 unsigned FrameReg = getFrameRegister(MF); 293 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/) [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/XCore/ |
XCoreRegisterInfo.cpp | 198 unsigned FrameReg = getFrameRegister(MF); 202 MI.getOperand(i).ChangeToRegister(FrameReg, false /*isDef*/); 240 .addReg(FrameReg) 246 .addReg(FrameReg) 251 .addReg(FrameReg) 261 .addReg(FrameReg) 267 .addReg(FrameReg) 272 .addReg(FrameReg)
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARC/ |
ARCRegisterInfo.cpp | 41 unsigned FrameReg, int Offset, int StackSize, 47 unsigned BaseReg = FrameReg; 70 << " for FrameReg=" << printReg(FrameReg, TRI) 78 .addReg(FrameReg) 114 .addReg(FrameReg) 190 unsigned FrameReg = getFrameRegister(MF); 191 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/);
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/XCore/ |
XCoreRegisterInfo.cpp | 64 unsigned Reg, unsigned FrameReg, int Offset ) { 72 .addReg(FrameReg) 79 .addReg(FrameReg) 85 .addReg(FrameReg) 95 unsigned Reg, unsigned FrameReg, 108 .addReg(FrameReg) 115 .addReg(FrameReg) 121 .addReg(FrameReg) 287 unsigned FrameReg = getFrameRegister(MF); 291 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/) [all...] |
/external/llvm/lib/CodeGen/ |
GCRootLowering.cpp | 322 unsigned FrameReg; // FIXME: surely GCRoot ought to store the 324 RI->StackOffset = TFI->getFrameIndexReference(MF, RI->Num, FrameReg);
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/external/llvm/lib/Target/AArch64/ |
AArch64RegisterInfo.cpp | 376 unsigned FrameReg; 382 Offset = TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg, 385 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/); 391 Offset = TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg); 392 if (rewriteAArch64FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII)) 403 emitFrameOffset(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, Offset, TII);
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/external/llvm/lib/Target/X86/ |
X86RegisterInfo.cpp | 665 unsigned FrameReg = getFrameRegister(MF); 667 FrameReg = getX86SubSuperRegister(FrameReg, 32); 668 return FrameReg;
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
GCRootLowering.cpp | 321 unsigned FrameReg; // FIXME: surely GCRoot ought to store the 323 RI->StackOffset = TFI->getFrameIndexReference(MF, RI->Num, FrameReg);
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
AArch64RegisterInfo.cpp | 404 unsigned FrameReg; 410 Offset = TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg, 413 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/); 419 Offset = TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg); 420 if (rewriteAArch64FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII)) 431 emitFrameOffset(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, Offset, TII);
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/MCTargetDesc/ |
X86WinCOFFTargetStreamer.cpp | 248 unsigned FrameReg = 0; 294 if (FrameReg) { 295 // CFA is FrameReg + FrameRegOff. 296 FuncOS << "$T0 " << printFPOReg(MRI, FrameReg) << " " << FrameRegOff 380 FSM.FrameReg = Inst.RegOrOffset; 387 if (FSM.FrameReg)
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
X86RegisterInfo.cpp | 758 unsigned FrameReg = getFrameRegister(MF); 760 FrameReg = getX86SubSuperRegister(FrameReg, 32); 761 return FrameReg;
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/AsmParser/ |
X86AsmInstrumentation.cpp | 517 unsigned FrameReg = GetFrameRegGeneric(Ctx, Out); 518 if (FrameReg == X86::NoRegister) 519 return FrameReg; 520 return getX86SubSuperRegister(FrameReg, 32); 550 unsigned FrameReg = GetFrameReg(Ctx, Out); 551 if (MRI && FrameReg != X86::NoRegister) { 553 if (FrameReg == X86::ESP) { 560 MCInstBuilder(X86::MOV32rr).addReg(LocalFrameReg).addReg(FrameReg)); 585 unsigned FrameReg = GetFrameReg(Ctx, Out); 586 if (Ctx.getRegisterInfo() && FrameReg != X86::NoRegister) [all...] |
/external/llvm/lib/CodeGen/AsmPrinter/ |
DwarfCompileUnit.cpp | 549 unsigned FrameReg = 0; 551 int Offset = TFI->getFrameIndexReference(*Asm->MF, FI, FrameReg); 554 FrameReg, Offset); [all...] |
/external/llvm/lib/Target/ARM/ |
ARMBaseRegisterInfo.cpp | 720 unsigned FrameReg; 722 int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj); 729 if (RS && FrameReg == ARM::SP && RS->isScavengingFrameIndex(FrameIndex)){ 744 Done = rewriteARMFrameIndex(MI, FIOperandNum, FrameReg, Offset, TII); 747 Done = rewriteT2FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII); 767 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, false); 771 emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, 775 emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
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