1 //===- AArch64RegisterInfo.cpp - AArch64 Register Information -------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the AArch64 implementation of the TargetRegisterInfo 11 // class. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "AArch64RegisterInfo.h" 16 #include "AArch64FrameLowering.h" 17 #include "AArch64InstrInfo.h" 18 #include "AArch64MachineFunctionInfo.h" 19 #include "AArch64Subtarget.h" 20 #include "MCTargetDesc/AArch64AddressingModes.h" 21 #include "llvm/ADT/BitVector.h" 22 #include "llvm/ADT/Triple.h" 23 #include "llvm/CodeGen/MachineFrameInfo.h" 24 #include "llvm/CodeGen/MachineInstrBuilder.h" 25 #include "llvm/CodeGen/MachineRegisterInfo.h" 26 #include "llvm/CodeGen/RegisterScavenging.h" 27 #include "llvm/IR/Function.h" 28 #include "llvm/Support/raw_ostream.h" 29 #include "llvm/CodeGen/TargetFrameLowering.h" 30 #include "llvm/Target/TargetOptions.h" 31 32 using namespace llvm; 33 34 #define GET_REGINFO_TARGET_DESC 35 #include "AArch64GenRegisterInfo.inc" 36 37 AArch64RegisterInfo::AArch64RegisterInfo(const Triple &TT) 38 : AArch64GenRegisterInfo(AArch64::LR), TT(TT) { 39 AArch64_MC::initLLVMToCVRegMapping(this); 40 } 41 42 const MCPhysReg * 43 AArch64RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 44 assert(MF && "Invalid MachineFunction pointer."); 45 if (MF->getFunction().getCallingConv() == CallingConv::GHC) 46 // GHC set of callee saved regs is empty as all those regs are 47 // used for passing STG regs around 48 return CSR_AArch64_NoRegs_SaveList; 49 if (MF->getFunction().getCallingConv() == CallingConv::AnyReg) 50 return CSR_AArch64_AllRegs_SaveList; 51 if (MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS) 52 return MF->getInfo<AArch64FunctionInfo>()->isSplitCSR() ? 53 CSR_AArch64_CXX_TLS_Darwin_PE_SaveList : 54 CSR_AArch64_CXX_TLS_Darwin_SaveList; 55 if (MF->getSubtarget<AArch64Subtarget>().getTargetLowering() 56 ->supportSwiftError() && 57 MF->getFunction().getAttributes().hasAttrSomewhere( 58 Attribute::SwiftError)) 59 return CSR_AArch64_AAPCS_SwiftError_SaveList; 60 if (MF->getFunction().getCallingConv() == CallingConv::PreserveMost) 61 return CSR_AArch64_RT_MostRegs_SaveList; 62 else 63 return CSR_AArch64_AAPCS_SaveList; 64 } 65 66 const MCPhysReg *AArch64RegisterInfo::getCalleeSavedRegsViaCopy( 67 const MachineFunction *MF) const { 68 assert(MF && "Invalid MachineFunction pointer."); 69 if (MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS && 70 MF->getInfo<AArch64FunctionInfo>()->isSplitCSR()) 71 return CSR_AArch64_CXX_TLS_Darwin_ViaCopy_SaveList; 72 return nullptr; 73 } 74 75 const TargetRegisterClass * 76 AArch64RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, 77 unsigned Idx) const { 78 // edge case for GPR/FPR register classes 79 if (RC == &AArch64::GPR32allRegClass && Idx == AArch64::hsub) 80 return &AArch64::FPR32RegClass; 81 else if (RC == &AArch64::GPR64allRegClass && Idx == AArch64::hsub) 82 return &AArch64::FPR64RegClass; 83 84 // Forward to TableGen's default version. 85 return AArch64GenRegisterInfo::getSubClassWithSubReg(RC, Idx); 86 } 87 88 const uint32_t * 89 AArch64RegisterInfo::getCallPreservedMask(const MachineFunction &MF, 90 CallingConv::ID CC) const { 91 bool SCS = MF.getFunction().hasFnAttribute(Attribute::ShadowCallStack); 92 if (CC == CallingConv::GHC) 93 // This is academic because all GHC calls are (supposed to be) tail calls 94 return SCS ? CSR_AArch64_NoRegs_SCS_RegMask : CSR_AArch64_NoRegs_RegMask; 95 if (CC == CallingConv::AnyReg) 96 return SCS ? CSR_AArch64_AllRegs_SCS_RegMask : CSR_AArch64_AllRegs_RegMask; 97 if (CC == CallingConv::CXX_FAST_TLS) 98 return SCS ? CSR_AArch64_CXX_TLS_Darwin_SCS_RegMask 99 : CSR_AArch64_CXX_TLS_Darwin_RegMask; 100 if (MF.getSubtarget<AArch64Subtarget>().getTargetLowering() 101 ->supportSwiftError() && 102 MF.getFunction().getAttributes().hasAttrSomewhere(Attribute::SwiftError)) 103 return SCS ? CSR_AArch64_AAPCS_SwiftError_SCS_RegMask 104 : CSR_AArch64_AAPCS_SwiftError_RegMask; 105 if (CC == CallingConv::PreserveMost) 106 return SCS ? CSR_AArch64_RT_MostRegs_SCS_RegMask 107 : CSR_AArch64_RT_MostRegs_RegMask; 108 else 109 return SCS ? CSR_AArch64_AAPCS_SCS_RegMask : CSR_AArch64_AAPCS_RegMask; 110 } 111 112 const uint32_t *AArch64RegisterInfo::getTLSCallPreservedMask() const { 113 if (TT.isOSDarwin()) 114 return CSR_AArch64_TLS_Darwin_RegMask; 115 116 assert(TT.isOSBinFormatELF() && "Invalid target"); 117 return CSR_AArch64_TLS_ELF_RegMask; 118 } 119 120 const uint32_t * 121 AArch64RegisterInfo::getThisReturnPreservedMask(const MachineFunction &MF, 122 CallingConv::ID CC) const { 123 // This should return a register mask that is the same as that returned by 124 // getCallPreservedMask but that additionally preserves the register used for 125 // the first i64 argument (which must also be the register used to return a 126 // single i64 return value) 127 // 128 // In case that the calling convention does not use the same register for 129 // both, the function should return NULL (does not currently apply) 130 assert(CC != CallingConv::GHC && "should not be GHC calling convention."); 131 return CSR_AArch64_AAPCS_ThisReturn_RegMask; 132 } 133 134 const uint32_t *AArch64RegisterInfo::getWindowsStackProbePreservedMask() const { 135 return CSR_AArch64_StackProbe_Windows_RegMask; 136 } 137 138 BitVector 139 AArch64RegisterInfo::getReservedRegs(const MachineFunction &MF) const { 140 const AArch64FrameLowering *TFI = getFrameLowering(MF); 141 142 // FIXME: avoid re-calculating this every time. 143 BitVector Reserved(getNumRegs()); 144 markSuperRegs(Reserved, AArch64::WSP); 145 markSuperRegs(Reserved, AArch64::WZR); 146 147 if (TFI->hasFP(MF) || TT.isOSDarwin()) 148 markSuperRegs(Reserved, AArch64::W29); 149 150 if (MF.getSubtarget<AArch64Subtarget>().isX18Reserved()) 151 markSuperRegs(Reserved, AArch64::W18); // Platform register 152 153 if (MF.getSubtarget<AArch64Subtarget>().isX20Reserved()) 154 markSuperRegs(Reserved, AArch64::W20); // Platform register 155 156 if (hasBasePointer(MF)) 157 markSuperRegs(Reserved, AArch64::W19); 158 159 assert(checkAllSuperRegsMarked(Reserved)); 160 return Reserved; 161 } 162 163 bool AArch64RegisterInfo::isReservedReg(const MachineFunction &MF, 164 unsigned Reg) const { 165 const AArch64FrameLowering *TFI = getFrameLowering(MF); 166 167 switch (Reg) { 168 default: 169 break; 170 case AArch64::SP: 171 case AArch64::XZR: 172 case AArch64::WSP: 173 case AArch64::WZR: 174 return true; 175 case AArch64::X18: 176 case AArch64::W18: 177 return MF.getSubtarget<AArch64Subtarget>().isX18Reserved(); 178 case AArch64::X19: 179 case AArch64::W19: 180 return hasBasePointer(MF); 181 case AArch64::X20: 182 case AArch64::W20: 183 return MF.getSubtarget<AArch64Subtarget>().isX20Reserved(); 184 case AArch64::FP: 185 case AArch64::W29: 186 return TFI->hasFP(MF) || TT.isOSDarwin(); 187 } 188 189 return false; 190 } 191 192 bool AArch64RegisterInfo::isConstantPhysReg(unsigned PhysReg) const { 193 return PhysReg == AArch64::WZR || PhysReg == AArch64::XZR; 194 } 195 196 const TargetRegisterClass * 197 AArch64RegisterInfo::getPointerRegClass(const MachineFunction &MF, 198 unsigned Kind) const { 199 return &AArch64::GPR64spRegClass; 200 } 201 202 const TargetRegisterClass * 203 AArch64RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const { 204 if (RC == &AArch64::CCRRegClass) 205 return &AArch64::GPR64RegClass; // Only MSR & MRS copy NZCV. 206 return RC; 207 } 208 209 unsigned AArch64RegisterInfo::getBaseRegister() const { return AArch64::X19; } 210 211 bool AArch64RegisterInfo::hasBasePointer(const MachineFunction &MF) const { 212 const MachineFrameInfo &MFI = MF.getFrameInfo(); 213 214 // In the presence of variable sized objects, if the fixed stack size is 215 // large enough that referencing from the FP won't result in things being 216 // in range relatively often, we can use a base pointer to allow access 217 // from the other direction like the SP normally works. 218 // Furthermore, if both variable sized objects are present, and the 219 // stack needs to be dynamically re-aligned, the base pointer is the only 220 // reliable way to reference the locals. 221 if (MFI.hasVarSizedObjects()) { 222 if (needsStackRealignment(MF)) 223 return true; 224 // Conservatively estimate whether the negative offset from the frame 225 // pointer will be sufficient to reach. If a function has a smallish 226 // frame, it's less likely to have lots of spills and callee saved 227 // space, so it's all more likely to be within range of the frame pointer. 228 // If it's wrong, we'll materialize the constant and still get to the 229 // object; it's just suboptimal. Negative offsets use the unscaled 230 // load/store instructions, which have a 9-bit signed immediate. 231 return MFI.getLocalFrameSize() >= 256; 232 } 233 234 return false; 235 } 236 237 unsigned 238 AArch64RegisterInfo::getFrameRegister(const MachineFunction &MF) const { 239 const AArch64FrameLowering *TFI = getFrameLowering(MF); 240 return TFI->hasFP(MF) ? AArch64::FP : AArch64::SP; 241 } 242 243 bool AArch64RegisterInfo::requiresRegisterScavenging( 244 const MachineFunction &MF) const { 245 return true; 246 } 247 248 bool AArch64RegisterInfo::requiresVirtualBaseRegisters( 249 const MachineFunction &MF) const { 250 return true; 251 } 252 253 bool 254 AArch64RegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const { 255 // This function indicates whether the emergency spillslot should be placed 256 // close to the beginning of the stackframe (closer to FP) or the end 257 // (closer to SP). 258 // 259 // The beginning works most reliably if we have a frame pointer. 260 const AArch64FrameLowering &TFI = *getFrameLowering(MF); 261 return TFI.hasFP(MF); 262 } 263 264 bool AArch64RegisterInfo::requiresFrameIndexScavenging( 265 const MachineFunction &MF) const { 266 return true; 267 } 268 269 bool 270 AArch64RegisterInfo::cannotEliminateFrame(const MachineFunction &MF) const { 271 const MachineFrameInfo &MFI = MF.getFrameInfo(); 272 if (MF.getTarget().Options.DisableFramePointerElim(MF) && MFI.adjustsStack()) 273 return true; 274 return MFI.hasVarSizedObjects() || MFI.isFrameAddressTaken(); 275 } 276 277 /// needsFrameBaseReg - Returns true if the instruction's frame index 278 /// reference would be better served by a base register other than FP 279 /// or SP. Used by LocalStackFrameAllocation to determine which frame index 280 /// references it should create new base registers for. 281 bool AArch64RegisterInfo::needsFrameBaseReg(MachineInstr *MI, 282 int64_t Offset) const { 283 for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) 284 assert(i < MI->getNumOperands() && 285 "Instr doesn't have FrameIndex operand!"); 286 287 // It's the load/store FI references that cause issues, as it can be difficult 288 // to materialize the offset if it won't fit in the literal field. Estimate 289 // based on the size of the local frame and some conservative assumptions 290 // about the rest of the stack frame (note, this is pre-regalloc, so 291 // we don't know everything for certain yet) whether this offset is likely 292 // to be out of range of the immediate. Return true if so. 293 294 // We only generate virtual base registers for loads and stores, so 295 // return false for everything else. 296 if (!MI->mayLoad() && !MI->mayStore()) 297 return false; 298 299 // Without a virtual base register, if the function has variable sized 300 // objects, all fixed-size local references will be via the frame pointer, 301 // Approximate the offset and see if it's legal for the instruction. 302 // Note that the incoming offset is based on the SP value at function entry, 303 // so it'll be negative. 304 MachineFunction &MF = *MI->getParent()->getParent(); 305 const AArch64FrameLowering *TFI = getFrameLowering(MF); 306 MachineFrameInfo &MFI = MF.getFrameInfo(); 307 308 // Estimate an offset from the frame pointer. 309 // Conservatively assume all GPR callee-saved registers get pushed. 310 // FP, LR, X19-X28, D8-D15. 64-bits each. 311 int64_t FPOffset = Offset - 16 * 20; 312 // Estimate an offset from the stack pointer. 313 // The incoming offset is relating to the SP at the start of the function, 314 // but when we access the local it'll be relative to the SP after local 315 // allocation, so adjust our SP-relative offset by that allocation size. 316 Offset += MFI.getLocalFrameSize(); 317 // Assume that we'll have at least some spill slots allocated. 318 // FIXME: This is a total SWAG number. We should run some statistics 319 // and pick a real one. 320 Offset += 128; // 128 bytes of spill slots 321 322 // If there is a frame pointer, try using it. 323 // The FP is only available if there is no dynamic realignment. We 324 // don't know for sure yet whether we'll need that, so we guess based 325 // on whether there are any local variables that would trigger it. 326 if (TFI->hasFP(MF) && isFrameOffsetLegal(MI, AArch64::FP, FPOffset)) 327 return false; 328 329 // If we can reference via the stack pointer or base pointer, try that. 330 // FIXME: This (and the code that resolves the references) can be improved 331 // to only disallow SP relative references in the live range of 332 // the VLA(s). In practice, it's unclear how much difference that 333 // would make, but it may be worth doing. 334 if (isFrameOffsetLegal(MI, AArch64::SP, Offset)) 335 return false; 336 337 // The offset likely isn't legal; we want to allocate a virtual base register. 338 return true; 339 } 340 341 bool AArch64RegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, 342 unsigned BaseReg, 343 int64_t Offset) const { 344 assert(Offset <= INT_MAX && "Offset too big to fit in int."); 345 assert(MI && "Unable to get the legal offset for nil instruction."); 346 int SaveOffset = Offset; 347 return isAArch64FrameOffsetLegal(*MI, SaveOffset) & AArch64FrameOffsetIsLegal; 348 } 349 350 /// Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx 351 /// at the beginning of the basic block. 352 void AArch64RegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB, 353 unsigned BaseReg, 354 int FrameIdx, 355 int64_t Offset) const { 356 MachineBasicBlock::iterator Ins = MBB->begin(); 357 DebugLoc DL; // Defaults to "unknown" 358 if (Ins != MBB->end()) 359 DL = Ins->getDebugLoc(); 360 const MachineFunction &MF = *MBB->getParent(); 361 const AArch64InstrInfo *TII = 362 MF.getSubtarget<AArch64Subtarget>().getInstrInfo(); 363 const MCInstrDesc &MCID = TII->get(AArch64::ADDXri); 364 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 365 MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF)); 366 unsigned Shifter = AArch64_AM::getShifterImm(AArch64_AM::LSL, 0); 367 368 BuildMI(*MBB, Ins, DL, MCID, BaseReg) 369 .addFrameIndex(FrameIdx) 370 .addImm(Offset) 371 .addImm(Shifter); 372 } 373 374 void AArch64RegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, 375 int64_t Offset) const { 376 int Off = Offset; // ARM doesn't need the general 64-bit offsets 377 unsigned i = 0; 378 379 while (!MI.getOperand(i).isFI()) { 380 ++i; 381 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 382 } 383 const MachineFunction *MF = MI.getParent()->getParent(); 384 const AArch64InstrInfo *TII = 385 MF->getSubtarget<AArch64Subtarget>().getInstrInfo(); 386 bool Done = rewriteAArch64FrameIndex(MI, i, BaseReg, Off, TII); 387 assert(Done && "Unable to resolve frame index!"); 388 (void)Done; 389 } 390 391 void AArch64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 392 int SPAdj, unsigned FIOperandNum, 393 RegScavenger *RS) const { 394 assert(SPAdj == 0 && "Unexpected"); 395 396 MachineInstr &MI = *II; 397 MachineBasicBlock &MBB = *MI.getParent(); 398 MachineFunction &MF = *MBB.getParent(); 399 const AArch64InstrInfo *TII = 400 MF.getSubtarget<AArch64Subtarget>().getInstrInfo(); 401 const AArch64FrameLowering *TFI = getFrameLowering(MF); 402 403 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 404 unsigned FrameReg; 405 int Offset; 406 407 // Special handling of dbg_value, stackmap and patchpoint instructions. 408 if (MI.isDebugValue() || MI.getOpcode() == TargetOpcode::STACKMAP || 409 MI.getOpcode() == TargetOpcode::PATCHPOINT) { 410 Offset = TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg, 411 /*PreferFP=*/true); 412 Offset += MI.getOperand(FIOperandNum + 1).getImm(); 413 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/); 414 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset); 415 return; 416 } 417 418 // Modify MI as necessary to handle as much of 'Offset' as possible 419 Offset = TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg); 420 if (rewriteAArch64FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII)) 421 return; 422 423 assert((!RS || !RS->isScavengingFrameIndex(FrameIndex)) && 424 "Emergency spill slot is out of reach"); 425 426 // If we get here, the immediate doesn't fit into the instruction. We folded 427 // as much as possible above. Handle the rest, providing a register that is 428 // SP+LargeImm. 429 unsigned ScratchReg = 430 MF.getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass); 431 emitFrameOffset(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, Offset, TII); 432 MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false, true); 433 } 434 435 unsigned AArch64RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, 436 MachineFunction &MF) const { 437 const AArch64FrameLowering *TFI = getFrameLowering(MF); 438 439 switch (RC->getID()) { 440 default: 441 return 0; 442 case AArch64::GPR32RegClassID: 443 case AArch64::GPR32spRegClassID: 444 case AArch64::GPR32allRegClassID: 445 case AArch64::GPR64spRegClassID: 446 case AArch64::GPR64allRegClassID: 447 case AArch64::GPR64RegClassID: 448 case AArch64::GPR32commonRegClassID: 449 case AArch64::GPR64commonRegClassID: 450 return 32 - 1 // XZR/SP 451 - (TFI->hasFP(MF) || TT.isOSDarwin()) // FP 452 - MF.getSubtarget<AArch64Subtarget>() 453 .isX18Reserved() // X18 reserved as platform register 454 - MF.getSubtarget<AArch64Subtarget>() 455 .isX20Reserved() // X20 reserved as platform register 456 - hasBasePointer(MF); // X19 457 case AArch64::FPR8RegClassID: 458 case AArch64::FPR16RegClassID: 459 case AArch64::FPR32RegClassID: 460 case AArch64::FPR64RegClassID: 461 case AArch64::FPR128RegClassID: 462 return 32; 463 464 case AArch64::DDRegClassID: 465 case AArch64::DDDRegClassID: 466 case AArch64::DDDDRegClassID: 467 case AArch64::QQRegClassID: 468 case AArch64::QQQRegClassID: 469 case AArch64::QQQQRegClassID: 470 return 32; 471 472 case AArch64::FPR128_loRegClassID: 473 return 16; 474 } 475 } 476