1 //===- AArch64RegisterInfo.cpp - AArch64 Register Information -------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the AArch64 implementation of the TargetRegisterInfo 11 // class. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "AArch64RegisterInfo.h" 16 #include "AArch64FrameLowering.h" 17 #include "AArch64InstrInfo.h" 18 #include "AArch64MachineFunctionInfo.h" 19 #include "AArch64Subtarget.h" 20 #include "MCTargetDesc/AArch64AddressingModes.h" 21 #include "llvm/ADT/BitVector.h" 22 #include "llvm/ADT/Triple.h" 23 #include "llvm/CodeGen/MachineFrameInfo.h" 24 #include "llvm/CodeGen/MachineInstrBuilder.h" 25 #include "llvm/CodeGen/MachineRegisterInfo.h" 26 #include "llvm/CodeGen/RegisterScavenging.h" 27 #include "llvm/IR/Function.h" 28 #include "llvm/Support/raw_ostream.h" 29 #include "llvm/Target/TargetFrameLowering.h" 30 #include "llvm/Target/TargetOptions.h" 31 32 using namespace llvm; 33 34 #define GET_REGINFO_TARGET_DESC 35 #include "AArch64GenRegisterInfo.inc" 36 37 AArch64RegisterInfo::AArch64RegisterInfo(const Triple &TT) 38 : AArch64GenRegisterInfo(AArch64::LR), TT(TT) {} 39 40 const MCPhysReg * 41 AArch64RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 42 assert(MF && "Invalid MachineFunction pointer."); 43 if (MF->getFunction()->getCallingConv() == CallingConv::GHC) 44 // GHC set of callee saved regs is empty as all those regs are 45 // used for passing STG regs around 46 return CSR_AArch64_NoRegs_SaveList; 47 if (MF->getFunction()->getCallingConv() == CallingConv::AnyReg) 48 return CSR_AArch64_AllRegs_SaveList; 49 if (MF->getFunction()->getCallingConv() == CallingConv::CXX_FAST_TLS) 50 return MF->getInfo<AArch64FunctionInfo>()->isSplitCSR() ? 51 CSR_AArch64_CXX_TLS_Darwin_PE_SaveList : 52 CSR_AArch64_CXX_TLS_Darwin_SaveList; 53 if (MF->getSubtarget<AArch64Subtarget>().getTargetLowering() 54 ->supportSwiftError() && 55 MF->getFunction()->getAttributes().hasAttrSomewhere( 56 Attribute::SwiftError)) 57 return CSR_AArch64_AAPCS_SwiftError_SaveList; 58 if (MF->getFunction()->getCallingConv() == CallingConv::PreserveMost) 59 return CSR_AArch64_RT_MostRegs_SaveList; 60 else 61 return CSR_AArch64_AAPCS_SaveList; 62 } 63 64 const MCPhysReg *AArch64RegisterInfo::getCalleeSavedRegsViaCopy( 65 const MachineFunction *MF) const { 66 assert(MF && "Invalid MachineFunction pointer."); 67 if (MF->getFunction()->getCallingConv() == CallingConv::CXX_FAST_TLS && 68 MF->getInfo<AArch64FunctionInfo>()->isSplitCSR()) 69 return CSR_AArch64_CXX_TLS_Darwin_ViaCopy_SaveList; 70 return nullptr; 71 } 72 73 const uint32_t * 74 AArch64RegisterInfo::getCallPreservedMask(const MachineFunction &MF, 75 CallingConv::ID CC) const { 76 if (CC == CallingConv::GHC) 77 // This is academic becase all GHC calls are (supposed to be) tail calls 78 return CSR_AArch64_NoRegs_RegMask; 79 if (CC == CallingConv::AnyReg) 80 return CSR_AArch64_AllRegs_RegMask; 81 if (CC == CallingConv::CXX_FAST_TLS) 82 return CSR_AArch64_CXX_TLS_Darwin_RegMask; 83 if (MF.getSubtarget<AArch64Subtarget>().getTargetLowering() 84 ->supportSwiftError() && 85 MF.getFunction()->getAttributes().hasAttrSomewhere(Attribute::SwiftError)) 86 return CSR_AArch64_AAPCS_SwiftError_RegMask; 87 if (CC == CallingConv::PreserveMost) 88 return CSR_AArch64_RT_MostRegs_RegMask; 89 else 90 return CSR_AArch64_AAPCS_RegMask; 91 } 92 93 const uint32_t *AArch64RegisterInfo::getTLSCallPreservedMask() const { 94 if (TT.isOSDarwin()) 95 return CSR_AArch64_TLS_Darwin_RegMask; 96 97 assert(TT.isOSBinFormatELF() && "only expect Darwin or ELF TLS"); 98 return CSR_AArch64_TLS_ELF_RegMask; 99 } 100 101 const uint32_t * 102 AArch64RegisterInfo::getThisReturnPreservedMask(const MachineFunction &MF, 103 CallingConv::ID CC) const { 104 // This should return a register mask that is the same as that returned by 105 // getCallPreservedMask but that additionally preserves the register used for 106 // the first i64 argument (which must also be the register used to return a 107 // single i64 return value) 108 // 109 // In case that the calling convention does not use the same register for 110 // both, the function should return NULL (does not currently apply) 111 assert(CC != CallingConv::GHC && "should not be GHC calling convention."); 112 return CSR_AArch64_AAPCS_ThisReturn_RegMask; 113 } 114 115 BitVector 116 AArch64RegisterInfo::getReservedRegs(const MachineFunction &MF) const { 117 const AArch64FrameLowering *TFI = getFrameLowering(MF); 118 119 // FIXME: avoid re-calculating this every time. 120 BitVector Reserved(getNumRegs()); 121 Reserved.set(AArch64::SP); 122 Reserved.set(AArch64::XZR); 123 Reserved.set(AArch64::WSP); 124 Reserved.set(AArch64::WZR); 125 126 if (TFI->hasFP(MF) || TT.isOSDarwin()) { 127 Reserved.set(AArch64::FP); 128 Reserved.set(AArch64::W29); 129 } 130 131 if (MF.getSubtarget<AArch64Subtarget>().isX18Reserved()) { 132 Reserved.set(AArch64::X18); // Platform register 133 Reserved.set(AArch64::W18); 134 } 135 136 if (hasBasePointer(MF)) { 137 Reserved.set(AArch64::X19); 138 Reserved.set(AArch64::W19); 139 } 140 141 return Reserved; 142 } 143 144 bool AArch64RegisterInfo::isReservedReg(const MachineFunction &MF, 145 unsigned Reg) const { 146 const AArch64FrameLowering *TFI = getFrameLowering(MF); 147 148 switch (Reg) { 149 default: 150 break; 151 case AArch64::SP: 152 case AArch64::XZR: 153 case AArch64::WSP: 154 case AArch64::WZR: 155 return true; 156 case AArch64::X18: 157 case AArch64::W18: 158 return MF.getSubtarget<AArch64Subtarget>().isX18Reserved(); 159 case AArch64::FP: 160 case AArch64::W29: 161 return TFI->hasFP(MF) || TT.isOSDarwin(); 162 case AArch64::W19: 163 case AArch64::X19: 164 return hasBasePointer(MF); 165 } 166 167 return false; 168 } 169 170 const TargetRegisterClass * 171 AArch64RegisterInfo::getPointerRegClass(const MachineFunction &MF, 172 unsigned Kind) const { 173 return &AArch64::GPR64RegClass; 174 } 175 176 const TargetRegisterClass * 177 AArch64RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const { 178 if (RC == &AArch64::CCRRegClass) 179 return &AArch64::GPR64RegClass; // Only MSR & MRS copy NZCV. 180 return RC; 181 } 182 183 unsigned AArch64RegisterInfo::getBaseRegister() const { return AArch64::X19; } 184 185 bool AArch64RegisterInfo::hasBasePointer(const MachineFunction &MF) const { 186 const MachineFrameInfo *MFI = MF.getFrameInfo(); 187 188 // In the presence of variable sized objects, if the fixed stack size is 189 // large enough that referencing from the FP won't result in things being 190 // in range relatively often, we can use a base pointer to allow access 191 // from the other direction like the SP normally works. 192 // Furthermore, if both variable sized objects are present, and the 193 // stack needs to be dynamically re-aligned, the base pointer is the only 194 // reliable way to reference the locals. 195 if (MFI->hasVarSizedObjects()) { 196 if (needsStackRealignment(MF)) 197 return true; 198 // Conservatively estimate whether the negative offset from the frame 199 // pointer will be sufficient to reach. If a function has a smallish 200 // frame, it's less likely to have lots of spills and callee saved 201 // space, so it's all more likely to be within range of the frame pointer. 202 // If it's wrong, we'll materialize the constant and still get to the 203 // object; it's just suboptimal. Negative offsets use the unscaled 204 // load/store instructions, which have a 9-bit signed immediate. 205 return MFI->getLocalFrameSize() >= 256; 206 } 207 208 return false; 209 } 210 211 unsigned 212 AArch64RegisterInfo::getFrameRegister(const MachineFunction &MF) const { 213 const AArch64FrameLowering *TFI = getFrameLowering(MF); 214 return TFI->hasFP(MF) ? AArch64::FP : AArch64::SP; 215 } 216 217 bool AArch64RegisterInfo::requiresRegisterScavenging( 218 const MachineFunction &MF) const { 219 return true; 220 } 221 222 bool AArch64RegisterInfo::requiresVirtualBaseRegisters( 223 const MachineFunction &MF) const { 224 return true; 225 } 226 227 bool 228 AArch64RegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const { 229 const MachineFrameInfo *MFI = MF.getFrameInfo(); 230 // AArch64FrameLowering::resolveFrameIndexReference() can always fall back 231 // to the stack pointer, so only put the emergency spill slot next to the 232 // FP when there's no better way to access it (SP or base pointer). 233 return MFI->hasVarSizedObjects() && !hasBasePointer(MF); 234 } 235 236 bool AArch64RegisterInfo::requiresFrameIndexScavenging( 237 const MachineFunction &MF) const { 238 return true; 239 } 240 241 bool 242 AArch64RegisterInfo::cannotEliminateFrame(const MachineFunction &MF) const { 243 const MachineFrameInfo *MFI = MF.getFrameInfo(); 244 if (MF.getTarget().Options.DisableFramePointerElim(MF) && MFI->adjustsStack()) 245 return true; 246 return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken(); 247 } 248 249 /// needsFrameBaseReg - Returns true if the instruction's frame index 250 /// reference would be better served by a base register other than FP 251 /// or SP. Used by LocalStackFrameAllocation to determine which frame index 252 /// references it should create new base registers for. 253 bool AArch64RegisterInfo::needsFrameBaseReg(MachineInstr *MI, 254 int64_t Offset) const { 255 for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) 256 assert(i < MI->getNumOperands() && 257 "Instr doesn't have FrameIndex operand!"); 258 259 // It's the load/store FI references that cause issues, as it can be difficult 260 // to materialize the offset if it won't fit in the literal field. Estimate 261 // based on the size of the local frame and some conservative assumptions 262 // about the rest of the stack frame (note, this is pre-regalloc, so 263 // we don't know everything for certain yet) whether this offset is likely 264 // to be out of range of the immediate. Return true if so. 265 266 // We only generate virtual base registers for loads and stores, so 267 // return false for everything else. 268 if (!MI->mayLoad() && !MI->mayStore()) 269 return false; 270 271 // Without a virtual base register, if the function has variable sized 272 // objects, all fixed-size local references will be via the frame pointer, 273 // Approximate the offset and see if it's legal for the instruction. 274 // Note that the incoming offset is based on the SP value at function entry, 275 // so it'll be negative. 276 MachineFunction &MF = *MI->getParent()->getParent(); 277 const AArch64FrameLowering *TFI = getFrameLowering(MF); 278 MachineFrameInfo *MFI = MF.getFrameInfo(); 279 280 // Estimate an offset from the frame pointer. 281 // Conservatively assume all GPR callee-saved registers get pushed. 282 // FP, LR, X19-X28, D8-D15. 64-bits each. 283 int64_t FPOffset = Offset - 16 * 20; 284 // Estimate an offset from the stack pointer. 285 // The incoming offset is relating to the SP at the start of the function, 286 // but when we access the local it'll be relative to the SP after local 287 // allocation, so adjust our SP-relative offset by that allocation size. 288 Offset += MFI->getLocalFrameSize(); 289 // Assume that we'll have at least some spill slots allocated. 290 // FIXME: This is a total SWAG number. We should run some statistics 291 // and pick a real one. 292 Offset += 128; // 128 bytes of spill slots 293 294 // If there is a frame pointer, try using it. 295 // The FP is only available if there is no dynamic realignment. We 296 // don't know for sure yet whether we'll need that, so we guess based 297 // on whether there are any local variables that would trigger it. 298 if (TFI->hasFP(MF) && isFrameOffsetLegal(MI, AArch64::FP, FPOffset)) 299 return false; 300 301 // If we can reference via the stack pointer or base pointer, try that. 302 // FIXME: This (and the code that resolves the references) can be improved 303 // to only disallow SP relative references in the live range of 304 // the VLA(s). In practice, it's unclear how much difference that 305 // would make, but it may be worth doing. 306 if (isFrameOffsetLegal(MI, AArch64::SP, Offset)) 307 return false; 308 309 // The offset likely isn't legal; we want to allocate a virtual base register. 310 return true; 311 } 312 313 bool AArch64RegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, 314 unsigned BaseReg, 315 int64_t Offset) const { 316 assert(Offset <= INT_MAX && "Offset too big to fit in int."); 317 assert(MI && "Unable to get the legal offset for nil instruction."); 318 int SaveOffset = Offset; 319 return isAArch64FrameOffsetLegal(*MI, SaveOffset) & AArch64FrameOffsetIsLegal; 320 } 321 322 /// Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx 323 /// at the beginning of the basic block. 324 void AArch64RegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB, 325 unsigned BaseReg, 326 int FrameIdx, 327 int64_t Offset) const { 328 MachineBasicBlock::iterator Ins = MBB->begin(); 329 DebugLoc DL; // Defaults to "unknown" 330 if (Ins != MBB->end()) 331 DL = Ins->getDebugLoc(); 332 const MachineFunction &MF = *MBB->getParent(); 333 const AArch64InstrInfo *TII = 334 MF.getSubtarget<AArch64Subtarget>().getInstrInfo(); 335 const MCInstrDesc &MCID = TII->get(AArch64::ADDXri); 336 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 337 MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF)); 338 unsigned Shifter = AArch64_AM::getShifterImm(AArch64_AM::LSL, 0); 339 340 BuildMI(*MBB, Ins, DL, MCID, BaseReg) 341 .addFrameIndex(FrameIdx) 342 .addImm(Offset) 343 .addImm(Shifter); 344 } 345 346 void AArch64RegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, 347 int64_t Offset) const { 348 int Off = Offset; // ARM doesn't need the general 64-bit offsets 349 unsigned i = 0; 350 351 while (!MI.getOperand(i).isFI()) { 352 ++i; 353 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 354 } 355 const MachineFunction *MF = MI.getParent()->getParent(); 356 const AArch64InstrInfo *TII = 357 MF->getSubtarget<AArch64Subtarget>().getInstrInfo(); 358 bool Done = rewriteAArch64FrameIndex(MI, i, BaseReg, Off, TII); 359 assert(Done && "Unable to resolve frame index!"); 360 (void)Done; 361 } 362 363 void AArch64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 364 int SPAdj, unsigned FIOperandNum, 365 RegScavenger *RS) const { 366 assert(SPAdj == 0 && "Unexpected"); 367 368 MachineInstr &MI = *II; 369 MachineBasicBlock &MBB = *MI.getParent(); 370 MachineFunction &MF = *MBB.getParent(); 371 const AArch64InstrInfo *TII = 372 MF.getSubtarget<AArch64Subtarget>().getInstrInfo(); 373 const AArch64FrameLowering *TFI = getFrameLowering(MF); 374 375 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 376 unsigned FrameReg; 377 int Offset; 378 379 // Special handling of dbg_value, stackmap and patchpoint instructions. 380 if (MI.isDebugValue() || MI.getOpcode() == TargetOpcode::STACKMAP || 381 MI.getOpcode() == TargetOpcode::PATCHPOINT) { 382 Offset = TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg, 383 /*PreferFP=*/true); 384 Offset += MI.getOperand(FIOperandNum + 1).getImm(); 385 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/); 386 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset); 387 return; 388 } 389 390 // Modify MI as necessary to handle as much of 'Offset' as possible 391 Offset = TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg); 392 if (rewriteAArch64FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII)) 393 return; 394 395 assert((!RS || !RS->isScavengingFrameIndex(FrameIndex)) && 396 "Emergency spill slot is out of reach"); 397 398 // If we get here, the immediate doesn't fit into the instruction. We folded 399 // as much as possible above. Handle the rest, providing a register that is 400 // SP+LargeImm. 401 unsigned ScratchReg = 402 MF.getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass); 403 emitFrameOffset(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, Offset, TII); 404 MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false, true); 405 } 406 407 unsigned AArch64RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, 408 MachineFunction &MF) const { 409 const AArch64FrameLowering *TFI = getFrameLowering(MF); 410 411 switch (RC->getID()) { 412 default: 413 return 0; 414 case AArch64::GPR32RegClassID: 415 case AArch64::GPR32spRegClassID: 416 case AArch64::GPR32allRegClassID: 417 case AArch64::GPR64spRegClassID: 418 case AArch64::GPR64allRegClassID: 419 case AArch64::GPR64RegClassID: 420 case AArch64::GPR32commonRegClassID: 421 case AArch64::GPR64commonRegClassID: 422 return 32 - 1 // XZR/SP 423 - (TFI->hasFP(MF) || TT.isOSDarwin()) // FP 424 - MF.getSubtarget<AArch64Subtarget>() 425 .isX18Reserved() // X18 reserved as platform register 426 - hasBasePointer(MF); // X19 427 case AArch64::FPR8RegClassID: 428 case AArch64::FPR16RegClassID: 429 case AArch64::FPR32RegClassID: 430 case AArch64::FPR64RegClassID: 431 case AArch64::FPR128RegClassID: 432 return 32; 433 434 case AArch64::DDRegClassID: 435 case AArch64::DDDRegClassID: 436 case AArch64::DDDDRegClassID: 437 case AArch64::QQRegClassID: 438 case AArch64::QQQRegClassID: 439 case AArch64::QQQQRegClassID: 440 return 32; 441 442 case AArch64::FPR128_loRegClassID: 443 return 16; 444 } 445 } 446
